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11. 发明授权

US06204786B1 Circuit for the acquisition of binary analog signals 失效
标题翻译：用于采集二进制模拟信号的电路
公开(公告)号：US06204786B1
公开(公告)日：2001-03-20
申请号：US09291044
申请日：1999-04-14
申请人： Philippe Bieth , Christian Pitot , Michel Prost
发明人： Philippe Bieth , Christian Pitot , Michel Prost
IPC分类号： H03M100
CPC分类号： G11C27/024 , H03K3/0377 , H03K5/08 , H03K5/1252
摘要： The disclosure relates to the acquisition of a binary analog signal at input of a digital integrated circuit after its range of voltage variation has been matched with that acceptable by the digital integrated circuit by means of a resistive divider bridge. It is usual to define the architecture of an ASIC digital integrated circuit on the basis of libraries of pre-characterized cells. The disclosed device is designed to increase the possibilities of choice open to the integrated circuit designer, in enabling him to one pre-characterized cell of a Schmitt trigger for its top switching threshold and another for its bottom switching threshold. It consists of a circuit comprising, at input, a bank of Schmitt triggers of different types, followed by a discrete-rendering logic circuit deducing the logic state of the binary input analog signal of the combination of the output states of the input Schmitt triggers.
摘要翻译：本公开涉及在数字集成电路的输入端的电压变化范围已经通过电阻分压器桥接器与数字集成电路可接受的数字匹配之后获取二进制模拟信号。通常在基于预先表征的单元库的基础上定义ASIC数字集成电路的架构。所公开的设备被设计为增加对集成电路设计者的选择开放的可能性，使得他能够使用施密特触发器的一个预先表征的单元作为其顶部切换阈值，另一个用于其底部切换阈值。它包括一个电路，该电路在输入端包括不同类型的施密特触发器组，随后是一个离散渲染逻辑电路，其输出输入施密特触发器的输出状态组合的二进制输入模拟信号的逻辑状态。

12. 发明授权

US5428650A Method and device for selecting information usable by a local unit connected to a digital transmission system 失效
标题翻译：用于选择连接到数字传输系统的本地单元可用的信息的方法和设备
公开(公告)号：US5428650A
公开(公告)日：1995-06-27
申请号：US872382
申请日：1992-04-23
申请人： Christian Pitot
发明人： Christian Pitot
IPC分类号： H04L12/54 , H04L23/00
CPC分类号： H04L12/56
摘要： A method of selecting information usable by a local unit connected to a digital transmission system includes cyclical scanning at fixed frequency of a list of programmed conditions stored in memory, acquisition of information on the transmission channels and activation of a selection process each time that the selection information of a message has been acquired. The selection process comprises a synchronization stage which waits for the scanning process to cross the start of the list of conditions. In a comparison sequence the selection information is compared with the conditions of the list. A selection variable is produced indicating if the message being received is of interest to the local unit or not. The method may be implemented through the use of a highly integrated interface.
摘要翻译：选择连接到数字传输系统的本地单元可使用的信息的方法包括以存储在存储器中的编程状态列表的固定频率的周期性扫描，在传输信道上获取信息并激活选择过程，每次选择消息的信息已经被获取。选择处理包括等待扫描处理跨越条件列表开始的同步阶段。在比较序列中，将选择信息与列表的条件进行比较。产生选择变量，指示正在接收的消息是否对本地单元感兴趣。该方法可以通过使用高度集成的接口来实现。

13. 发明授权

US06943713B1 Process and device for the sequential addressing of the inputs of a multiplexer of a data acquisition circuit 有权
标题翻译：用于数据采集电路的多路复用器的输入的顺序寻址的过程和设备
公开(公告)号：US06943713B1
公开(公告)日：2005-09-13
申请号：US09673666
申请日：2000-03-10
申请人： Christian Pitot , Jean-Michel Chopin
发明人： Christian Pitot , Jean-Michel Chopin
IPC分类号： G06F17/40 , H03M1/00
CPC分类号： G08C15/00
摘要： The systematic, and possibly repeated, acquisition of several distinct quantities for exploitation by a user system by utilizing a multiplexer with staged architecture without all inputs hard-wired. Each multiplexer stage is addressed by an elementary counter chained with elementary counters for addressing lower stages. The multiplexer inputs are scanned by regularly incrementing the chain of counters. If no precaution is taken, all the multiplexer inputs are scanned without considering their possible absences. To remedy this drawback a first elementary counter addresses the first stage of adjustable counting capacity switches, the elementary counters can address intermediate stages of the switches with controllable shunting circuits, and a global counter is reconfigured, at the end of each counting cycle of the first elementary counter, by commands adjusting the first elementary counter capacity, and activating or inhibiting the shunting circuits. The stored commands are a string of instructions executed one by one.
摘要翻译：系统地，可能重复地采集几个不同的数量，以供用户系统利用具有分段架构的多路复用器，而不需要所有输入的硬连线。每个复用器级由基本计数器寻址，用基本计数器链接用于寻址较低级。通过定期递增计数器链来扫描多路复用器输入。如果没有采取预防措施，所有的多路复用器输入都被扫描，而不考虑它们的可能缺席。为了弥补这个缺陷，第一个基本计数器解决了可调计数能力开关的第一阶段，基本计数器可以利用可控制的分流电路解决开关的中间阶段，并且在第一个计数周期的每个计数周期结束时重新配置一个全局计数器基本计数器，通过调整第一基本计数器容量的命令，以及启动或禁止分流电路。存储的命令是逐个执行的指令串。

14. 发明授权

US6046644A Phase-locked loop oscillator formed entirely of logic circuits 失效
标题翻译：锁相环振荡器完全由逻辑电路组成
公开(公告)号：US6046644A
公开(公告)日：2000-04-04
申请号：US165094
申请日：1998-10-02
申请人： Christian Pitot , Michel Prost
发明人： Christian Pitot , Michel Prost
IPC分类号： H03L7/089 , H03L7/099 , H03B5/02 , H03L7/085
CPC分类号： H03L7/089 , H03L7/0995
摘要： Phase-locked loop oscillators that are designed to set the clock rate of electronic circuits based on combinations of logic circuits and to be integrated, at the same time as these electronic circuits, into one and the same chip. There is proposed a phase-locked loop oscillator based purely on combinations of logic circuits so as not to make use of integration techniques different from those used for the electronic circuits based on combinations of logic circuits, for which they are designed to set the clock rate.
摘要翻译：锁相环振荡器被设计为基于逻辑电路的组合来设置电子电路的时钟速率，并且与这些电子电路同时集成到同一个芯片中。提出了一种纯粹基于逻辑电路组合的锁相环振荡器，以便不利用与基于逻辑电路组合的用于电子电路的集成技术不同的集成技术，它们被设计用于设置时钟速率。

15. 发明授权

US5701315A Method and device for protecting the execution of linear sequences of commands performed by a processor 失效
标题翻译：用于保护由处理器执行的线性命令序列的执行的方法和装置
公开(公告)号：US5701315A
公开(公告)日：1997-12-23
申请号：US504113
申请日：1995-07-19
申请人： Christian Pitot , Martinez Michel
发明人： Christian Pitot , Martinez Michel
IPC分类号： G06F12/16 , G06F11/10 , G06F11/28 , G11C29/00
CPC分类号： G06F11/10 , G06F11/1008 , G06F11/28
摘要： A method for detecting errors in a linear sequence of commands executed by a processor and stored in a memory at a predetermined start address, comprises the association of each word in the sequence to a bit of the start address. Before storing each sequence word into the memory, the method determines the value of an unused bit of the word so that the value of the associated bit of the start address will be equal to the result of a predetermined function applied to the bits of the word. When reading a sequence word in said memory, the method compares the result of said function applied to the bits of the word read, with the value of the associated bit of the start address, and transmits an error signal if a difference is detected.
摘要翻译：一种用于检测由处理器执行并存储在存储器中的预定起始地址的命令的线性序列中的错误的方法，包括将序列中的每个字与起始地址的位的关联。在将每个序列字存储到存储器中之前，该方法确定字的未使用位的值，使得起始地址的相关位的值将等于应用于字的位的预定函数的结果。当在所述存储器中读取序列字时，该方法将应用于读取的字的位的所述功能的结果与起始地址的相关位的值进行比较，并且如果检测到差异则发送错误信号。

16. 发明授权

US5375208A Device for managing a plurality of independent queues in a common non-dedicated memory space 失效
标题翻译：用于在公共非专用存储器空间中管理多个独立队列的设备
公开(公告)号：US5375208A
公开(公告)日：1994-12-20
申请号：US872379
申请日：1992-04-23
申请人： Christian Pitot
发明人： Christian Pitot
IPC分类号： G06F5/06 , G06F13/00
CPC分类号： G06F5/065 , G06F2205/066
摘要： A device for managing a plurality of independent queues in a common non-dedicated memory space uses a set of memory space resource use vectors with one vector per managed queue. A vector defines a list of free memory space locations. Read and write pointer registers store the address of memory locations last written or read and a circuit for evaluating the closest successor of these latter memory locations. The device has the advantage of enabling all memory resources to be used, the same resource being usable by any queue.
摘要翻译：用于管理公共非专用存储器空间中的多个独立队列的设备使用一组存储器空间资源使用向量，每个管理队列具有一个向量。向量定义了可用内存空间位置的列表。读写指针寄存器存储最后写入或读取的存储器位置的地址，以及用于评估这些后一个存储器位置的最后继的电路。该设备具有使能所有存储器资源的优点，同一资源可被任何队列使用。

17. 发明授权

US07971109B2 Method for improving the integrity of communication means 有权
标题翻译：提高通信手段完整性的方法
公开(公告)号：US07971109B2
公开(公告)日：2011-06-28
申请号：US12328193
申请日：2008-12-04
申请人： Remi Andreoletti , Christian Pitot , Patrice Toillon
发明人： Remi Andreoletti , Christian Pitot , Patrice Toillon
IPC分类号： G06F11/00
CPC分类号： H04L1/22 , H04L1/20
摘要： Embodiments of the invention enable the integrity of data processed by a switch to be guaranteed better than 10−9 undetected erroneous frames per flight hour. To do this, rules for disabling ports are included in the switch management program. These rules include a maximum absolute admissible number of erroneous frames, to a maximum relative rate of admissible erroneous frames and a minimum number of erroneous frames constituting a significance threshold. Random errors are detected at the level of each frame due to the insertion of a CRC. Deterministic or data-dependent errors able to deceive systematically the CRC check are made random by means of a frame index.
摘要翻译：本发明的实施例使得由开关处理的数据的完整性能够比每个飞行小时的10-9个未检测到的错误帧更好地得到保证。为此，交换机管理程序中包含禁用端口的规则。这些规则包括最大绝对允许的错误帧数，允许错误帧的最大相对速率和构成重要阈值的最小错误帧数。由于插入CRC，在每个帧的级别上检测到随机错误。系统地欺骗CRC校验的确定性或依赖于数据的错误是通过帧索引进行随机的。

18. 发明申请

US20100007527A1 DEVICE AND METHOD FOR DETECTING THE DIGITAL ORIGIN OF AN ANALOGUE SIGNAL 有权
标题翻译：用于检测模拟信号的数字原点的装置和方法
公开(公告)号：US20100007527A1
公开(公告)日：2010-01-14
申请号：US12491821
申请日：2009-06-25
申请人： Christian Pitot , Jacques Phelippeau , Philippe Bieth
发明人： Christian Pitot , Jacques Phelippeau , Philippe Bieth
IPC分类号： G08B21/00 , H04L27/00 , H03D1/00
CPC分类号： G08B29/10
摘要： The present invention relates to an alarm management system intended to be carried onboard an aircraft. More precisely, the invention is aimed at improving the certainty level relating to the integrity of the announcements of faults or information intended for the pilot and based on voice syntheses. For this purpose, the present invention proposes a device and a method for detecting the digital origin of an analog signal providing a validity signal (VAL) enabling the voice announcements made to the pilot to be rendered secure.
摘要翻译：本发明涉及一种旨在承载在飞机上的报警管理系统。更准确地说，本发明的目的在于提高与针对飞行员的故障或信息的公告的完整性相关的确定性水平，并且基于语音合成。为此，本发明提出了一种用于检测提供有效信号（VAL）的模拟信号的数字原点的装置和方法，使得能够使对飞行员的声音通知变得安全。

19. 发明授权

US07184438B2 Task management method for a packet switch routing automaton forming part of a secured packet-switching transmission network 有权
标题翻译：分组交换路由自动机的任务管理方法，形成安全分组交换传输网络的一部分
公开(公告)号：US07184438B2
公开(公告)日：2007-02-27
申请号：US10205399
申请日：2002-07-26
申请人： Alain Loge , Christian Pitot
发明人： Alain Loge , Christian Pitot
IPC分类号： H04L12/28
CPC分类号： H04L49/309 , H04Q11/0478
摘要： This method consists in making a routing automaton carry out verifications on the integrity of the packets arriving at the packet switch, their periods of stay in the packet switch, their matching with the virtual paths that they claim to take as well as the routings proper, within the packet switch, of the datagrams that have satisfactorily undergone the verification. The routing automaton is provided with a random access memory of instructed values containing a table of virtual path local descriptors. The processing time of the automaton is divided into a repetitive sequence of time slots individually allocated to the different input ports of the packet switch.
摘要翻译：该方法包括使路由自动机对分组交换机到达的分组的完整性，分组交换机的停留时间，与所声称的虚拟路径的匹配以及适当的路由进行验证，在分组交换机内，已经令人满意地进行验证的数据报。路由自动机具有包含虚拟路径局部描述符表的指示值的随机存取存储器。自动机的处理时间被分为分别分配给分组交换机的不同输入端口的时隙的重复序列。

20. 发明授权

US06571300B2 Offset autonomous input/output controller with time slots allocation 有权
标题翻译：偏移具有时隙分配的自主输入/输出控制器
公开(公告)号：US06571300B2
公开(公告)日：2003-05-27
申请号：US09331171
申请日：1999-06-21
申请人： Christian Pitot , Olivier Le Borgne
发明人： Christian Pitot , Olivier Le Borgne
IPC分类号： G06F300
CPC分类号： G06F11/1008 , G06F9/3877
摘要： An input/output controller interacts with a central processing unit of a computer which communicates with peripheral electronic equipment. The link with the central processor unit is produced with an input serial line and at least one output serial line. It receives instructions of a first type from the central processing unit and instructions of at least a second kind which are stored in the memory external to the central processing unit. These are processed using a sequencer device which allocates time slots to the instructions according to their type. This device is especially useful in the field of avionics and flight management systems.
摘要翻译：输入/输出控制器与与外围电子设备通信的计算机的中央处理单元进行交互。与中央处理器单元的链接由输入串行线和至少一个输出串行线产生。它从中央处理单元接收第一类型的指令，并且存储在中央处理单元外部的存储器中的至少第二类型的指令。这些使用定序器装置进行处理，该定序器装置根据它们的类型向指令分配时隙。该设备在航空电子和飞行管理系统领域尤其有用。

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