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11. 发明授权

US08090019B2 Intra prediction circuit device applied to the H.264 video coding standard 有权
标题翻译：帧内预测电路设备应用于H.264视频编码标准
公开(公告)号：US08090019B2
公开(公告)日：2012-01-03
申请号：US11517348
申请日：2006-09-08
申请人： Jiun-In Guo , Jinn-Shyan Wang , Jia-Wei Chen
发明人： Jiun-In Guo , Jinn-Shyan Wang , Jia-Wei Chen
IPC分类号： H04N7/12 , H04N11/02
CPC分类号： H04N19/42 , H04N19/11 , H04N19/176 , H04N19/61
摘要： An intra prediction circuit device applied to the H.264 video coding standard is provided. The intra prediction device uses a method of decreasing the repeated operations of the shared terms of the video pixel data to reduce the circuit computation and simplify the hardware architecture. In the intra prediction scheme, the computational complexity can be lessened by implementing not only the adder based method but also decomposition technique to simplify the algorithm of the intra prediction.
摘要翻译：提供了应用于H.264视频编码标准的帧内预测电路装置。帧内预测装置使用减少视频像素数据的共享项的重复操作以减少电路计算并简化硬件体系结构的方法。在帧内预测方案中，通过不仅采用基于加法器的方法，而且通过实现分解技术来简化帧内预测算法，可以减少计算复杂度。

12. 发明申请

US20110299596A1 Fractional motion estimation method with adaptive mode selection 审中-公开
标题翻译：具有自适应模式选择的分数运动估计方法
公开(公告)号：US20110299596A1
公开(公告)日：2011-12-08
申请号：US12805902
申请日：2010-08-24
申请人： Jiun-In Guo , Chih-Chuan Yang , Yao-Chang Yang
发明人： Jiun-In Guo , Chih-Chuan Yang , Yao-Chang Yang
IPC分类号： H04N7/26
CPC分类号： H04N19/567 , H04N19/105 , H04N19/147 , H04N19/176 , H04N19/196 , H04N19/197 , H04N19/523
摘要： A fractional motion estimation method including the steps of categorizing search modes of the macroblock into a single mode, a reduced mode, and a full mode; determining a search mode of a to-be-process macroblock according to a predetermined condition; and conducting a fractional motion estimation of a to-be-estimated pixel according to the search mode determined in the aforesaid step. Therefore, the fractional motion estimation method can have the adaptive mode selection to spare some parts of computation for low throughput. In other words, it can effectively enhance efficiency of hardware, to lower power consumption, and to maintain consistent image quality.
摘要翻译：一种分数运动估计方法，包括以下步骤：将宏块的搜索模式分类为单个模式，简化模式和全模式; 根据预定条件确定待处理宏块的搜索模式; 以及根据在上述步骤中确定的搜索模式进行待估计像素的分数运动估计。因此，分数运动估计方法可以具有自适应模式选择，以节省一些低吞吐量的计算。换句话说，它可以有效提高硬件的效率，降低功耗，并保持一致的图像质量。

13. 发明授权

US07724975B2 Design techniques and their circuit designs for versatile and scalable video coding 有权
标题翻译：设计技术及其电路设计，用于多功能和可扩展的视频编码
公开(公告)号：US07724975B2
公开(公告)日：2010-05-25
申请号：US11472344
申请日：2006-06-22
申请人： Jiun-In Guo , Kuan-Hung Chen , Jinn-Shyan Wang
发明人： Jiun-In Guo , Kuan-Hung Chen , Jinn-Shyan Wang
IPC分类号： G06K9/36
CPC分类号： H04N19/436 , H04N19/60 , H04N19/61
摘要： Design techniques and their circuit designs for versatile and scalable video coding are proposed, in which the inner product operation in the transform coding expression is taken apart into a series of add and shift operations, and the expression is partitioned into several sub-expressions. Taking each order of the add-and-shift series as a clock period, several adders/subtractors and a shift accumulator are used to carry out corresponding additions/subtractions and shift operations to finish the inner product operations. The calculating result is accumulated until all the orders are finished. The final accumulated value is the output of the transform coding. Data throughput rate can thus be enhanced to save the power consumption of the circuit system. Moreover, a dynamic guarded computation method and a switching power suppression technique are provided to further lower the power consumption.
摘要翻译：提出了通用和可扩展视频编码的设计技术及其电路设计，其中将变换编码表达式中的内部产品操作分为一系列的加法和移位操作，并将表达式划分为几个子表达式。将加/运系列的每个顺序作为时钟周期，使用多个加法器/减法器和移位累加器来执行相应的加法/减法和移位操作以完成内部产品操作。累计计算结果，直到所有订单完成。最终累积值是变换编码的输出。因此可以提高数据吞吐率，以节省电路系统的功耗。此外，提供动态保护计算方法和开关功率抑制技术以进一步降低功耗。

14. 发明授权

US07339507B1 Device for video decoding 有权
标题翻译：视频解码设备
公开(公告)号：US07339507B1
公开(公告)日：2008-03-04
申请号：US11519922
申请日：2006-09-13
申请人： Jiun-In Guo , Yao-Chang Yang
发明人： Jiun-In Guo , Yao-Chang Yang
IPC分类号： H30M7/00 , H04N11/02
CPC分类号： H04N19/42 , H04N19/13 , H04N19/61
摘要： A device for video decoding is disclosed. It includes at least a pipeline scheduler, a decoding core, a segmented context memory and a context cache. The pipeline scheduler and the decoding core could decrease the time taken in a code-decoding period. The segmented context memory and the context cache could reduce accessing time of reading and writing context values.
摘要翻译：公开了一种用于视频解码的设备。它至少包括流水线调度器，解码核心，分段上下文存储器和上下文高速缓存。流水线调度器和解码核心可以减少码译码周期所花费的时间。分段上下文存储器和上下文高速缓存可以减少读取和写入上下文值的访问时间。

15. 发明申请

US20070297500A1 Design techniques and their circuit designs for versatile and scalable video coding 有权
标题翻译：设计技术及其电路设计，用于多功能和可扩展的视频编码
公开(公告)号：US20070297500A1
公开(公告)日：2007-12-27
申请号：US11472344
申请日：2006-06-22
申请人： Jiun-In Guo , Kuan-Hung Chen , Jinn-Shyan Wang
发明人： Jiun-In Guo , Kuan-Hung Chen , Jinn-Shyan Wang
IPC分类号： H04B1/66
CPC分类号： H04N19/436 , H04N19/60 , H04N19/61
摘要： Design techniques and their circuit designs for versatile and scalable video coding are proposed, in which the inner product operation in the transform coding expression is taken apart into a series of add and shift operations, and the expression is partitioned into several sub-expressions. Taking each order of the add-and-shift series as a clock period, several adders/subtractors and a shift accumulator are used to carry out corresponding additions/subtractions and shift operations to finish the inner product operations. The calculating result is accumulated until all the orders are finished. The final accumulated value is the output of the transform coding. Data throughput rate can thus be enhanced to save the power consumption of the circuit system. Moreover, a dynamic guarded computation method and a switching power suppression technique are provided to further lower the power consumption.
摘要翻译：提出了通用和可扩展视频编码的设计技术及其电路设计，其中将变换编码表达式中的内部产品操作分为一系列的加法和移位操作，并将表达式划分为几个子表达式。将加/运系列的每个顺序作为时钟周期，使用多个加法器/减法器和移位累加器来执行相应的加法/减法和移位操作以完成内部产品操作。累计计算结果，直到所有订单完成。最终累积值是变换编码的输出。因此可以提高数据吞吐率，以节省电路系统的功耗。此外，提供动态保护计算方法和开关功率抑制技术以进一步降低功耗。

16. 发明申请

US20050004963A1 Parallel adder-based DCT/IDCT design using cyclic convolution 有权
标题翻译：基于并行加法器的DCT / IDCT设计采用循环卷积
公开(公告)号：US20050004963A1
公开(公告)日：2005-01-06
申请号：US10897486
申请日：2004-07-23
申请人： Jiun-In Guo , Kun-Wang Liu
发明人： Jiun-In Guo , Kun-Wang Liu
IPC分类号： G06F17/14
CPC分类号： G06F7/76 , G06F17/147
摘要： The present invention provides a device and method for applying 1-D and 2-D DCT and IDCT transforms to sets of input data, typically 8×8 or 16×16 matrices of coefficients. In one embodiment, the present invention provides input lines, logic to pre-add input values and generate operands and one or more adder networks that effectively carry out the multiplication operations required to apply a DCT/IDCT transform: The device may apply a 1-D transform twice to accomplish a 2-D transform. Alternatively, the present invention may either include successive stages of logic for the second 1-D transform or it may send data transformed once back through the same logic to pre-add and adder networks for the second 1-D transform. Calculations may be carried out after Booth encoding of operands. The processing may be split between producing vp, a vector of sums of output values, and producing vn, a vector of differences of output values, which vectors may be recombined to produce an output vector v.
摘要翻译：本发明提供一种用于将1-D和2-D DCT和IDCT变换应用于一组输入数据（通常为8×8或16×16个系数矩阵）的装置和方法。在一个实施例中，本发明提供输入线，用于预先添加输入值并产生操作数的逻辑，以及有效地执行应用DCT / IDCT变换所需的相乘操作的一个或多个加法器网络。该装置可以应用1- D转换两次以完成2-D变换。或者，本发明可以包括用于第二个1-D变换的连续的逻辑级，或者可以将通过相同的逻辑转换的数据一次发送到用于第二个1-D变换的预加和加法网络。计算可以在布尔编码操作数后进行。可以在产生vp，输出值之和的矢量和产生vn，输出值差的向量之间分割处理，该向量可以被重组以产生输出向量v。

17. 发明授权

US07464230B2 Memory controlling method 有权
公开(公告)号：US07464230B2
公开(公告)日：2008-12-09
申请号：US11517410
申请日：2006-09-08
申请人： Jiun-In Guo , Chih-Ta Chien , Chia-Jui Huang
发明人： Jiun-In Guo , Chih-Ta Chien , Chia-Jui Huang
IPC分类号： G06F12/00
CPC分类号： G06F12/0207 , G06F13/161 , Y02D10/13 , Y02D10/14
摘要： A method for memory controlling is disclosed. It includes an embedded address generator and a controlling scheme of burst terminates burst, which could erase the latency caused by bus interface during the access of non-continuous addresses. Moreover, it includes a controlling scheme of anticipative row activating, which could reduce the latency across different rows of memory by data access. The method could improve the access efficiency and power consumption of memory.

18. 发明申请

US20080056355A1 Method for reducing computational complexity of video compression standard 有权
标题翻译：降低视频压缩标准计算复杂度的方法
公开(公告)号：US20080056355A1
公开(公告)日：2008-03-06
申请号：US11512287
申请日：2006-08-30
申请人： Jiun-In Guo , Jinn-Shyan Wang , Jia-Wei Chen , Chun-Hao Chang , Yi-Huan Ou Yang
发明人： Jiun-In Guo , Jinn-Shyan Wang , Jia-Wei Chen , Chun-Hao Chang , Yi-Huan Ou Yang
IPC分类号： H04N7/12 , H04N11/04
CPC分类号： H04N19/11 , H04N19/176
摘要： A method for reducing computational complexity of video compression standard is provided, and it includes an intra 4×4 macroblock (I4MB) search algorithm, an intra 16×16 macroblock (I16MB) search algorithm and a chroma search algorithm. The I4MB search algorithm and I16MB search algorithm accelerate the prediction process of the luma macroblock, and the chroma search algorithm accelerates the prediction process of chroma macroblock. The above algorithms can greatly reduce the computation of prediction mode of video compression standard.
摘要翻译：提供了一种降低视频压缩标准的计算复杂度的方法，包括内部4×4宏块（I4MB）搜索算法，帧内16×16宏块（I16MB）搜索算法和色度搜索算法。 I4MB搜索算法和I16MB搜索算法加速了亮度宏块的预测过程，色度搜索算法加速了色度宏块的预测过程。上述算法可以大大减少视频压缩标准预测模式的计算。

19. 发明申请

US20070094320A1 Parallel Adder-Based DCT / IDCT Design Using Cyclic Convolution 审中-公开
标题翻译：基于平行加法器的DCT / IDCT设计使用循环卷积
公开(公告)号：US20070094320A1
公开(公告)日：2007-04-26
申请号：US11538017
申请日：2006-10-02
申请人： Jiun-In Guo , Kun-Wang Liu
发明人： Jiun-In Guo , Kun-Wang Liu
IPC分类号： G06F7/38
CPC分类号： G06F7/76 , G06F17/147
摘要： A device and method are described that apply 1-D and 2-D discrete cosine transforms (DCT) and inverse discrete cosine transforms (IDCT) to sets of input data, typically 8×8 or 16×16 matricies of coefficients. One device includes input lines, logic to pre-add input values and generate operands and one or more adder networks that effectively carry out the multiplication operations required to apply a DCT/IDCT transform. The device may apply a 1-D transform twice to accomplish a 2-D transform. Alternatively, the device may either include successive stages of logic for the second 1-D transform or it may send data transformed once back through the same logic to pre-add and adder networks for the second 1-D transform. Calculations may be carried out after Booth encoding of operands. The processing may be split between producing vp, a vector of sums of output values, and producing vn, a vector of differences of output values, which vectors may be recombined to produce an output vector v.
摘要翻译：描述了将1-D和2-D离散余弦变换（DCT）和反相离散余弦变换（IDCT）应用于输入数据集合（通常为8×8或16×16系数系数）的装置和方法。一个设备包括输入线，用于预先添加输入值的逻辑和生成操作数的逻辑，以及有效地执行应用DCT / IDCT变换所需的乘法运算的一个或多个加法器网络。该设备可以应用1-D变换两次来完成2-D变换。或者，该设备可以包括用于第二个1-D变换的连续的逻辑级，或者它可以将通过相同的逻辑转换的数据经过一次转换为用于第二个1-D变换的预加和加法器网络。计算可以在布尔编码操作数后进行。该处理可以在生成输出值之和的向量和产生v N n N之间进行分割，输出值的差异向量可以被重新组合以产生输出向量v。

20. 发明申请

US20080219350A1 H.264/AVC intra coding algorithms having quality scalability 审中-公开
标题翻译：具有质量可扩展性的H.264 / AVC帧内编码算法
公开(公告)号：US20080219350A1
公开(公告)日：2008-09-11
申请号：US11812247
申请日：2007-06-15
申请人： Jiun-In Guo , Jia-Wei Chen , Chun-Hao Chang
发明人： Jiun-In Guo , Jia-Wei Chen , Chun-Hao Chang
IPC分类号： H04N7/26
CPC分类号： H04N19/103 , H04N19/136 , H04N19/156 , H04N19/60
摘要： Different algorithms are used in H.264/AVC intra coding to form three coding levels. Algorithms used in two of the three coding levels reduce calculation complexities and power consumptions. The basic level is an exception, which fully keeps an original picture quality. Thus, various needs can be met by coding in the various levels with the various algorithms.
摘要翻译：在H.264 / AVC帧内编码中使用不同的算法来形成三个编码级别。在三个编码级别中的两个中使用的算法降低了计算复杂度和功耗。基本水平是一个例外，完全保持原始图片质量。因此，通过使用各种算法在各个层次中进行编码可以满足各种需要。

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