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11. 发明申请

US20130257498A1 Pulse Clock Generation Logic with Built-in Level Shifter and Programmable Rising Edge and Pulse Width 有权
标题翻译：具有内置电平移位器和可编程上升沿和脉冲宽度的脉冲时钟生成逻辑
公开(公告)号：US20130257498A1
公开(公告)日：2013-10-03
申请号：US13433891
申请日：2012-03-29
申请人： Shaoping Ge , Chiaming Chai , Stephen Edward Liles , Lam V. Nguyen , Jeffrey Herbert Fischer
发明人： Shaoping Ge , Chiaming Chai , Stephen Edward Liles , Lam V. Nguyen , Jeffrey Herbert Fischer
IPC分类号： H03K5/01
CPC分类号： G06F1/04 , G11C7/222 , G11C11/417 , G11C11/418 , G11C11/419
摘要： Systems and methods for generating pulse clocks with programmable edges and pulse widths configured for varying requirements of different memory access operations. A pulse clock generation circuit includes a selective delay logic to provide a programmable rising edge delay of the pulse clock, a selective pulse width widening logic to provide a programmable pulse width of the pulse clock, and a built-in level shifter for shifting a voltage level of the pulse clock. A rising edge delay for a read operation is programmed to correspond to an expected read array access delay, and the pulse width for a write operation is programmed to be wider than the pulse width for a read operation.
摘要翻译：用于产生具有可编程边沿和脉冲宽度的脉冲时钟的系统和方法被配置用于不同存储器访问操作的不同需求。脉冲时钟产生电路包括提供脉冲时钟的可编程上升沿延迟的选择性延迟逻辑，提供脉冲时钟可编程脉冲宽度的选择性脉宽扩展逻辑，以及内置电平转换器，脉冲时钟电平。读操作的上升沿延迟被编程为对应于期望的读数组访问延迟，并且用于写操作的脉冲宽度被编程为比读操作的脉冲宽度宽。

12. 发明申请

US20130182514A1 Mimicking Multi-Voltage Domain Wordline Decoding Logic for a Memory Array 有权
标题翻译：模拟存储器阵列的多电压域字线解码逻辑
公开(公告)号：US20130182514A1
公开(公告)日：2013-07-18
申请号：US13424833
申请日：2012-03-20
申请人： Shaoping Ge , Chiaming Chai , Stephen E. Liles , Lam V. Nguyen , Jeffrey Herbert Fischer
发明人： Shaoping Ge , Chiaming Chai , Stephen E. Liles , Lam V. Nguyen , Jeffrey Herbert Fischer
IPC分类号： G11C7/12 , G11C8/10 , G11C7/00
CPC分类号： G11C8/08 , G11C7/12 , G11C7/22 , G11C7/227 , G11C8/10
摘要： Systems and methods for adaptively mimicking wordline decoding logic for multi-voltage domain memory are disclosed. In one embodiment, the multi-voltage domain memory includes a memory array implemented in a high voltage domain and a multi-voltage domain control circuit. The multi-voltage domain control circuit includes multi-voltage domain decoding logic that generates a wordline for the memory array and a multi-voltage domain mimic logic that mimics the multi-voltage domain decoding logic to generate a dummy wordline. In one embodiment, the dummy wordline is utilized to trigger an ending edge (e.g., a falling edge) of the wordline once the wordline is asserted. In addition or alternatively, the dummy wordline is utilized to generate one or more control signals for the memory array such as, for example, a pre-charge control signal and/or a sense amplifier enable signal.
摘要翻译：公开了用于自适应模拟用于多电压域存储器的字线解码逻辑的系统和方法。在一个实施例中，多电压域存储器包括以高电压域实现的存储器阵列和多电压域控制电路。多电压域控制电路包括生成用于存储器阵列的字线的多电压域解码逻辑和模拟多电压域解码逻辑以产生伪字线的多电压域模拟逻辑。在一个实施例中，一旦确定了字线，就使用伪字线来触发字线的结束边缘（例如，下降沿）。另外或替代地，伪字线用于产生用于存储器阵列的一个或多个控制信号，例如预充电控制信号和/或读出放大器使能信号。

13. 发明申请

US20110227639A1 Method and Apparatus for Suppressing Bitline Coupling Through Miller Capacitance to a Sense Amplifier Interstitial Node 审中-公开
标题翻译：用于通过米勒电容抑制位线耦合到感测放大器间隙节点的方法和装置
公开(公告)号：US20110227639A1
公开(公告)日：2011-09-22
申请号：US12727833
申请日：2010-03-19
申请人： Michael ThaiThanh Phan , Chiaming Chai , Manish Garg
发明人： Michael ThaiThanh Phan , Chiaming Chai , Manish Garg
IPC分类号： G06G7/00 , H03F3/45
CPC分类号： G11C7/02 , G11C7/065
摘要： A sense amplifier circuit is implemented for suppressing Miller effect capacitive coupling. The amplifier circuit comprises a differential amplifier circuit having a first input, a first output interstitial node, a second input, a second output interstitial node, a third input to enable or disable the differential amplifier, and having an equalizer circuit coupled between the first output interstitial node and the second output interstitial node. The amplifier circuit also comprises a cross coupled latch circuit having a first latch input coupled to the first output interstitial node, a second latch input coupled to the second output interstitial node, a first latch output, and a second latch output, wherein during a first time period the first latch output and the second latch output are precharged, the differential amplifier circuit is disabled, and the equalizer circuit is enabled to suppress the Miller effect capacitive coupling on the sense amplifier inputs.
摘要翻译：实现了一种用于抑制米勒效应电容耦合的读出放大器电路。所述放大器电路包括差分放大器电路，所述差分放大器电路具有第一输入端，第一输出间隙节点，第二输入端，第二输出间隙型节点，第三输入端，用于使能或禁止差分放大器，以及具有耦合在第一输出端间质性节点和第二输出间质性节点。放大器电路还包括交叉耦合的锁存电路，其具有耦合到第一输出间隙节点的第一锁存器输入，耦合到第二输出间隙节点的第二锁存器输入，第一锁存器输出和第二锁存器输出，其中在第一第一锁存器输出和第二锁存器输出被预充电的时间段，差分放大器电路被禁止，并且均衡器电路被使能以抑制在感测放大器输入上的米勒效应电容耦合。

14. 发明授权

US08008961B2 Adaptive clock generators, systems, and methods 有权
标题翻译：自适应时钟发生器，系统和方法
公开(公告)号：US08008961B2
公开(公告)日：2011-08-30
申请号：US12637321
申请日：2009-12-14
申请人： Manish Garg , Chiaming Chai , Jeffrey Todd Bridges
发明人： Manish Garg , Chiaming Chai , Jeffrey Todd Bridges
IPC分类号： H03K3/00
CPC分类号： H03K3/0315 , H03K2005/00058 , H03K2005/00215
摘要： Adaptive clock generators, systems, and related methods than can be used to generate a clock signal for a functional circuit to avoid or reduce performance margin are disclosed. In certain embodiments, a clock generator autonomously and adaptively generates a clock signal according to a delay path(s) provided in a delay circuit(s) relating to a selected delay path(s) in the functional circuit(s). The clock generator includes a delay circuit(s) adapted to receive an input signal and delay the input signal by an amount relating to a delay path(s) of a functional circuit(s) to produce an output signal. A feedback circuit is coupled to the delay circuit(s) and responsive to the output signal, wherein the feedback circuit is adapted to generate the input signal back to the delay circuit(s) in an oscillation loop configuration. The input signal can be used to provide a clock signal to the functional circuit(s).
摘要翻译：公开了可用于生成用于功能电路的时钟信号以避免或降低性能裕度的自适应时钟发生器，系统和相关方法。在某些实施例中，时钟发生器根据在与功能电路中所选择的延迟路径相关的延迟电路中提供的延迟路径来自主地且自适应地生成时钟信号。时钟发生器包括适于接收输入信号并将输入信号延迟与功能电路的延迟路径相关的量以产生输出信号的延迟电路。反馈电路耦合到延迟电路并响应于输出信号，其中反馈电路适于在振荡环路配置中产生回到延迟电路的输入信号。输入信号可用于向功能电路提供时钟信号。

15. 发明授权

US06816396B2 Apparatus for detecting multiple hits in a CAMRAM memory array 失效
标题翻译：用于检测CAMRAM存储器阵列中的多个命中的装置
公开(公告)号：US06816396B2
公开(公告)日：2004-11-09
申请号：US10405736
申请日：2003-04-01
申请人： Chiaming Chai , Jeffrey Herbert Fischer , Michael Thaithanh Phan , Joel Abraham Silberman
发明人： Chiaming Chai , Jeffrey Herbert Fischer , Michael Thaithanh Phan , Joel Abraham Silberman
IPC分类号： G11C1500
CPC分类号： G11C15/00
摘要： A CAMRAM capable of detecting multiple hit is disclosed. The CAMRAM includes a random address memory, a content-addressable memory, a set of index address lines and a set of multiple-hit detection address lines. The index address lines and the multiple-hit detection address lines are complementarily connected to a set of matchlines via transistors. Coupled to the index address lines and the multiple-hit detection address lines, a comparator circuit is capable of outputting a multi-hit signal when more than one of the matchlines are turned on simultaneously during an address comparison operation.
摘要翻译：公开了一种能够检测多次命中的CAMRAM。 CAMRAM包括随机地址存储器，内容寻址存储器，一组索引地址线和一组多命中检测地址线。索引地址线和多命中检测地址线通过晶体管互补地连接到一组匹配线。耦合到索引地址线和多命中检测地址线，当地址比较操作期间多于一条匹配线同时导通时，比较器电路能够输出多命中信号。

16. 发明授权

US08576612B2 Low leakage high performance static random access memory cell using dual-technology transistors 有权
标题翻译：低泄漏高性能静态随机存取存储单元采用双工晶体管
公开(公告)号：US08576612B2
公开(公告)日：2013-11-05
申请号：US13102961
申请日：2011-05-06
申请人： Manish Garg , Chiaming Chai , Michael ThaiThanh Phan
发明人： Manish Garg , Chiaming Chai , Michael ThaiThanh Phan
IPC分类号： G11C11/00
CPC分类号： G11C11/419 , G11C8/08
摘要： A memory cell includes a storage element, a write circuit coupled to the storage element and a read circuit coupled to the storage element. At least a portion of the storage element and at least a portion of the write circuit are fabricated using a thicker functional gate oxide and at least a portion of the read circuit is fabricated using a thinner functional gate oxide.
摘要翻译：存储单元包括存储元件，耦合到存储元件的写入电路和耦合到存储元件的读取电路。使用较厚的功能栅极氧化物制造存储元件的至少一部分和写入电路的至少一部分，并且使用更薄的功能栅极氧化物制造读取电路的至少一部分。

17. 发明授权

US08154900B2 Method and apparatus for reducing power consumption in a content addressable memory 有权
标题翻译：用于降低内容可寻址存储器中的功耗的方法和装置
公开(公告)号：US08154900B2
公开(公告)日：2012-04-10
申请号：US12569537
申请日：2009-09-29
申请人： Chiaming Chai , Jeffrey Herbert Fischer , Michael Thai Thanh Phan
发明人： Chiaming Chai , Jeffrey Herbert Fischer , Michael Thai Thanh Phan
IPC分类号： G11C15/00
CPC分类号： G11C15/04
摘要： Power consumption in a Content Addressable Memory (CAM) circuit is reduced by use of a CAM circuit. According to one embodiment of the CAM circuit, the CAM circuit includes a plurality of match lines and match line restoration circuitry. The match line restoration circuitry is configured to prevent at least one of the match lines from being restored to a pre-evaluation state responsive to corresponding enable information.
摘要翻译：通过使用CAM电路可以减少内容寻址存储器（CAM）电路中的功耗。根据CAM电路的一个实施例，CAM电路包括多个匹配线和匹配线恢复电路。匹配线路恢复电路被配置为响应于相应的启用信息来防止至少一个匹配线路恢复到预评估状态。

18. 发明申请

US20110140752A1 Adaptive Clock Generators, Systems, and Methods 有权
标题翻译：自适应时钟发生器，系统和方法
公开(公告)号：US20110140752A1
公开(公告)日：2011-06-16
申请号：US12637321
申请日：2009-12-14
申请人： Manish Garg , Chiaming Chai , Jeffrey Todd Bridges
发明人： Manish Garg , Chiaming Chai , Jeffrey Todd Bridges
IPC分类号： H03K3/00
CPC分类号： H03K3/0315 , H03K2005/00058 , H03K2005/00215
摘要： Adaptive clock generators, systems, and related methods than can be used to generate a clock signal for a functional circuit to avoid or reduce performance margin are disclosed. In certain embodiments, a clock generator autonomously and adaptively generates a clock signal according to a delay path(s) provided in a delay circuit(s) relating to a selected delay path(s) in the functional circuit(s). The clock generator includes a delay circuit(s) adapted to receive an input signal and delay the input signal by an amount relating to a delay path(s) of a functional circuit(s) to produce an output signal. A feedback circuit is coupled to the delay circuit(s) and responsive to the output signal, wherein the feedback circuit is adapted to generate the input signal back to the delay circuit(s) in an oscillation loop configuration. The input signal can be used to provide a clock signal to the functional circuit(s).
摘要翻译：公开了可用于生成用于功能电路的时钟信号以避免或降低性能裕度的自适应时钟发生器，系统和相关方法。在某些实施例中，时钟发生器根据在与功能电路中所选择的延迟路径相关的延迟电路中提供的延迟路径来自主地且自适应地生成时钟信号。时钟发生器包括适于接收输入信号并将输入信号延迟与功能电路的延迟路径相关的量以产生输出信号的延迟电路。反馈电路耦合到延迟电路并响应于输出信号，其中反馈电路适于在振荡环路配置中产生回到延迟电路的输入信号。输入信号可用于向功能电路提供时钟信号。

19. 发明授权

US07961499B2 Low leakage high performance static random access memory cell using dual-technology transistors 有权
标题翻译：低泄漏高性能静态随机存取存储单元采用双工晶体管
公开(公告)号：US07961499B2
公开(公告)日：2011-06-14
申请号：US12357938
申请日：2009-01-22
申请人： Manish Garg , Chiaming Chai , Michael ThaiThanh Phan
发明人： Manish Garg , Chiaming Chai , Michael ThaiThanh Phan
IPC分类号： G11C11/00
CPC分类号： G11C11/419 , G11C8/08
摘要： A memory cell includes a storage element, a write circuit coupled to the storage element and a read circuit coupled to the storage element. At least a portion of the storage element and at least a portion of the write circuit are fabricated using a thicker functional gate oxide and at least a portion of the read circuit is fabricated using a thinner functional gate oxide.
摘要翻译：存储单元包括存储元件，耦合到存储元件的写入电路和耦合到存储元件的读取电路。使用较厚的功能栅极氧化物制造存储元件的至少一部分和写入电路的至少一部分，并且使用更薄的功能栅极氧化物制造读取电路的至少一部分。

20. 发明申请

US20100148839A1 Self-Tuning Of Signal Path Delay In Circuit Employing Multiple Voltage Domains 有权
标题翻译：信号路径延迟自适应采用多电压域的电路
公开(公告)号：US20100148839A1
公开(公告)日：2010-06-17
申请号：US12336741
申请日：2008-12-17
申请人： Chiaming Chai , Stephen Edward Liles
发明人： Chiaming Chai , Stephen Edward Liles
IPC分类号： H03H11/26
CPC分类号： G11C7/08 , G11C7/22 , G11C7/222 , G11C11/413 , G11C11/417 , G11C11/419
摘要： Circuits and methods provided in multiple voltage domains that include self-tuning or timing of a signal path are disclosed. A plurality of paths is provided in the circuit. Each path traverses a portion of the multiple voltage domains, which may include any number or combination of the multiple voltage domains. Each of the paths has a delay responsive to at least one of the plurality of voltage domains. A delay circuit is provided and configured to generate a delay output related to the delay in the plurality of paths. In this manner, the delay output of the delay circuit is self-tuned or adjusted according to the delay in the plurality of paths. This self-tuning may be particularly suited to control the delay of a first signal path relative to a second signal path wherein the delay in the paths can vary with respect to each other during operation.
摘要翻译：公开了包括信号路径的自整定或定时在多个电压域中提供的电路和方法。在电路中提供多个路径。每个路径遍及多个电压域的一部分，其可以包括多个电压域的任何数量或组合。每个路径具有响应于多个电压域中的至少一个的延迟。延迟电路被提供并被配置为产生与多个路径中的延迟相关的延迟输出。以这种方式，延迟电路的延迟输出根据多个路径中的延迟进行自调谐或调整。该自整定可以特别适合于控制相对于第二信号路径的第一信号路径的延迟，其中路径中的延迟在操作期间可以相对于彼此而变化。

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