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11. 发明申请

US20120094464A1 Method of Fabricating Semiconductor Device Isolation Structure 审中-公开
标题翻译：制造半导体器件隔离结构的方法
公开(公告)号：US20120094464A1
公开(公告)日：2012-04-19
申请号：US13336887
申请日：2011-12-23
申请人： Chen-Hua Yu , Chen-Nan Yeh , Chu-Yun Fu , Ding-Yuan Chen
发明人： Chen-Hua Yu , Chen-Nan Yeh , Chu-Yun Fu , Ding-Yuan Chen
IPC分类号： H01L21/762
CPC分类号： H01L21/76202 , H01L21/26506 , H01L21/26533 , H01L21/26586 , H01L21/266 , H01L21/324 , H01L21/762 , H01L21/823481 , H01L29/0649 , H01L29/6659 , H01L29/7833
摘要： A semiconductor device including reentrant isolation structures and a method for making such a device. A preferred embodiment comprises a substrate of semiconductor material forming at least one isolation structure having a reentrant profile and isolating one or more adjacent operational components. The reentrant profile of the at least one isolation structure is formed of substrate material and is created by ion implantation, preferably using oxygen ions applied at a number of different angles and energy levels. In another embodiment the present invention is a method of forming an isolation structure for a semiconductor device performing at least one oxygen ion implantation.
摘要翻译：包括可折入隔离结构的半导体器件和用于制造这种器件的方法。优选实施例包括形成至少一个隔离结构的半导体材料的衬底，该隔离结构具有折返轮廓并且隔离一个或多个相邻的操作部件。至少一个隔离结构的折返轮廓由衬底材料形成，并且通过离子注入产生，优选地使用以多个不同角度和能级施加的氧离子。在另一个实施方案中，本发明是形成用于进行至少一个氧离子注入的半导体器件的隔离结构的方法。

12. 发明授权

US07892909B2 Polysilicon gate formation by in-situ doping 有权
标题翻译：通过原位掺杂形成多晶硅栅
公开(公告)号：US07892909B2
公开(公告)日：2011-02-22
申请号：US11729009
申请日：2007-03-28
申请人： Chen-Hua Yu , Ding-Yuan Chen , Chu-Yun Fu , Liang-Gi Yao , Chen-Nan Yeh
发明人： Chen-Hua Yu , Ding-Yuan Chen , Chu-Yun Fu , Liang-Gi Yao , Chen-Nan Yeh
IPC分类号： H01L29/76
CPC分类号： H01L29/7834 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L29/165 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric layer on the semiconductor substrate; forming a first silicon-containing layer on the gate dielectric layer, wherein the first silicon-containing layer is substantially free from p-type and n-type impurities; forming a second silicon-containing layer over the first silicon-containing layer, wherein the second silicon-containing layer comprises an impurity; and performing an annealing to diffuse the impurity in the second silicon-containing layer into the first silicon-containing layer.
摘要翻译：一种形成半导体结构的方法包括提供半导体衬底; 在所述半导体衬底上形成栅介电层; 在所述栅极电介质层上形成第一含硅层，其中所述第一含硅层基本上不含p型和n型杂质; 在所述第一含硅层上形成第二含硅层，其中所述第二含硅层包含杂质; 并进行退火以将第二含硅层中的杂质扩散到第一含硅层中。

13. 发明申请

US20080303104A1 Method of Fabricating Semiconductor Device Isolation Structure 有权
标题翻译：制造半导体器件隔离结构的方法
公开(公告)号：US20080303104A1
公开(公告)日：2008-12-11
申请号：US11758043
申请日：2007-06-05
申请人： Chen-Hua Yu , Chen-Nan Yeh , Chu-Yun Fu , Ding-Yuan Chen
发明人： Chen-Hua Yu , Chen-Nan Yeh , Chu-Yun Fu , Ding-Yuan Chen
IPC分类号： H01L29/94
CPC分类号： H01L21/76202 , H01L21/26506 , H01L21/26533 , H01L21/26586 , H01L21/266 , H01L21/324 , H01L21/762 , H01L21/823481 , H01L29/0649 , H01L29/6659 , H01L29/7833
摘要： A semiconductor device including reentrant isolation structures and a method for making such a device. A preferred embodiment comprises a substrate of semiconductor material forming at least one isolation structure having a reentrant profile and isolating one or more adjacent operational components. The reentrant profile of the at least one isolation structure is formed of substrate material and is created by ion implantation, preferably using oxygen ions applied at a number of different angles and energy levels. In another embodiment the present invention is a method of forming an isolation structure for a semiconductor device performing at least one oxygen ion implantation.
摘要翻译：包括可折入隔离结构的半导体器件和用于制造这种器件的方法。优选实施例包括形成至少一个隔离结构的半导体材料的衬底，该隔离结构具有折返轮廓并且隔离一个或多个相邻的操作部件。至少一个隔离结构的折返轮廓由衬底材料形成，并且通过离子注入产生，优选地使用以多个不同角度和能级施加的氧离子。在另一个实施方案中，本发明是形成用于进行至少一个氧离子注入的半导体器件的隔离结构的方法。

14. 发明授权

US06372664B1 Crack resistant multi-layer dielectric layer and method for formation thereof 有权
标题翻译：耐裂纹多层电介质层及其形成方法
公开(公告)号：US06372664B1
公开(公告)日：2002-04-16
申请号：US09419104
申请日：1999-10-15
申请人： Syun-Ming Jang , Chu-Yun Fu , Chen-Hua Yu
发明人： Syun-Ming Jang , Chu-Yun Fu , Chen-Hua Yu
IPC分类号： H01L2131
CPC分类号： H01L21/02164 , H01L21/022 , H01L21/02211 , H01L21/02271 , H01L21/02274 , H01L21/31612 , H01L21/76801
摘要： A method for forming upon a substrate employed within a microelectronics fabrication a dieletric layer with improved physical properties. There is first provided a substrate. There is then formed over the substrate a series of lines which constitute a patterned microelectronics layer. There is then formed over the patterned microelectronics layer and substrate a conformal dielectric layer. There is then formed over the substrate a second dielectric layer. There is then formed over the substrate a third dielectric layer formed of silicon oxide dielectric material employing high density plasma chemical vapor deposition (HDP-CVD) to complete a composite inter-level metal dielectric (IMD) layer. A fourth dielectric layer formed employing silicon containing dielectric material may be formed over the substrate and third dielectric layer to complete an inter-level metal dielectric (IMD) layer. The fourth dielectric layer is inhibited from cracking by the presence of the third silicon oxide dielectric layer formed by HDP-CVD method.
摘要翻译：一种用于在微电子制造中使用的衬底上形成具有改进的物理性质的抗蚀层的方法。首先提供基板。然后在衬底上形成构成图案化微电子层的一系列线。然后在图案化的微电子层和衬底上形成共形介电层。然后在衬底上形成第二介电层。然后在衬底上形成由使用高密度等离子体化学气相沉积（HDP-CVD）的氧化硅介电材料形成的第三介电层，以完成复合层间金属电介质（IMD）层。可以在衬底和第三电介质层上形成使用含硅电介质材料形成的第四电介质层，以完成层间金属电介质（IMD）层。通过存在由HDP-CVD法形成的第三氧化硅电介质层，可以抑制第四绝缘层的破裂。

15. 发明申请

US20090035909A1 METHOD OF FABRICATION OF A FINFET ELEMENT 有权
标题翻译： FINFET元件的制造方法
公开(公告)号：US20090035909A1
公开(公告)日：2009-02-05
申请号：US11831098
申请日：2007-07-31
申请人： Cheng-Hung Chang , Chen-Hua Yu , Chen-Nan Yeh , Chu-Yun Fu , Yu-Rung Hsu , Ding-Yuan Chen
发明人： Cheng-Hung Chang , Chen-Hua Yu , Chen-Nan Yeh , Chu-Yun Fu , Yu-Rung Hsu , Ding-Yuan Chen
IPC分类号： H01L21/8238
CPC分类号： H01L21/823828 , H01L21/823807 , H01L21/823821 , H01L21/823857 , H01L29/66795 , H01L29/785
摘要： The present disclosure provides a method of fabricating a FinFET element including providing a substrate including a first fin and a second fin. A first layer is formed on the first fin. The first layer comprises a dopant of a first type. A dopant of a second type is provided to the second fin. High temperature processing of the substrate is performed on the substrate including the formed first layer and the dopant of the second type.
摘要翻译：本公开提供了一种制造FinFET元件的方法，包括提供包括第一鳍片和第二鳍片的衬底。在第一散热片上形成第一层。第一层包括第一类型的掺杂剂。第二类型的掺杂剂被提供到第二鳍。在包括所形成的第一层和第二类型的掺杂剂的衬底上进行衬底的高温处理。

16. 发明授权

US09224606B2 Method of fabricating semiconductor device isolation structure 有权
标题翻译：制造半导体器件隔离结构的方法
公开(公告)号：US09224606B2
公开(公告)日：2015-12-29
申请号：US13336887
申请日：2011-12-23
申请人： Chen-Hua Yu , Chen-Nan Yeh , Chu-Yun Fu , Ding-Yuan Chen
发明人： Chen-Hua Yu , Chen-Nan Yeh , Chu-Yun Fu , Ding-Yuan Chen
IPC分类号： H01L21/76 , H01L21/265 , H01L29/66 , H01L29/78
CPC分类号： H01L21/76202 , H01L21/26506 , H01L21/26533 , H01L21/26586 , H01L21/266 , H01L21/324 , H01L21/762 , H01L21/823481 , H01L29/0649 , H01L29/6659 , H01L29/7833
摘要： A semiconductor device including reentrant isolation structures and a method for making such a device. A preferred embodiment comprises a substrate of semiconductor material forming at least one isolation structure having a reentrant profile and isolating one or more adjacent operational components. The reentrant profile of the at least one isolation structure is formed of substrate material and is created by ion implantation, preferably using oxygen ions applied at a number of different angles and energy levels. In another embodiment the present invention is a method of forming an isolation structure for a semiconductor device performing at least one oxygen ion implantation.
摘要翻译：包括可折入隔离结构的半导体器件和用于制造这种器件的方法。优选实施例包括形成至少一个隔离结构的半导体材料的衬底，该隔离结构具有折返轮廓并且隔离一个或多个相邻的操作部件。至少一个隔离结构的折返轮廓由衬底材料形成，并且通过离子注入产生，优选地使用以多个不同角度和能级施加的氧离子。在另一个实施方案中，本发明是形成用于进行至少一个氧离子注入的半导体器件的隔离结构的方法。

17. 发明授权

US08883597B2 Method of fabrication of a FinFET element 有权
标题翻译： FinFET元件的制造方法
公开(公告)号：US08883597B2
公开(公告)日：2014-11-11
申请号：US11831098
申请日：2007-07-31
申请人： Cheng-Hung Chang , Chen-Hua Yu , Chen-Nan Yeh , Chu-Yun Fu , Yu-Rang Hsu , Ding-Yuan Chen
发明人： Cheng-Hung Chang , Chen-Hua Yu , Chen-Nan Yeh , Chu-Yun Fu , Yu-Rang Hsu , Ding-Yuan Chen
IPC分类号： H01L21/8236 , H01L21/8238 , H01L29/78 , H01L29/66
CPC分类号： H01L21/823828 , H01L21/823807 , H01L21/823821 , H01L21/823857 , H01L29/66795 , H01L29/785
摘要： The present disclosure provides a method of fabricating a FinFET element including providing a substrate including a first fin and a second fin. A first layer is formed on the first fin. The first layer comprises a dopant of a first type. A dopant of a second type is provided to the second fin. High temperature processing of the substrate is performed on the substrate including the formed first layer and the dopant of the second type.
摘要翻译：本公开提供了一种制造FinFET元件的方法，包括提供包括第一鳍片和第二鳍片的衬底。在第一散热片上形成第一层。第一层包括第一类型的掺杂剂。第二类型的掺杂剂被提供到第二鳍。在包括所形成的第一层和第二类型的掺杂剂的衬底上进行衬底的高温处理。

18. 发明授权

US07612405B2 Fabrication of FinFETs with multiple fin heights 有权
标题翻译：具有多个翅片高度的FinFET的制造
公开(公告)号：US07612405B2
公开(公告)日：2009-11-03
申请号：US11714644
申请日：2007-03-06
申请人： Chen-Hua Yu , Chen-Nan Yeh , Chu-Yun Fu , Yu-Rung Hsu
发明人： Chen-Hua Yu , Chen-Nan Yeh , Chu-Yun Fu , Yu-Rung Hsu
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L21/823431 , H01L27/0886 , H01L29/66795
摘要： A semiconductor structure includes a first semiconductor strip extending from a top surface of the semiconductor substrate into the semiconductor substrate, wherein the first semiconductor strip has a first height. A first insulating region is formed in the semiconductor substrate and surrounding a bottom portion of the first semiconductor strip, wherein the first insulating region has a first top surface lower than a top surface of the first semiconductor strip. A second semiconductor strip extends from a top surface of the semiconductor substrate into the semiconductor substrate, wherein the second semiconductor strip has a second height greater than the first height. A second insulating region is formed in the semiconductor substrate and surrounding a bottom portion of the second semiconductor strip, wherein the second insulating region has a second top surface lower than the first top surface, and wherein the first and the second insulating regions have substantially same thicknesses.
摘要翻译：半导体结构包括从半导体衬底的顶表面延伸到半导体衬底中的第一半导体条，其中第一半导体条具有第一高度。第一绝缘区域形成在半导体衬底中并围绕第一半导体条的底部，其中第一绝缘区具有比第一半导体条的顶表面低的第一顶表面。第二半导体条从半导体衬底的顶表面延伸到半导体衬底中，其中第二半导体条的第二高度大于第一高度。第二绝缘区域形成在半导体衬底中并围绕第二半导体条的底部，其中第二绝缘区域具有比第一顶表面低的第二顶表面，并且其中第一绝缘区域和第二绝缘区域基本相同厚度

19. 发明授权

US06365523B1 Integrated high density plasma chemical vapor deposition (HDP-CVD) method and chemical mechanical polish (CMP) planarizing method for forming patterned planarized aperture fill layers 有权
标题翻译：集成高密度等离子体化学气相沉积（HDP-CVD）方法和用于形成图案化平面化孔径填充层的化学机械抛光（CMP）平面化方法
公开(公告)号：US06365523B1
公开(公告)日：2002-04-02
申请号：US09177188
申请日：1998-10-22
申请人： Syun-Ming Jang , Chu-Yun Fu , Ying-Ho Chen
发明人： Syun-Ming Jang , Chu-Yun Fu , Ying-Ho Chen
IPC分类号： H01L21302
CPC分类号： H01L21/76229 , H01L21/31053 , H01L21/31612
摘要： A method for forming a series of patterned planarized aperture fill layers within a series of apertures within a topographic substrate layer employed within a microelectronics fabrication. There is first provided a topographic substrate layer employed within a microelectronics fabrication, where the topographic substrate layer comprises a series of mesas of substantially equivalent height but of differing widths and the series of mesas is separated by a series of apertures. There is then formed upon the topographic substrate layer a blanket first aperture fill layer. The blanket first aperture fill layer is formed employing a first simultaneous deposition and sputter method. The blanket first aperture fill layer fills the series of apertures to a planarizing thickness at least as high as the height of the mesas while simultaneously forming a series of protrusions of the blanket first aperture fill layer corresponding with the series of mesas, where the thickness of a protrusion of the blanket first aperture fill layer over a narrow mesa is less than the thickness of a protrusion of the blanket first aperture fill layer over a wide mesa. The first simultaneous deposition and sputter method employs a first deposition rate:sputter rate ratio which provides sufficient thickness of the blanket first aperture fill layer over the narrow mesa such that upon chemical mechanical polish (CMP) planarizing the blanket first aperture fill layer to form a series of patterned planarized first aperture fill layers within the series of apertures erosion of the narrow mesa is attenuated. Finally, there is then chemical mechanical polish (CMP) planarized the blanket first aperture fill layer to form the series of patterned planarized first aperture fill layers within the series of apertures.
摘要翻译：一种用于在微电子学制造中使用的地形衬底层内的一系列孔内形成一系列图案化的平坦化孔填充层的方法。首先提供了在微电子制造中使用的地形衬底层，其中地形衬底层包括基本上等同的高度但具有不同宽度的一系列台面，并且一系列台面由一系列孔分隔开。然后在地形衬底层上形成毯子第一孔填充层。毯子第一孔填充层使用第一同时沉积和溅射方法形成。毯子第一孔填充层将一系列孔填充至至少与台面的高度相同的平坦化厚度，同时形成与一系列台面相对应的毯子第一孔填充层的一系列突起，其中厚度毯子第一孔填充层在窄台面上的突起小于宽台面上的第一孔填充层的突起的厚度。第一同时沉积和溅射方法使用第一沉积速率：溅射速率比，其在窄台面上提供足够厚度的第一孔填充层，使得在化学机械抛光（CMP）上平坦化第一孔填充层以形成一系列图案化的平面化的第一孔径填充层在一系列孔径内的狭窄台面的侵蚀被衰减。最后，然后是化学机械抛光（CMP）平坦化第一孔填充层，以在一系列孔内形成一系列图案化的平坦化的第一孔填充层。

20. 发明申请

US20060211250A1 Scratch reduction for chemical mechanical polishing 有权
标题翻译：化学机械抛光刮刮
公开(公告)号：US20060211250A1
公开(公告)日：2006-09-21
申请号：US11082517
申请日：2005-03-17
申请人： Chuang-Ping Hou , Syun-Ming Jang , Ying-Ho Chen , Chu-Yun Fu , Tung-Ching Tseng
发明人： Chuang-Ping Hou , Syun-Ming Jang , Ying-Ho Chen , Chu-Yun Fu , Tung-Ching Tseng
IPC分类号： H01L21/461 , H01L21/302
CPC分类号： H01L21/31053
摘要： A method for forming a semiconductor device utilizing a chemical-mechanical polishing (CMP) process is provided. In one example, the method includes sequentially performing a first CMP process for removing a first portion of an oxide surface of a semiconductor device using a high selectivity slurry (HSS) and a first polish pad, interrupting the first CMP process, cleaning the semiconductor device and the first polish pad, and performing a second CMP process for removing a second portion of the oxide surface.
摘要翻译：提供了一种利用化学机械抛光（CMP）工艺形成半导体器件的方法。在一个示例中，该方法包括依次执行第一CMP处理，以使用高选择性浆料（HSS）和第一抛光垫去除半导体器件的氧化物表面的第一部分，中断第一CMP工艺，清洁半导体器件和第一抛光垫，并且执行用于去除氧化物表面的第二部分的第二CMP工艺。

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