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11. 发明授权

US06249827B1 Method for transferring data associated with a read/write command between a processor and a reader circuit using a plurality of clock lines 失效
标题翻译：使用多个时钟线在处理器和读取器电路之间传送与读取/写入命令相关联的数据的方法
公开(公告)号：US06249827B1
公开(公告)日：2001-06-19
申请号：US08987328
申请日：1997-12-09
申请人： David V. James , Bruce Millar , Cormac M. O'Connell , Peter B. Gillingham , Brent Keeth
发明人： David V. James , Bruce Millar , Cormac M. O'Connell , Peter B. Gillingham , Brent Keeth
IPC分类号： G06F1304
CPC分类号： G11C7/109 , G06F13/4243 , G11C7/10 , G11C7/1012 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/1087 , G11C7/22 , G11C2207/2254
摘要： A memory circuit with glitch-less transfer of timing information. In one embodiment, the invention is a memory circuit including a controller, multiple loads, a command link communicatively coupling the controller and the loads and a data link. The data link includes multiple data clocks and communicatively couples the controller and the multiple loads. In another embodiment, the invention transfers data between a memory controller and a RAM by coupling the controller and the RAM using a data bus and multiple clock lines. The invention transfers a read/write command from the controller to the RAM and then transfers data associated with the read/write command, clocking the data using one of the clock lines.
摘要翻译：具有无故障传输定时信息的存储电路。在一个实施例中，本发明是包括控制器，多个负载，通信地耦合控制器和负载的命令链路以及数据链路的存储器电路。数据链路包括多个数据时钟，并且通信地耦合控制器和多个负载。在另一个实施例中，本发明通过使用数据总线和多个时钟线耦合控制器和RAM来在存储器控制器和RAM之间传送数据。本发明将读/写命令从控制器传送到RAM，然后传送与读/写命令相关的数据，使用其中一个时钟线为数据计时。

12. 发明授权

US5198709A Address transition detector circuit 失效
标题翻译：地址转换检测电路
公开(公告)号：US5198709A
公开(公告)日：1993-03-30
申请号：US721050
申请日：1991-06-26
申请人： Cormac M. O'Connell
发明人： Cormac M. O'Connell
IPC分类号： G11C11/41 , H03K5/1534 , H03K19/21
CPC分类号： H03K5/1534 , H03K19/215
摘要： A semiconductor integrated circuit including a detection circuit (e.g. an address transition detector) for detecting a change of a first and a second input signal. The detection circuit includes a first and a second resettable delay circuit and a gate circuit which is connected thereto. The gate circuit receives directly both the input signals and the output signals of the delay circuits for promptly outputting an output pulse signal with a minimum duration T for all durations of input signals.

13. 发明授权

US06434699B1 Encryption processor with shared memory interconnect 有权
标题翻译：具有共享内存互连的加密处理器
公开(公告)号：US06434699B1
公开(公告)日：2002-08-13
申请号：US09584930
申请日：2000-06-01
申请人： David E. Jones , Cormac M. O'Connell
发明人： David E. Jones , Cormac M. O'Connell
IPC分类号： G06F124
CPC分类号： G06F7/5324 , G06F7/49931 , G06F7/5052 , G06F7/72 , G06F7/722 , G06F2207/382 , G06F2207/3828 , H04L9/14 , H04L2209/125
摘要： An encryption chip is programmable to process a variety of secret key and public key encryption algorithms. The chip includes a pipeline of processing elements, each of which can process a round within a secret key algorithm. Data is transferred between the processing elements through dual port memories. A central processing unit allows for processing of very wide data words from global memory in single cycle operations. An adder circuit is simplified by using plural relatively small adder circuits with sums and carries looped back in plural cycles. Multiplier circuitry can be shared between the processing elements and the central processor by adapting the smaller processing element multipliers for concatenation as a very wide central processor multiplier.
摘要翻译：加密芯片是可编程的，用于处理各种秘密密钥和公钥加密算法。该芯片包括处理元件的流水线，每个处理元件可以在秘密密钥算法内处理一轮。通过双端口存储器在处理元件之间传送数据。中央处理单元允许在单周期操作中处理来自全局存储器的非常宽的数据字。通过使用多个具有和的相对较小的加法器电路来简化加法器电路，并以多个周期进行循环。乘法器电路可以通过将较小的处理单元乘法器适配为级联，作为非常宽的中央处理器乘法器而在处理元件和中央处理器之间共享。

14. 发明授权

US6088800A Encryption processor with shared memory interconnect 失效
公开(公告)号：US6088800A
公开(公告)日：2000-07-11
申请号：US32029
申请日：1998-02-27
申请人： David E. Jones , Cormac M. O'Connell
发明人： David E. Jones , Cormac M. O'Connell
IPC分类号： G06F13/36 , G06F7/50 , G06F7/52 , G06F7/72 , G09C1/00 , H04L9/00 , H04L9/06 , H04L9/30
CPC分类号： G06F7/5324 , G06F7/5052 , G06F7/72 , G06F7/722 , H04L9/14 , G06F2207/382 , G06F2207/3828 , G06F7/49931 , H04L2209/125
摘要： An encryption chip is programmable to process a variety of secret key and public key encryption algorithms. The chip includes a pipeline of processing elements, each of which can process a round within a secret key algorithm. Data is transferred between the processing elements through dual port memories. A central processing unit allows for processing of very wide data words from global memory in single cycle operations. An adder circuit is simplified by using plural relatively small adder circuits with sums and carries looped back in plural cycles. Multiplier circuitry can be shared between the processing elements and the central processor by adapting the smaller processing element multipliers for concatenation as a very wide central processor multiplier.

15. 发明授权

US5715200A Memory devices 失效
标题翻译：内存设备
公开(公告)号：US5715200A
公开(公告)日：1998-02-03
申请号：US682661
申请日：1996-10-01
申请人： Dennis A. Fielder , James H. Derbyshire , Peter B. Gillingham , Cormac M. O'Connell , Randall R. Torrance
发明人： Dennis A. Fielder , James H. Derbyshire , Peter B. Gillingham , Cormac M. O'Connell , Randall R. Torrance
IPC分类号： G06F12/08 , G11C7/10 , G11C7/00 , G11C15/00
CPC分类号： G11C7/1051 , G06F12/0893
摘要： A memory device with a dynamic random access memory (DRAM) having an array of a plurality of rows and columns of memory elements; a cache memory formed integrally with the DRAM and includinmg at least one register with a plurality of memory elements and connected in pitch-matched relation to the DRAM array, the number of memory elements in a row of the DRAM being n times the number of memory elements in the at least one register, n being an integer greater than or equal to 2; and a connector for connecting the at least one register to the DRAM, the connector for the at least one register being a bus having a width corresponding to the number of memory elements therein.
摘要翻译： PCT No.PCT / GB95 / 02780 Sec。 371日期：1996年10月1日 102（e）日期1996年10月1日PCT提交1995年11月29日PCT公布。出版物WO96 / 17354 日期：1996年6月6日具有动态随机存取存储器（DRAM）的存储器件，具有存储元件的多个行和列的阵列; 与DRAM一体形成的高速缓冲存储器，并且包括至少一个具有多个存储元件的寄存器并以与音调匹配的关系连接到DRAM阵列，DRAM的一行中的存储器元件的数量是存储器数量的n倍所述至少一个寄存器中的元素，n是大于或等于2的整数; 以及用于将至少一个寄存器连接到DRAM的连接器，用于至少一个寄存器的连接器是具有对应于其中的存储器元件的数量的宽度的总线。

16. 发明授权

US4783601A Integrated logic circuit having a control circuit for generating a time-dependent waveform 失效
标题翻译：具有用于产生时间相关波形的控制电路的集成逻辑电路
公开(公告)号：US4783601A
公开(公告)日：1988-11-08
申请号：US9428
申请日：1987-02-02
申请人： Cornelis D. Hartgring , Roelof H. W. Salters , Cormac M. O'Connell , Joannes J. M. Koomen
发明人： Cornelis D. Hartgring , Roelof H. W. Salters , Cormac M. O'Connell , Joannes J. M. Koomen
IPC分类号： H03K17/687 , H03K5/02 , H03K17/16 , H03K19/003 , H03K19/0185 , H03K19/094 , H03K19/0944 , H03K19/0952 , H03K17/56 , H03K3/01 , H03K5/13
CPC分类号： H03K19/00361 , H03K17/163 , H03K5/023
摘要： An integrated logic circuit includes an output circuit for generating an output current which increases linearly in time. In integrated logic circuits the problem presents itself that the rapid variation of the (dis) charging of a data output causes a reverse voltage pulse VL across the inductance formed by the connection wires. The reverse voltage is limited by causing the charge or discharge current (for the load capacities present) to increase linearly to a maximum permissible value. This is done by driving the output field effect transistor with a control voltage VC which varies in time in the form of a square root.

17. 再颁专利

USRE44697E1 Encryption processor with shared memory interconnect 有权
标题翻译：具有共享内存互连的加密处理器
公开(公告)号：USRE44697E1
公开(公告)日：2014-01-07
申请号：US13603137
申请日：2012-09-04
申请人： David E. Jones , Cormac M. O'Connell
发明人： David E. Jones , Cormac M. O'Connell
IPC分类号： G06F21/00
CPC分类号： G06F7/5324 , G06F7/49931 , G06F7/5052 , G06F7/72 , G06F7/722 , G06F2207/382 , G06F2207/3828 , H04L9/14 , H04L2209/125
摘要： An encryption chip is programmable to process a variety of secret key and public key encryption algorithms. The chip includes a pipeline of processing elements, each of which can process a round within a secret key algorithm. Data is transferred between the processing elements through dual port memories. A central processing unit allows for processing of very wide data words from global memory in single cycle operations. An adder circuit is simplified by using plural relatively small adder circuits with sums and carries looped back in plural cycles. Multiplier circuitry can be shared between the processing elements and the central processor by adapting the smaller processing element multipliers for concatenation as a very wide central processor multiplier.
摘要翻译：加密芯片是可编程的，用于处理各种秘密密钥和公钥加密算法。该芯片包括处理元件的流水线，每个处理元件可以在秘密密钥算法内处理一轮。通过双端口存储器在处理元件之间传送数据。中央处理单元允许在单周期操作中处理来自全局存储器的非常宽的数据字。通过使用多个具有和的相对较小的加法器电路来简化加法器电路，并以多个周期进行循环。乘法器电路可以通过将较小的处理单元乘法器适配为级联，作为非常宽的中央处理器乘法器而在处理元件和中央处理器之间共享。

18. 再颁专利

USRE41565E1 Single chip frame buffer and graphics accelerator 有权
标题翻译：单片机缓冲器和图形加速器
公开(公告)号：USRE41565E1
公开(公告)日：2010-08-24
申请号：US11872353
申请日：2007-10-15
申请人： Dennis A. Fielder , Philip S. Shaer , James H. Derbyshire , Peter B. Gillingham , Randy R. Torrance , Cormac M. O'Connell
发明人： Dennis A. Fielder , James H. Derbyshire , Peter B. Gillingham , Randy R. Torrance , Cormac M. O'Connell
IPC分类号： G06F13/14 , G06F15/00 , G06F12/02 , G09G5/36
CPC分类号： G09G5/363 , G09G5/39 , G11C7/10 , G11C7/1048 , G11C11/4093 , G11C11/4096 , G11C2207/104
摘要： A single chip display processor comprised of a dynamic random access memory (DRAM) for storing at least one of graphics and video pixel data, a pixel data unit (PDU) for processing the pixel data, integrated in the same integrated circuit (IC) chip as the DRAM, the IC chip further comprising a massively parallel bus for transferring blocks of pixel data at the same time from the DRAM to the PDU, whereby the PDU can process the blocks of pixel data for subsequent display of processed pixel data.
摘要翻译：一种单芯片显示处理器，包括用于存储图形和视频像素数据中的至少一个的动态随机存取存储器（DRAM），用于处理像素数据的像素数据单元（PDU），集成在同一集成电路（IC）芯片中作为DRAM，IC芯片还包括用于从DRAM到PDU同时传送像素数据块的大规模并行总线，由此PDU可以处理像素数据块以用于随后显示经处理的像素数据。

19. 再颁专利

USRE40326E1 Single chip frame buffer and graphics accelerator 有权
标题翻译：单片机缓冲器和图形加速器
公开(公告)号：USRE40326E1
公开(公告)日：2008-05-20
申请号：US10264013
申请日：2002-10-04
申请人： Dennis A. Fielder , James H. Derbyshire , Peter B. Gillingham , Randy R. Torrance , Cormac M. O'Connell
发明人： Dennis A. Fielder , James H. Derbyshire , Peter B. Gillingham , Randy R. Torrance , Cormac M. O'Connell
IPC分类号： G06F15/76 , G06F15/00 , G06F12/02 , G06T1/00 , G09G5/36
CPC分类号： G09G5/363 , G09G5/39 , G11C7/10 , G11C7/1048 , G11C11/4093 , G11C11/4096 , G11C2207/104
摘要： A single chip display processor comprised of a dynamic random access memory (DRAM) for storing at least one of graphics and video pixel data, a pixel data unit (PDU) for processing the pixel data, integrated in the same integrated circuit (IC) chip as the DRAM, the IC chip further comprising a massively parallel bus for transferring blocks of pixel data at the same time from the DRAM to the PDU, whereby the PDU can process the blocks of pixel data for subsequent display of processed pixel data.
摘要翻译：一种单芯片显示处理器，包括用于存储图形和视频像素数据中的至少一个的动态随机存取存储器（DRAM），用于处理像素数据的像素数据单元（PDU），集成在同一集成电路（IC）芯片中作为DRAM，IC芯片还包括用于从DRAM到PDU同时传送像素数据块的大规模并行总线，由此PDU可以处理像素数据块以用于随后显示经处理的像素数据。

20. 发明授权

US06995808B2 Television tuner 失效
公开(公告)号：US06995808B2
公开(公告)日：2006-02-07
申请号：US10053603
申请日：2002-01-24
申请人： Stephen J. Kovacic , Cormac M. O'Connell
发明人： Stephen J. Kovacic , Cormac M. O'Connell
IPC分类号： H04N5/50 , H04N5/455
CPC分类号： H04N21/4263 , H03J1/0008 , H04N5/50
摘要： A front end tuner for receiving TV signals and the like includes a frequency conversion circuit including a mixer for beating a local signal with received signals within a predetermined band of frequencies to provide selected signals within a predetermined band of frequencies to provide selected signals within a predetermined channel band of frequencies. A signal converter circuit generates digitally encoded signal representations of the selected signals. The frequency conversion circuit and the signal converter circuit are in a form of an integrated circuit within a semiconductor substrate. In a TV receiver, on-following digital processing of the digitally encoded signals is performed in a microcomputer. In one example a channel selection code is used by the microcomputer to synthesize the local oscillator signal and in another example the signal converter circuit is a codec, responsive to codes from the microprocessor, to supply a control voltage for controlling a local oscillator. From time to time channel selection is automatically fine tuned.

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