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11. 发明授权

US06799200B1 Mechanisms for efficient message passing with copy avoidance in a distributed system 有权
标题翻译：在分布式系统中有效的消息传递与避免复制的机制
公开(公告)号：US06799200B1
公开(公告)日：2004-09-28
申请号：US09619053
申请日：2000-07-18
申请人： Robert S. Blackmore , Chulho Kim , Kevin J. Gildea , Rama K. Govindaraju , Gautam H. Shah
发明人： Robert S. Blackmore , Chulho Kim , Kevin J. Gildea , Rama K. Govindaraju , Gautam H. Shah
IPC分类号： G06F15167
CPC分类号： G06F12/1081
摘要： An efficient mechanism for sending messages without the use of intermediate copies (i.e. without the staging of data) is provided. In particular an interface specification which allows use users of a transport protocol is defined so as to lend itself to efficient implementations. The interface specification is a complete and robust set of user functions usable within systems desiring reliable and efficient zero copy transport protocols. Two methods are provided to accomplish the implementation of an efficient zero copy protocol. The first method is especially useful in systems where the network device has limited capabilities in terms of hardware, message fragmentation and message reassembly. An additional RDRAM memory allows data to reside in an adapter while handshake operations take place between an adapter and a node so as to specify the final destination of the data. The second method takes advantage of network devices with advanced features which are exploited for maximum efficiency.
摘要翻译：提供了一种用于在不使用中间副本（即，不进行数据分段）的情况下发送消息的有效机制。特别地，允许使用传输协议的用户的接口规范被定义为使其能够有效地实现。接口规范是一个完整和强大的用户功能集合，可在系统中使用，可靠和高效的零拷贝传输协议。提供了两种方法来实现有效的零拷贝协议。第一种方法在系统中特别有用，其中网络设备在硬件，消息分段和消息重组方面具有有限的能力。另外的RDRAM内存允许数据驻留在适配器中，而握手操作会在适配器和节点之间进行，以便指定数据的最终目的地。第二种方法利用具有高效能的网络设备，以最大限度地提高效率。

12. 发明授权

US07089289B1 Mechanisms for efficient message passing with copy avoidance in a distributed system using advanced network devices 有权
标题翻译：使用高级网络设备的分布式系统中有效的消息传递与避免复制的机制
公开(公告)号：US07089289B1
公开(公告)日：2006-08-08
申请号：US09619051
申请日：2000-07-18
申请人： Robert S. Blackmore , Kevin J. Gildea , Rama K. Govindaraju , Gautam H. Shah
发明人： Robert S. Blackmore , Kevin J. Gildea , Rama K. Govindaraju , Gautam H. Shah
IPC分类号： G06F15/167 , G06F15/16 , G06F13/28
CPC分类号： G06F13/28
摘要： An efficient mechanism for sending messages without the use of intermediate copies (i.e. without the staging of data) is provided. In particular an interface specification which allows use users of a transport protocol is defined so as to lend itself to efficient implementations. The interface specification is a complete and robust set of user functions usable within systems desiring reliable and efficient zero copy transport protocols. Two methods are provided to accomplish the implementation of an efficient zero copy protocol. The first method is especially useful in systems where the network device has limited capabilities in terms of hardware, message fragmentation and message reassembly. An additional RDRAM memory allows data to reside in an adapter while handshake operations take place between an adapter and a node so as to specify the final destination of the data. The second method takes advantage of network devices with advanced features which are exploited for maximum efficiency.
摘要翻译：提供了一种用于在不使用中间副本（即，不进行数据分段）的情况下发送消息的有效机制。特别地，允许使用传输协议的用户的接口规范被定义为使其能够有效地实现。接口规范是一个完整和强大的用户功能集合，可在系统中使用，可靠和高效的零拷贝传输协议。提供了两种方法来实现有效的零拷贝协议。第一种方法在系统中特别有用，其中网络设备在硬件，消息分段和消息重组方面具有有限的能力。另外的RDRAM内存允许数据驻留在适配器中，而握手操作会在适配器和节点之间进行，以便指定数据的最终目的地。第二种方法利用具有高效能的网络设备，以最大限度地提高效率。

13. 发明授权

US08140801B2 Efficient and flexible memory copy operation 失效
标题翻译：高效灵活的内存复制操作
公开(公告)号：US08140801B2
公开(公告)日：2012-03-20
申请号：US12191655
申请日：2008-08-14
申请人： Ravi K. Arimilli , Rama K. Govindaraju , Peter H. Hochschild , Bruce G. Mealey , Satya P. Sharma , Balaram Sinharoy
发明人： Ravi K. Arimilli , Rama K. Govindaraju , Peter H. Hochschild , Bruce G. Mealey , Satya P. Sharma , Balaram Sinharoy
IPC分类号： G06F12/00
CPC分类号： G06F9/3834 , G06F9/3004 , G06F9/3824
摘要： A system, method, and computer program product for semi-synchronously copying data from a first portion of memory to a second portion of memory are disclosed. The method comprises receiving, in a processor, a call for a semi-synchronous memory copy operation. The semi-synchronous memory copy operation preserves temporal persistence of validity for a virtual source address corresponding to a source location in a memory and a virtual target address corresponding to a target location in the memory by setting a flag bit. The call includes at least the virtual source address, the virtual target address, and an indicator identifying a number of bytes to be copied. The memory copy operation is placed in a queue for execution by a memory controller. The queue is coupled to the memory controller. At least one subsequent instruction is continued to be executed as the subsequent instruction becomes available from an instruction pipeline.
摘要翻译：公开了一种用于将数据从存储器的第一部分半数同步地复制到存储器的第二部分的系统，方法和计算机程序产品。该方法包括在处理器中接收对半同步存储器复制操作的呼叫。半同步存储器复制操作通过设置标志位来保持对应于存储器中的源位置的虚拟源地址和对应于存储器中的目标位置的虚拟目标地址的有效性的时间持续性。该呼叫至少包括虚拟源地址，虚拟目标地址和标识要复制的字节数的指示符。存储器复制操作被放置在队列中以由存储器控制器执行。队列耦合到存储器控制器。随着随后的指令从指令流水线可用，继续执行至少一个后续指令。

14. 发明申请

US20090271549A1 INTERRUPT HANDLING USING SIMULTANEOUS MULTI-THREADING 失效
标题翻译：使用同时多线程的中断处理
公开(公告)号：US20090271549A1
公开(公告)日：2009-10-29
申请号：US12371865
申请日：2009-02-16
申请人： ROBERT S. BLACKMORE , Rama K. Govindaraju , Peter H. Hochschild
发明人： ROBERT S. BLACKMORE , Rama K. Govindaraju , Peter H. Hochschild
IPC分类号： G06F13/24
CPC分类号： G06F9/5077 , G06F9/4812 , G06F9/4843 , G06F9/5027 , G06F2209/5018
摘要： Disclosed are a method, information processing system, and computer readable medium for managing interrupts. The method includes placing at least one physical processor of an information processing system in a simultaneous multi-threading mode. At least a first logical processor and a second logical processor associated with the at least one physical processor are partitioned. The first logical processor is assigned to manage interrupts and the second logical processor is assigned to dispatch runnable user threads.
摘要翻译：公开了一种用于管理中断的方法，信息处理系统和计算机可读介质。该方法包括将信息处理系统的至少一个物理处理器置于同时多线程模式中。至少与至少一个物理处理器相关联的第一逻辑处理器和第二逻辑处理器被分区。分配第一个逻辑处理器来管理中断，第二个逻辑处理器被分配给调度可运行的用户线程。

15. 发明授权

US07523260B2 Propagating data using mirrored lock caches 失效
标题翻译：使用镜像锁高速缓存传播数据
公开(公告)号：US07523260B2
公开(公告)日：2009-04-21
申请号：US11315465
申请日：2005-12-22
申请人： Ravi K. Arimilli , Rama K. Govindaraju , Peter H. Hochschild , Bruce G. Mealey , Satya P. Sharma , Balaram Sinharoy
发明人： Ravi K. Arimilli , Rama K. Govindaraju , Peter H. Hochschild , Bruce G. Mealey , Satya P. Sharma , Balaram Sinharoy
IPC分类号： G06F12/00
CPC分类号： G06F12/0806 , G06F9/526 , G06F11/1666 , G06F11/20 , G06F11/2097 , G06F12/0815 , G06F12/0875
摘要： A method, processing node, and computer readable medium for propagating data using mirrored lock caches are disclosed. The method includes coupling a first mirrored lock cache associated with a first processing node to a bus that is communicatively coupled to at least a second mirrored lock cache associated with a second processing node in a multi-processing system. The method further includes receiving, by the first mirrored lock cache, data from a processing node. The data is then mirrored automatically so that the same data is available locally at the second mirrored lock cache for use by the second processing node.
摘要翻译：公开了一种用于使用镜像锁高速缓存传播数据的方法，处理节点和计算机可读介质。该方法包括将与第一处理节点相关联的第一镜像锁缓存耦合到通信地耦合到与多处理系统中的第二处理节点相关联的至少第二镜像锁高速缓存的总线。该方法还包括由第一镜像锁高速缓存从处理节点接收数据。然后自动镜像数据，以便相同的数据在第二个镜像锁缓存器本地可用，供第二个处理节点使用。

16. 发明授权

US07506132B2 Validity of address ranges used in semi-synchronous memory copy operations 有权
标题翻译：在半同步存储器复制操作中使用的地址范围的有效性
公开(公告)号：US07506132B2
公开(公告)日：2009-03-17
申请号：US11315757
申请日：2005-12-22
申请人： Ravi K. Arimilli , Rama K. Govindaraju , Peter H. Hochschild , Bruce G. Mealey , Satya P. Sharma , Balaram Sinharoy
发明人： Ravi K. Arimilli , Rama K. Govindaraju , Peter H. Hochschild , Bruce G. Mealey , Satya P. Sharma , Balaram Sinharoy
IPC分类号： G06F12/00
CPC分类号： G06F12/1441 , G06F12/0888 , G06F12/0897
摘要： A system, method, and a computer readable for protecting content of a memory page are disclosed. The method includes determining a start of a semi-synchronous memory copy operation. A range of addresses is determined where the semi-synchronous memory copy operation is being performed. An issued instruction that removes a page table entry is detected. The method further includes determining whether the issued instruction is destined to remove a page table entry associated with at least one address in the range of addresses. In response to the issued instruction being destined to remove the page table entry, the execution of the issued instruction is stalled until the semi-synchronous memory copy operation is completed.
摘要翻译：公开了一种用于保护存储器页面的内容的系统，方法和可读取的计算机。该方法包括确定半同步存储器复制操作的开始。确定正在执行半同步存储器复制操作的地址范围。检测到发出的删除页表条目的指令。所述方法还包括确定所发出的指令是否旨在去除与地址范围中的至少一个地址相关联的页表条目。响应于发出的指令旨在去除页表条目，所发出的指令的执行停止，直到半同步存储器复制操作完成。

17. 发明申请

US20080307182A1 EFFICIENT AND FLEXIBLE MEMORY COPY OPERATION 失效
标题翻译：高效和灵活的内存复印操作
公开(公告)号：US20080307182A1
公开(公告)日：2008-12-11
申请号：US12191655
申请日：2008-08-14
申请人： Ravi K. Arimilli , Rama K. Govindaraju , Peter H. Hochschild , Bruce G. Mealey , Satya P. Sharma , Balaram Sinharoy
发明人： Ravi K. Arimilli , Rama K. Govindaraju , Peter H. Hochschild , Bruce G. Mealey , Satya P. Sharma , Balaram Sinharoy
IPC分类号： G06F13/00 , G06F12/16
CPC分类号： G06F9/3834 , G06F9/3004 , G06F9/3824
摘要： A system, method, and computer program product for semi-synchronously copying data from a first portion of memory to a second portion of memory are disclosed. The method comprises receiving, in a processor, a call for a semi-synchronous memory copy operation. The semi-synchronous memory copy operation preserves temporal persistence of validity for a virtual source address corresponding to a source location in a memory and a virtual target address corresponding to a target location in the memory by setting a flag bit. The call includes at least the virtual source address, the virtual target address, and an indicator identifying a number of bytes to be copied. The memory copy operation is placed in a queue for execution by a memory controller. The queue is coupled to the memory controller. At least one subsequent instruction is continued to be executed as the subsequent instruction becomes available from an instruction pipeline.
摘要翻译：公开了一种用于将数据从存储器的第一部分半数同步地复制到存储器的第二部分的系统，方法和计算机程序产品。该方法包括在处理器中接收对半同步存储器复制操作的呼叫。半同步存储器复制操作通过设置标志位来保持对应于存储器中的源位置的虚拟源地址和对应于存储器中的目标位置的虚拟目标地址的有效性的时间持续性。该呼叫至少包括虚拟源地址，虚拟目标地址和标识要复制的字节数的指示符。存储器复制操作被放置在队列中以由存储器控制器执行。队列耦合到存储器控制器。随着随后的指令从指令流水线可用，继续执行至少一个后续指令。

18. 发明授权

US08364849B2 Snapshot interface operations 失效
标题翻译：快照界面操作
公开(公告)号：US08364849B2
公开(公告)日：2013-01-29
申请号：US11017332
申请日：2004-12-20
申请人： Piyush Chaudhary , Jason E. Goscinski , Rama K. Govindaraju , Leonard W. Helmer, Jr. , Peter H. Hochschild , Deryck X. Hong , John S. Houston , Jang-Soo Lee , Steven J. Martin , Yuqing Zhu
发明人： Piyush Chaudhary , Jason E. Goscinski , Rama K. Govindaraju , Leonard W. Helmer, Jr. , Peter H. Hochschild , Deryck X. Hong , John S. Houston , Jang-Soo Lee , Steven J. Martin , Yuqing Zhu
IPC分类号： G06F15/16
CPC分类号： H04L67/1097
摘要： In a multinode data processing system in which the nodes communicate with one another via communication adapters over a network or switch, the adapters are provided with a dual register mechanism for tracking microcode task status. Upon the issuance of a disruptive command that requires attention from one of the nodes, the task status maintained in one register is copied to the snapshot register. As tasks within the adapter are completed, both registers are updated, thus providing a mechanism for the nodes to determine that all tasks active at the time of the disruptive command have completed. This means that the nodes now have a mechanism for determining, as soon as possible, that all tasks that are active when a disruptive command occurs have completed, thus allowing the data processing node to perform such operations as releasing system memory that is associated with the disruptive command, thus eliminating temporal overhead that can affect performance.
摘要翻译：在其中节点通过网络或交换机经由通信适配器彼此通信的多节点数据处理系统中，适配器被提供有用于跟踪微代码任务状态的双重注册机制。在发出需要从其中一个节点注意的破坏性命令时，将一个寄存器中维护的任务状态复制到快照寄存器。当适配器中的任务完成时，两个寄存器都被更新，从而为节点确定在破坏性命令时激活的所有任务完成的机制。这意味着节点现在具有用于尽可能快地确定在发生破坏性命令时活动的所有任务已经完成的机制，从而允许数据处理节点执行诸如释放与破坏性命令，从而消除可能影响性能的时间开销。

19. 发明申请

US20110078410A1 EFFICIENT PIPELINING OF RDMA FOR COMMUNICATIONS 审中-公开
标题翻译： RDMA通信的有效管道
公开(公告)号：US20110078410A1
公开(公告)日：2011-03-31
申请号：US11457921
申请日：2006-07-17
申请人： Robert S. Blackmore , Rama K. Govindaraju , Peter H. Hochschild , Chulho Kim , Rajeev Sivaram , Richard R. Treumann , Hanhong Xue
发明人： Robert S. Blackmore , Rama K. Govindaraju , Peter H. Hochschild , Chulho Kim , Rajeev Sivaram , Richard R. Treumann , Hanhong Xue
IPC分类号： G06F12/00 , G06F15/76 , G06F9/02
CPC分类号： G06F15/17375
摘要： Disclosed are a method of and system for multiple party communications in a processing system including multiple processing subsystems. Each of the processing subsystems includes a central processing unit and one or more network adapters for connecting said each processing subsystem to the other processing subsystems. A multitude of nodes are established or created, and each of these nodes is associated with one of the processing subsystems. A first aspect of the invention involves pipelined communication using RDMA among three nodes, where the first node breaks up a large communication into multiple parts and sends these parts one after the other to the second node using RDMA, and the second node in turn absorbs and forwards each of these parts to a third node before all parts of the communication arrive from the first node.
摘要翻译：公开了一种包括多个处理子系统的处理系统中的多方通信的方法和系统。每个处理子系统包括中央处理单元和用于将所述每个处理子系统连接到其他处理子系统的一个或多个网络适配器。建立或创建多个节点，并且这些节点中的每一个都与处理子系统之一相关联。本发明的第一方面涉及在三个节点之间使用RDMA的流水线通信，其中第一节点将大型通信分解成多个部分，并且使用RDMA将这些部分一个接一个地发送到第二节点，并且第二节点依次吸收和在通信的所有部分从第一节点到达之前，将这些部分中的每一个转发到第三节点。

20. 发明申请

US20090182968A1 VALIDITY OF ADDRESS RANGES USED IN SEMI-SYNCHRONOUS MEMORY COPY OPERATIONS 有权
标题翻译：在同步存储器复制操作中使用的地址范围的有效性
公开(公告)号：US20090182968A1
公开(公告)日：2009-07-16
申请号：US12402904
申请日：2009-03-12
申请人： RAVI K. ARIMILLI , Rama K. Govindaraju , Peter H. Hochschild , Bruce G. Mealey , Satya P. Sharma , Balaram Sinharoy
发明人： RAVI K. ARIMILLI , Rama K. Govindaraju , Peter H. Hochschild , Bruce G. Mealey , Satya P. Sharma , Balaram Sinharoy
IPC分类号： G06F12/02
CPC分类号： G06F12/1441 , G06F12/0888 , G06F12/0897
摘要： A system, method, and a computer readable for protecting content of a memory page are disclosed. The method includes determining a start of a semi-synchronous memory copy operation. A range of addresses is determined where the semi-synchronous memory copy operation is being performed. An issued instruction that removes a page table entry is detected. The method further includes determining whether the issued instruction is destined to remove a page table entry associated with at least one address in the range of addresses. In response to the issued instruction being destined to remove the page table entry, the execution of the issued instruction is stalled until the semi-synchronous memory copy operation is completed.
摘要翻译：公开了一种用于保护存储器页面的内容的系统，方法和可读取的计算机。该方法包括确定半同步存储器复制操作的开始。确定正在执行半同步存储器复制操作的地址范围。检测到发出的删除页表条目的指令。所述方法还包括确定所发出的指令是否旨在去除与地址范围中的至少一个地址相关联的页表条目。响应于发出的指令旨在去除页表条目，所发出的指令的执行停止，直到半同步存储器复制操作完成。

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