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11. 发明授权

US07999707B2 Apparatus for compensating for error of time-to-digital converter 有权
标题翻译：用于补偿时间 - 数字转换器误差的装置
公开(公告)号：US07999707B2
公开(公告)日：2011-08-16
申请号：US12629020
申请日：2009-12-01
申请人： Mi Jeong Park , Byung Hun Min , Ja Yol Lee , Hyun Kyu Yu
发明人： Mi Jeong Park , Byung Hun Min , Ja Yol Lee , Hyun Kyu Yu
IPC分类号： H03M1/06
CPC分类号： G04F10/06 , H03L7/085 , H03L2207/50
摘要： An apparatus for compensating for an error of a time-to-digital converter (TDC) is disclosed to receive a delay phase from a phase detector including the TDC and a phase error including a TDC error and compensate for the TDC error to have a time resolution higher by N times (N is a natural number). The apparatus includes: a fragmenting and multiplying unit fragmenting the delay phase by N times (N is a natural number) to generate first to (N−1)th fragmented delay phases; an adding unit adding each of the first to the (N−1)th fragmented delay phases to the phase error to generate first to (N−1)th phase errors; and a comparison unit acquiring a phase error compensation value nearest to an actual phase error from the phase error and the first to (N−1)th phase errors.
摘要翻译：公开了用于补偿时间 - 数字转换器（TDC）的误差的装置，以从包括TDC的相位检测器和包括TDC误差的相位误差接收延迟相位并补偿TDC误差以具有时间分辨率提高N倍（N是自然数）。该装置包括：分段和乘法单元，将延迟相位分片N次（N是自然数），以产生第一至第（N-1）个分段延迟相位; 加法单元将第一到第（N-1）个分段延迟相位中的每一个相加到相位误差，以产生第一到第（N-1）个相位误差; 以及比较单元从相位误差和第一到第（N-1）个相位误差获取最接近实际相位误差的相位误差补偿值。

12. 发明申请

US20100134335A1 APPARATUS FOR COMPENSATING FOR ERROR OF TIME-TO-DIGITAL CONVERTER 有权
标题翻译：用于补偿时间到数字转换器错误的装置
公开(公告)号：US20100134335A1
公开(公告)日：2010-06-03
申请号：US12629020
申请日：2009-12-01
申请人： Mi Jeong Park , Byung Hun Min , Ja Yol Lee , Hyun Kyu Yu
发明人： Mi Jeong Park , Byung Hun Min , Ja Yol Lee , Hyun Kyu Yu
IPC分类号： H03M1/06
CPC分类号： G04F10/06 , H03L7/085 , H03L2207/50
摘要： An apparatus for compensating for an error of a time-to-digital converter (TDC) is disclosed to receive a delay phase from a phase detector including the TDC and a phase error including a TDC error and compensate for the TDC error to have a time resolution higher by N times (N is a natural number). The apparatus includes: a fragmenting and multiplying unit fragmenting the delay phase by N times (N is a natural number) to generate first to (N−1)th fragmented delay phases; an adding unit adding each of the first to the (N−1)th fragmented delay phases to the phase error to generate first to (N−1)th phase errors; and a comparison unit acquiring a phase error compensation value nearest to an actual phase error from the phase error and the first to (N−1)th phase errors.
摘要翻译：公开了用于补偿时间 - 数字转换器（TDC）的误差的装置，以从包括TDC的相位检测器和包括TDC误差的相位误差接收延迟相位并补偿TDC误差以具有时间分辨率提高N倍（N是自然数）。该装置包括：分段和乘法单元，将延迟相位分片N次（N是自然数），以产生第一到第（N-1）个分段延迟相位; 加法单元将第一到第（N-1）个分段延迟相位中的每一个相加到相位误差，以产生第一到第（N-1）个相位误差; 以及比较单元从相位误差和第一到第（N-1）个相位误差获取最接近实际相位误差的相位误差补偿值。

13. 发明授权

US08258832B2 Loop filter and phase locked loop including the same 有权
标题翻译：环路滤波器和锁相环包括相同的
公开(公告)号：US08258832B2
公开(公告)日：2012-09-04
申请号：US12860498
申请日：2010-08-20
申请人： Byung Hun Min
发明人： Byung Hun Min
IPC分类号： H03L7/06
CPC分类号： H03L7/0893 , H03L7/093
摘要： Provided is a loop filter which receives first and second currents whose current ratio is n (where n is a natural number). The loop filter includes a first-order filter path, a second-order filter path, and a third-order filter path. The first-order filter path includes an operational amplifier generating an output impedance by increasing by as much as n times an impedance of a second input node to which the second current is applied. The first-order filter path performs a first-order filtering on the first current applied to a first input node by using the operational amplifier. The second-order filter path performs a second-order filtering on the first current applied to the first input node. The third-order filter path performs a third-order filtering on the first current applied to the first input node.
摘要翻译：提供一种环路滤波器，其接收电流比为n（其中n为自然数）的第一和第二电流。环路滤波器包括一阶滤波器路径，二阶滤波器路径和三阶滤波器路径。一阶滤波器路径包括运算放大器，通过将施加第二电流的第二输入节点的阻抗增加多达n倍，产生输出阻抗。一阶滤波器路径通过使用运算放大器对施加到第一输入节点的第一电流执行一阶滤波。二阶滤波器路径对施加到第一输入节点的第一电流执行二阶滤波。三阶滤波器路径对施加到第一输入节点的第一电流执行三阶滤波。

14. 发明授权

US08031009B2 Frequency calibration loop circuit 失效
标题翻译：频率校准回路电路
公开(公告)号：US08031009B2
公开(公告)日：2011-10-04
申请号：US12581105
申请日：2009-10-16
申请人： Byung Hun Min , Ja Yol Lee , Seong Do Kim , Cheon Soo Kim , Hyun Kyu Yu
发明人： Byung Hun Min , Ja Yol Lee , Seong Do Kim , Cheon Soo Kim , Hyun Kyu Yu
IPC分类号： H03L7/085 , H03L7/095 , H03L7/18 , H03L7/081
CPC分类号： H03L7/181 , H03L2207/50 , Y10S331/02
摘要： A frequency calibration loop circuit having a pre-set frequency channel word (FCW) command value, a bit inputted to obtain a target frequency in an oscillator and a pre-set minimum division ratio n (n is a constant) of a programmable divider, includes: an oscillator adjusting an oscillation frequency of an oscillation signal according to a control value; a programmable divider dividing the oscillation signal according to a division ratio to output a divided signal; a counter counting the number of clocks of the divided signal for one cycle of a reference signal to output a count value; and a frequency detector obtaining the control value by subtracting the count value from a reference comparison value, wherein the reference comparison value is obtained by dividing a Frequency Channel Word (FCW) command value by a minimum division ratio of the programmable divider.
摘要翻译：一种频率校准环路电路，具有预定的频道字（FCW）指令值，为了获得振荡器中的目标频率输入的比特和可编程分频器的预设最小分频比n（n是常数）包括：振荡器，根据控制值调整振荡信号的振荡频率; 可编程分频器，根据分频比除以振荡信号，输出分频信号; 计数针对参考信号的一个周期的分频信号的时钟数，以输出计数值; 以及频率检测器，通过从参考比较值中减去计数值来获得控制值，其中通过将频率通道字（FCW）指令值除以可编程分频器的最小分频比来获得参考比较值。

15. 发明申请

US20100134195A1 CAPACITOR HAVING VARIABLE CAPACITANCE AND DIGITALLY CONTROLLED OSCILLATOR INCLUDING THE SAME 审中-公开
标题翻译：具有可变电容的电容器和包括其的数字控制振荡器
公开(公告)号：US20100134195A1
公开(公告)日：2010-06-03
申请号：US12629742
申请日：2009-12-02
申请人： Ja Yol LEE , Byung Hun Min , Seong Do Kim , Hyun Kyu Yu
发明人： Ja Yol LEE , Byung Hun Min , Seong Do Kim , Hyun Kyu Yu
IPC分类号： H03B5/12 , H01L27/06
CPC分类号： H03B5/1228 , H03B5/1215 , H03B5/1265
摘要： There is provided a capacitor having variable capacitance, which forms different capacitances according to a control signal by applying a switch to a metal-oxide-metal (MOM) structure plate capacitor using a CMOS process. The capacitor includes a stack structure including a plurality of metal layers including a first metal layer, and a plurality of dielectric layers respectively interposed between the plurality of metal layers, and a switch part including at least one switch having one side connected to at least one metal layer among the plurality of metal layers other than the first metal layer. The first metal layer and the other side of the switch serve as both terminals of the capacitor, and at least two capacitances are provided between both terminals of the capacitor upon controlling a short/open of the switch.
摘要翻译：提供具有可变电容的电容器，其通过使用CMOS工艺将开关施加到金属氧化物金属（MOM）结构板电容器上，根据控制信号形成不同的电容。电容器包括堆叠结构，其包括多个金属层，包括第一金属层和分别介于多个金属层之间的多个电介质层，以及开关部分，其包括至少一个开关，该开关的一侧连接至至少一个除了第一金属层之外的多个金属层中的金属层。开关的第一金属层和另一侧用作电容器的两端，并且在控制开关的短路/断开时，至少两个电容设置在电容器的两个端子之间。

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