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11. 发明授权

US08241988B2 Photo key and method of fabricating semiconductor device using the photo key 有权
标题翻译：使用照片键制造半导体器件的照片键和方法
公开(公告)号：US08241988B2
公开(公告)日：2012-08-14
申请号：US13204752
申请日：2011-08-08
申请人： Byoung-ho Kwon , Chang-ki Hong , Bo-un Yoon , Jae-dong Lee , Sang-jin Kim
发明人： Byoung-ho Kwon , Chang-ki Hong , Bo-un Yoon , Jae-dong Lee , Sang-jin Kim
IPC分类号： H01L21/76 , H01L21/00 , H01L21/66 , G01R31/26
CPC分类号： H01L23/544 , G03F7/70633 , G03F9/7076 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A photo key has a plurality of first regions spaced apart from one another on a semiconductor substrate, and a second region surrounding the first regions, and one of the first regions and the second region constitutes a plurality of photo key regions spaced apart from one another. Each of the photo key regions includes a plurality of first conductive patterns spaced apart from one another; and a plurality of second conductive patterns interposed between the first conductive patterns.
摘要翻译：光钥匙具有在半导体衬底上彼此间隔开的多个第一区域和围绕第一区域的第二区域，并且第一区域和第二区域中的一个构成彼此间隔开的多个光键区域。每个照片键区域包括彼此间隔开的多个第一导电图案; 以及介于所述第一导电图案之间的多个第二导电图案。

12. 发明申请

US20120028435A1 SEMICONDUCTOR DEVICE INCLUDING DUMMY GATE PART AND METHOD OF FABRICATING THE SAME 审中-公开
标题翻译：包括双门部分的半导体器件及其制造方法
公开(公告)号：US20120028435A1
公开(公告)日：2012-02-02
申请号：US13240475
申请日：2011-09-22
申请人： Byoung-ho Kwon , Sang-youn Jo , Jin-sook Choi , Chang-ki Hong , Bo-un Yoon , Hong-soo Kim , Se-rah Yun
发明人： Byoung-ho Kwon , Sang-youn Jo , Jin-sook Choi , Chang-ki Hong , Bo-un Yoon , Hong-soo Kim , Se-rah Yun
IPC分类号： H01L21/76
CPC分类号： H01L21/31053 , H01L27/105 , H01L27/1052 , H01L29/66545
摘要： In a reliable semiconductor device and a method of fabricating the semiconductor device, a difference in height between upper surfaces of a cell region and a peripheral region (also referred to as a level difference) is minimized by optimizing dummy gate parts. The semiconductor device includes a semiconductor substrate including a cell region and a peripheral region surrounding the cell region, a plurality of dummy active regions surrounded by a device isolating region and formed apart from each other, and a plurality of dummy gate parts formed on the dummy active regions and on the device isolating regions located between the dummy active regions, wherein each of the dummy gate parts covers two or more of the dummy active regions.
摘要翻译：在可靠的半导体器件和制造半导体器件的方法中，通过优化虚拟栅极部分来最小化单元区域的上表面与外围区域之间的高度差（也称为电平差）。半导体器件包括：半导体衬底，包括单元区域和围绕单元区域的周边区域;多个虚设有源区域，被器件隔离区域包围并形成为彼此分离;多个虚拟栅极部件，形成在虚拟区域上; 有源区域和位于虚拟有源区域之间的器件隔离区域，其中每个伪栅极部分覆盖两个或更多个虚拟有源区域。

13. 发明申请

US20080206985A1 Method of fabricating a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US20080206985A1
公开(公告)日：2008-08-28
申请号：US11878508
申请日：2007-07-25
申请人： Chae-Iyoung Kim , Chang-Ki Hong , Bo-un Yoon , Sung-ho Shin , Byoung-ho Kwon
发明人： Chae-Iyoung Kim , Chang-Ki Hong , Bo-un Yoon , Sung-ho Shin , Byoung-ho Kwon
IPC分类号： H01L21/44
CPC分类号： H01L21/76816 , H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/7688 , Y10S438/947
摘要： Methods of fabricating a semiconductor device is provided. The methods include forming an interlayer insulating layer on a semiconductor substrate having a first region and a second region. First contact plugs may be formed on a portion of the second region to fill a plurality of first contact holes. A plurality of first contact mask layers and a plurality of first dummy mask layers may be formed on the interlayer insulating layer. The first contact mask layers may be formed in the first region. The first dummy mask layers may be formed in the second region. A plurality of second contact mask layers may be formed between two adjacent first contact mask layers. A plurality of second dummy mask layers may be formed between two adjacent first dummy mask layers. The interlayer insulating layer may be etched using the first contact mask layers and the second contact mask layers as etch stop layers to form a plurality of second contact holes through the interlayer insulating layer formed in the first region.
摘要翻译：提供制造半导体器件的方法。所述方法包括在具有第一区域和第二区域的半导体衬底上形成层间绝缘层。第一接触塞可以形成在第二区域的一部分上以填充多个第一接触孔。多个第一接触掩模层和多个第一伪掩模层可以形成在层间绝缘层上。第一接触掩模层可以形成在第一区域中。第一虚拟掩模层可以形成在第二区域中。可以在两个相邻的第一接触掩模层之间形成多个第二接触掩模层。可以在两个相邻的第一虚拟掩模层之间形成多个第二虚拟掩模层。可以使用第一接触掩模层和第二接触掩模层作为蚀刻停止层来蚀刻层间绝缘层，以形成穿过形成在第一区域中的层间绝缘层的多个第二接触孔。

14. 发明申请

US20090121296A1 Semiconductor device including dummy gate part and method of fabricating the same 有权
标题翻译：半导体器件包括伪栅极部分及其制造方法
公开(公告)号：US20090121296A1
公开(公告)日：2009-05-14
申请号：US12291211
申请日：2008-11-07
申请人： Byoung-ho Kwon , Sang-youn Jo , Jin-sook Choi , Chang-ki Hong , Bo-un Yoon , Hong-soo Kim , Se-rah Yun
发明人： Byoung-ho Kwon , Sang-youn Jo , Jin-sook Choi , Chang-ki Hong , Bo-un Yoon , Hong-soo Kim , Se-rah Yun
IPC分类号： H01L27/10
CPC分类号： H01L21/31053 , H01L27/105 , H01L27/1052 , H01L29/66545
摘要： In a reliable semiconductor device and a method of fabricating the semiconductor device, a difference in height between upper surfaces of a cell region and a peripheral region (also referred to as a level difference) is minimized by optimizing dummy gate parts. The semiconductor device includes a semiconductor substrate including a cell region and a peripheral region surrounding the cell region, a plurality of dummy active regions surrounded by a device isolating region and formed apart from each other, and a plurality of dummy gate parts formed on the dummy active regions and on the device isolating regions located between the dummy active regions, wherein each of the dummy gate parts covers two or more of the dummy active regions.
摘要翻译：在可靠的半导体器件和制造半导体器件的方法中，通过优化虚拟栅极部分来最小化单元区域的上表面与外围区域之间的高度差（也称为电平差）。半导体器件包括：半导体衬底，包括单元区域和围绕单元区域的周边区域;多个虚设有源区域，被器件隔离区域包围并形成为彼此分离;多个虚拟栅极部件，形成在虚拟区域上; 有源区域和位于虚拟有源区域之间的器件隔离区域，其中每个伪栅极部分覆盖两个或更多个虚拟有源区域。

15. 发明申请

US20070155178A1 Slurry for chemical mechanical polishing process and method of manufacturing semiconductor device using the same 审中-公开
标题翻译：用于化学机械抛光工艺的浆料及使用其制造半导体器件的方法
公开(公告)号：US20070155178A1
公开(公告)日：2007-07-05
申请号：US11712931
申请日：2007-03-01
申请人： Young-rae Park , Jung-yup Kim , Bo-un Yoon , Kwang-bok Kim , Jae-phill Boo , Jong-won Lee , Sang-rok Hah , Kyung-hyun Kim , Chang-ki Hong
发明人： Young-rae Park , Jung-yup Kim , Bo-un Yoon , Kwang-bok Kim , Jae-phill Boo , Jong-won Lee , Sang-rok Hah , Kyung-hyun Kim , Chang-ki Hong
IPC分类号： H01L21/306 , H01L21/461 , B44C1/22 , C23F1/00 , H01L21/302
CPC分类号： H01L21/76224 , B24B37/044 , C09G1/02 , H01L21/31053
摘要： A slurry composition useful for chemical mechanical polishing of the surface of a material layer, e.g., a silicon oxide layer, is disclosed. A first material surface which is exposed to the slurry exhibits hydrophilicity, while a second material layer, e.g., a polysilicon layer, the surface of which is also exposed to the slurry, exhibits hydrophobicity, and accordingly acts as a polishing stopping layer. The slurry composition consists essentially of water, abrasive grains, and a polymer additive having both hydrophilic and hydrophobic functional groups.
摘要翻译：公开了一种用于材料层表面例如氧化硅层的化学机械抛光的浆料组合物。暴露于浆料的第一材料表面显示出亲水性，而第二材料层，例如其表面也暴露于浆料的多晶硅层，表现出疏水性，因此用作抛光停止层。浆料组合物基本上由水，磨料颗粒和具有亲水和疏水官能团的聚合物添加剂组成。

16. 发明申请

US20060124594A1 Chemical mechanical polishing (CMP) slurries and CMP methods using and making the same 审中-公开
标题翻译：化学机械抛光（CMP）浆料和CMP方法使用和制造相同
公开(公告)号：US20060124594A1
公开(公告)日：2006-06-15
申请号：US11287361
申请日：2005-11-28
申请人： Jong-heun Lim , Jae-dong Lee , Bo-un Yoon , Chang-ki Hong
发明人： Jong-heun Lim , Jae-dong Lee , Bo-un Yoon , Chang-ki Hong
IPC分类号： C09K3/14 , C09G1/02 , C09K13/00 , B44C1/22 , C23F1/00 , C09C1/68 , B24D3/02
CPC分类号： C09K3/1463 , C09G1/02 , H01L21/31053
摘要： In one aspect, a chemical-mechanical-polishing (CMP) slurry composition is provided which includes ceria abrasive contained in a solution, where the solution includes a viscosity increasing agent which includes a non-ionic polymer compound, and where a viscosity of the composition is at least 1.5 cP. In other aspects, the viscosity increasing agent includes one or more of poly(ethyleneglycol), a Gum compound and isopropyl alcohol.
摘要翻译：一方面，提供了一种化学机械抛光（CMP）浆料组合物，其包括溶液中所含的二氧化铈磨料，其中溶液包括包含非离子聚合物化合物的增粘剂，并且其中组合物的粘度至少1.5cP。在其它方面，增粘剂包括聚（乙二醇），胶体化合物和异丙醇中的一种或多种。

17. 发明授权

US07846801B2 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07846801B2
公开(公告)日：2010-12-07
申请号：US11833050
申请日：2007-08-02
申请人： Sung-jun Kim , Seong-kyu Yun , Chang-ki Hong , Bo-un Yoon , Jong-won Lee , Ho-young Kim
发明人： Sung-jun Kim , Seong-kyu Yun , Chang-ki Hong , Bo-un Yoon , Jong-won Lee , Ho-young Kim
IPC分类号： H01L21/336
CPC分类号： H01L29/66795 , H01L29/7851
摘要： Disclosed is a method of fabricating a semiconductor device including a multi-gate transistor. The method of fabricating a semiconductor device includes providing a semiconductor device having a number of active patterns which extend in a first direction, are separated by an isolation layer, and covered with a first insulating layer; forming a first groove by etching the isolation layer located between the active patterns adjacent to each other in the first direction; burying the first groove with a passivation layer; forming a second groove exposing at least a portion of both sides of the active patterns by etching the isolation layer located between the active patterns in a second direction intersecting the first direction; removing the passivation layer in the first groove; and forming a gate line filling at least a portion of the second groove and extending in the second direction.
摘要翻译：公开了一种制造包括多栅极晶体管的半导体器件的方法。制造半导体器件的方法包括提供具有多个沿第一方向延伸的活性图案的半导体器件，被隔离层隔开并被第一绝缘层覆盖; 通过在第一方向上蚀刻位于彼此相邻的有源图案之间的隔离层来形成第一凹槽; 用钝化层掩埋第一槽; 通过在与所述第一方向相交的第二方向上蚀刻位于所述有源图案之间的所述隔离层来形成暴露所述有源图案的两侧的至少一部分的第二凹槽; 去除第一凹槽中的钝化层; 以及形成填充所述第二凹槽的至少一部分并沿所述第二方向延伸的栅极线。

18. 发明申请

US20080045019A1 Method of Fabricating Semiconductor Device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20080045019A1
公开(公告)日：2008-02-21
申请号：US11833050
申请日：2007-08-02
申请人： Sung-jun Kim , Seong-kyu Yun , Chang-ki Hong , Bo-un Yoon , Jong-won Lee , Ho-young Kim
发明人： Sung-jun Kim , Seong-kyu Yun , Chang-ki Hong , Bo-un Yoon , Jong-won Lee , Ho-young Kim
IPC分类号： H01L21/302
CPC分类号： H01L29/66795 , H01L29/7851
摘要： Disclosed is a method of fabricating a semiconductor device including a multi-gate transistor. The method of fabricating a semiconductor device includes providing a semiconductor device having a number of active patterns which extend in a first direction, are separated by an isolation layer, and covered with a first insulating layer; forming a first groove by etching the isolation layer located between the active patterns adjacent to each other in the first direction; burying the first groove with a passivation layer; forming a second groove exposing at least a portion of both sides of the active patterns by etching the isolation layer located between the active patterns in a second direction intersecting the first direction; removing the passivation layer in the first groove; and forming a gate line filling at least a portion of the second groove and extending in the second direction.
摘要翻译：公开了一种制造包括多栅极晶体管的半导体器件的方法。制造半导体器件的方法包括提供具有多个沿第一方向延伸的活性图案的半导体器件，被隔离层隔开并被第一绝缘层覆盖; 通过在第一方向上蚀刻位于彼此相邻的有源图案之间的隔离层来形成第一凹槽; 用钝化层掩埋第一槽; 通过在与所述第一方向相交的第二方向上蚀刻位于所述有源图案之间的所述隔离层来形成暴露所述有源图案的两侧的至少一部分的第二凹槽; 去除第一凹槽中的钝化层; 以及形成填充所述第二凹槽的至少一部分并沿所述第二方向延伸的栅极线。

19. 发明申请

US20070045671A1 Multi-level transistor and related method 有权
标题翻译：多级晶体管及相关方法
公开(公告)号：US20070045671A1
公开(公告)日：2007-03-01
申请号：US11485485
申请日：2006-07-13
申请人： Sung-jun Kim , Chang-ki Hong , Bo-un Yoon , Jae-kwang Choi
发明人： Sung-jun Kim , Chang-ki Hong , Bo-un Yoon , Jae-kwang Choi
IPC分类号： H01L29/768
CPC分类号： H01L21/8221 , H01L27/0688 , H01L27/12
摘要： A multi-level transistor comprising a second active region having a single-crystalline characteristic and a method for manufacturing the multi-level transistor are disclosed. The multi-level transistor comprises a substrate comprising a first active region, a first transistor formed on the first active region, a first insulating layer covering the first transistor, and adapted to isolate the first active region, a second active region comprising a patterned first selective epitaxial growth (SEG) layer formed on the first insulating layer, and a second transistor formed on the second active region.
摘要翻译：公开了一种包括具有单晶特性的第二有源区和多电平晶体管的制造方法的多电平晶体管。所述多电平晶体管包括衬底，所述衬底包括第一有源区，形成在所述第一有源区上的第一晶体管，覆盖所述第一晶体管的第一绝缘层，并且适于隔离所述第一有源区;第二有源区，形成在第一绝缘层上的选择性外延生长（SEG）层和形成在第二有源区上的第二晶体管。

20. 发明授权

US06626968B2 Slurry for chemical mechanical polishing process and method of manufacturing semiconductor device using the same 失效
公开(公告)号：US06626968B2
公开(公告)日：2003-09-30
申请号：US09861697
申请日：2001-05-21
申请人： Young-rae Park , Jung-yup Kim , Bo-un Yoon , Kwang-bok Kim , Jae-phil Boo , Jong-won Lee , Sang-rok Hah , Kyung-hyun Kim , Chang-ki Hong
发明人： Young-rae Park , Jung-yup Kim , Bo-un Yoon , Kwang-bok Kim , Jae-phil Boo , Jong-won Lee , Sang-rok Hah , Kyung-hyun Kim , Chang-ki Hong
IPC分类号： C09G102
CPC分类号： H01L21/76224 , B24B37/044 , C09G1/02 , H01L21/31053
摘要： A slurry composition useful for chemical mechanical polishing of the surface of a material layer, e.g., a silicon oxide layer, is disclosed. A first material surface which is exposed to the slurry exhibits hydrophilicity, while a second material layer, e.g., a polysilicon layer, the surface of which is also exposed to the slurry, exhibits hydrophobicity, and accordingly acts as a polishing stopping layer. The slurry composition consists essentially of water, abrasive grains, and a polymer additive having both hydrophilic and hydrophobic functional groups.

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