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11. 发明授权

US07630208B2 Multilayer chip capacitor, circuit board apparatus having the capacitor, and circuit board 有权
标题翻译：多层片式电容器，具有电容器的电路板装置和电路板
公开(公告)号：US07630208B2
公开(公告)日：2009-12-08
申请号：US12198342
申请日：2008-08-26
申请人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC分类号： H05K1/16
CPC分类号： H01G4/232 , H01G4/012 , H01G4/30 , H01G4/385 , H05K1/0231 , H05K1/113 , H05K2201/09309 , H05K2201/09772 , H05K2201/0979 , H05K2201/10015 , H05K2201/10636 , Y02P70/611
摘要： Provided is a multilayer chip capacitor including a capacitor body having first and second capacitor units arranged in a lamination direction; and a plurality of external electrodes formed outside the capacitor body. The first capacitor unit includes at least one pair of first and second internal electrodes disposed alternately in an inner part of the capacitor body, the second capacitor unit includes a plurality of third and fourth internal electrodes disposed alternately in an inner part of the capacitor body, and the first to fourth internal electrodes are coupled to the first to fourth external electrodes. The first capacitor unit has a lower equivalent series inductance (ESL) than the second capacitor unit, and the first capacitor unit has a higher equivalent series resistance (ESR) than the second capacitor unit.
摘要翻译：本发明提供一种多层片状电容器，其包括具有层叠方向配置的第一和第二电容器单元的电容器体; 以及形成在电容器主体外部的多个外部电极。第一电容器单元包括交替设置在电容器主体的内部的至少一对第一和第二内部电极，第二电容器单元包括交替设置在电容器主体内部的多个第三和第四内部电极，并且第一至第四内部电极耦合到第一至第四外部电极。第一电容器单元具有比第二电容器单元更低的等效串联电感（ESL），并且第一电容器单元具有比第二电容器单元更高的等效串联电阻（ESR）。

12. 发明申请

US20080158773A1 Multilayer capacitor array 有权
标题翻译：多层电容阵列
公开(公告)号：US20080158773A1
公开(公告)日：2008-07-03
申请号：US11979875
申请日：2007-11-09
申请人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC分类号： H01G4/228 , H01G4/005
CPC分类号： H01G4/232 , H01G4/005 , H01G4/30 , H03H2001/0014
摘要： A multilayer capacitor array having a plurality of multilayer capacitor devices formed in a single multilayer structure, the multilayer capacitor array including: a capacitor body formed by depositing a plurality of dielectric layers and having first and second side surfaces opposite to each other; a plurality of first polarity internal electrodes and second polarity internal electrodes, disposed oppositely to each other in the capacitor body, interposing the dielectric layer there between, and formed of a single electrode plate comprising a single lead, respectively; and a plurality of first polarity external electrodes and second polarity external electrodes, formed on the first side surface and second side surface, respectively, and connected to a correspondent polarity internal electrode via the lead, the first polarity external electrode formed on the first side surface and the second polarity external electrode formed on the second side surface, wherein the numbers of the first polarity external electrodes and the second polarity external electrodes are two or more, respectively, and are identical to each other, and a total number of the multilayer capacitor devices in the multilayer capacitor array is identical to the number of the first polarity external electrodes.
摘要翻译： 1.一种多层电容器阵列，具有形成为单层多层结构的多层多层电容器件，所述层叠电容器阵列包括：通过沉积多个电介质层而形成的电容器体，并且具有彼此相对的第一和第二侧面; 多个第一极性内部电极和第二极性内部电极，其彼此相对设置在电容器主体中，分别在其间插入电介质层，并由单个引线构成的单个电极板形成; 以及多个第一极性外部电极和第二极性外部电极，分别形成在所述第一侧面和所述第二侧面上，并且经由所述引线与相应的极性内部电极连接，所述第一极性外部电极形成在所述第一侧面和形成在第二侧面上的第二极性外部电极，其中第一极性外部电极和第二极性外部电极的数量分别为两个或更多个，并且彼此相同，并且层叠电容器的总数多层电容器阵列中的器件与第一极性外部电极的数量相同。

13. 发明授权

US08117584B2 Method of implementing low ESL and controlled ESR of multilayer capacitor 有权
标题翻译：实现低ESL和多层电容控制ESR的方法
公开(公告)号：US08117584B2
公开(公告)日：2012-02-14
申请号：US12155805
申请日：2008-06-10
申请人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC分类号： G06F17/50 , H01G4/30 , H01G4/055 , H01G4/288
CPC分类号： H01G4/232 , H01G4/30
摘要： Disclosed is a method of implementing controlled equivalent series resistance (ESR) having low equivalent series inductance (ESL) of a multi-layer chip capacitor which includes a plurality of internal electrodes each having first polarity or second polarity which is opposite to the first polarity, and dielectric layers each disposed between the internal electrodes of the first polarity and the second polarity, wherein the internal electrodes having the first polarity and the internal electrodes having the second polarity are alternated at least once to form one or more blocks being stacked.
摘要翻译：公开了一种实现具有低等效串联电感（ESL）的受控等效串联电阻（ESR）的方法，该多层片式电容器包括多个内部电极，每个内部电极具有与第一极性相反的第一极性或第二极性，以及电介质层，其各自设置在第一极性和第二极性的内部电极之间，其中具有第一极性的内部电极和具有第二极性的内部电极至少交替一次以形成一个或多个堆叠的块。

14. 发明授权

US07920370B2 Multilayer chip capacitor 有权
公开(公告)号：US07920370B2
公开(公告)日：2011-04-05
申请号：US11987835
申请日：2007-12-05
申请人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC分类号： H01G4/228 , H01G4/248 , H01G4/06
CPC分类号： H01G4/30 , H01G4/012 , H01G4/232
摘要： A multilayer chip capacitor includes: a capacitor body having first and second side surfaces and a bottom surface; a plurality of first and second internal electrodes in the capacitor body; first and second external electrodes having a first polarity and formed on the first and second side surfaces, respectively, to cover a respective lower edge of the side surfaces and to partially extend to the bottom surface; and a third external electrode having a second polarity and formed on the bottom surface. The internal electrodes are disposed in perpendicular to the bottom surface. Each of the first internal electrodes has a first lead drawn to the first side and bottom surfaces and a second lead drawn to the second side and bottom surfaces. Each of the second internal electrodes has a third lead drawn to the bottom surface.

15. 发明授权

US07733628B2 Multilayer chip capacitor 有权
标题翻译：多层片式电容器
公开(公告)号：US07733628B2
公开(公告)日：2010-06-08
申请号：US12005300
申请日：2007-12-27
申请人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC分类号： H01G4/228 , H01G4/06
CPC分类号： H01G4/232 , H01G4/012 , H01G4/30
摘要： A multilayer chip capacitor including: a capacitor body having a plurality of dielectric layers deposited therein and having a parallelepiped shape; at least three pairs of first and second external electrodes formed on two longer sides, the first and second external electrodes in each of the pairs having different polarities and opposing each other, and the first and second external electrodes on each of the longer sides arranged alternately with each other; and a plurality of first and second internal electrodes arranged alternately to interpose each of the dielectric layers, the first and second internal electrodes connected to the first and second external electrodes by leads, respectively, wherein the capacitor body has a length that is 2.5 times greater than a width thereof.
摘要翻译：一种多层片状电容器，包括：具有沉积在其中并具有平行六面体形状的多个电介质层的电容器主体; 形成在两个长边上的至少三对第一和第二外部电极，每对中的第一和第二外部电极具有不同的极性并且彼此相对，并且每个长边上的第一和第二外部电极交替布置彼此; 并且交替地布置多个第一和第二内部电极以分别插入每个电介质层，第一和第二内部电极分别通过引线连接到第一和第二外部电极，其中电容器主体具有2.5倍的长度比其宽度。

16. 发明申请

US20090244803A1 MULTILAYER CHIP CAPACITOR 有权
标题翻译：多层芯片电容器
公开(公告)号：US20090244803A1
公开(公告)日：2009-10-01
申请号：US12245856
申请日：2008-10-06
申请人： Byoung Hwa LEE , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa LEE , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC分类号： H01G4/30
CPC分类号： H01G4/30 , H01G4/012 , H01G4/232
摘要： A multilayer chip capacitor includes a capacitor body including a first capacitor part and a second capacitor part, first and second external electrodes respectively formed on first and second longer side faces of the capacitor body, and third and fourth external electrodes respectively formed on first and second shorter side faces of the capacitor body. The first capacitor part includes first and second internal electrodes of opposite polarity, and the second capacitor part includes third and fourth internal electrodes of opposite polarity. The first to fourth internal electrodes each have one lead. The first to fourth external electrodes are respectively connected to the leads of the first to fourth internal electrodes. A series resonance frequency of the first capacitor part is different from that of the second capacitor part. Equivalent series resistance (ESR1) of the first capacitor part and the equivalent series resistance (ESR2) of the second capacitor part satisfy ERS1≧20 mΩ and 0.7(ESR1)≦ESR2≦1.3(ESR1).
摘要翻译：多层片状电容器包括电容器本体，其包括第一电容器部分和第二电容器部分，分别形成在电容器主体的第一和第二长侧面上的第一和第二外部电极，以及分别形成在第一和第二电极部分上的第三和第四外部电极电容器主体的较短侧面。第一电容器部分包括具有相反极性的第一和第二内部电极，并且第二电容器部分包括具有相反极性的第三和第四内部电极。第一至第四内部电极各有一个引线。第一至第四外部电极分别连接到第一至第四内部电极的引线。第一电容器部分的串联谐振频率与第二电容器部分的串联谐振频率不同。第一电容器部分的等效串联电阻（ESR1）和第二电容器部分的等效串联电阻（ESR2）满足ERS1> = 20mOmega和0.7（ESR1）<= ESR2 <= 1.3（ESR1）。

17. 发明申请

US20090034154A1 MULTILAYER CHIP CAPACITOR 有权
标题翻译：多层芯片电容器
公开(公告)号：US20090034154A1
公开(公告)日：2009-02-05
申请号：US12010018
申请日：2008-01-18
申请人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC分类号： H01G4/005
CPC分类号： H01G4/232 , H01G4/012 , H01G4/30
摘要： A multilayer chip capacitor includes: a capacitor body; internal electrodes disposed in the capacitor body, each internal electrode having one or more lead; and external electrodes disposed on first and second side surfaces of the capacitor body to be electrically connected to the internal electrodes through the leads. The average number of leads in each internal electrode is smaller than half (½) of the total number of external electrodes. The leads of the internal electrodes having opposite polarities and adjacent in the lamination direction are disposed to be adjacent to each other as seen from the lamination direction. All the internal electrodes having the same polarity are electrically connected to each other in the capacitor.
摘要翻译：多层片状电容器包括：电容器本体; 设置在电容器本体中的内部电极，每个内部电极具有一个或多个引线; 以及设置在电容器主体的第一和第二侧面上的外部电极，以通过引线与内部电极电连接。每个内部电极的引线平均数小于外部电极总数的一半（1/2）。具有相反极性并且在层叠方向上相邻的内部电极的引线设置成从层叠方向看彼此相邻。具有相同极性的所有内部电极在电容器中彼此电连接。

18. 发明授权

US08159813B2 Multilayer chip capacitor, motherboard apparatus having the same, and power distribution network 有权
标题翻译：多层片式电容器，具有相同的主板设备和配电网络
公开(公告)号：US08159813B2
公开(公告)日：2012-04-17
申请号：US12270330
申请日：2008-11-13
申请人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC分类号： H01G4/005 , H01G4/06
CPC分类号： H01G4/385 , H01G4/005 , H01G4/30 , H01L2224/16227 , H01L2924/15311 , H01L2924/19105
摘要： There is provided a multilayer chip capacitor including: a capacitor body including first and second capacitor units arranged in a laminated direction; and first to fourth outer electrodes formed on side surfaces of the capacitor body, respectively, wherein the first capacitor unit includes first and second inner electrodes of different polarities alternately arranged in the capacitor body to oppose each other while interposing a corresponding one of dielectric layers, the second capacitor unit includes third and fourth inner electrodes of different polarities alternately arranged in the capacitor body to oppose each other while interposing another corresponding one of the dielectric layers, the first and second capacitor units are electrically insulated from each other, and the first capacitor unit operates in a first frequency range and the second capacitor unit operates in a second frequency range lower than the first frequency range.
摘要翻译：提供了一种多层片状电容器，包括：电容器体，包括沿层叠方向布置的第一和第二电容器单元; 以及分别形成在电容器主体的侧面上的第一至第四外部电极，其中，所述第一电容器单元包括交替布置在所述电容器体中的第一和第二内部电极，所述第一和第二内部电极彼此相对，同时插入相应的一个电介质层，所述第二电容器单元包括具有不同极性的第三和第四内部电极，所述第三和第四内部电极交替地布置在所述电容器体中，以相对于彼此相对，同时插入另一个对应的一个所述介电层，所述第一和第二电容器单元彼此电绝缘，单元在第一频率范围内操作，并且第二电容器单元在低于第一频率范围的第二频率范围内操作。

19. 发明申请

US20100238605A1 MULTILAYER CHIP CAPACITOR AND METHOD OF FABRICATING THE SAME 有权
标题翻译：多层芯片电容器及其制造方法
公开(公告)号：US20100238605A1
公开(公告)日：2010-09-23
申请号：US12650134
申请日：2009-12-30
申请人： Byoung Hwa LEE , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa LEE , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC分类号： H01G4/228
CPC分类号： H01G4/232 , H01G2/065 , H01G4/30 , H05K1/0231 , H05K1/0295 , H05K1/181 , H05K2201/0979 , H05K2201/09954 , Y10T29/435
摘要： A multilayer chip capacitor includes: a capacitor main body; a plurality of first and second inner electrodes; and m (m≧3) number of first and second outer electrodes. The plurality of first and second inner electrodes are connected with two outer electrodes positioned on both opposing surfaces and having the same polarity as that of the first and second inner electrodes, and classified into a plurality of groups depending on the locations of the outer electrodes connected to the first and second inner electrodes. At least one of two outer electrodes connected with inner electrodes of each group is different from an outer electrode connected with inner electrodes of a different group having the same polarity, and inner electrodes of one group are connected to outer electrodes connected with at least another one group so that all the inner electrodes belonging to the same polarity can be electrically connected.
摘要翻译：一种多层片状电容器包括：电容器主体; 多个第一和第二内部电极; 和m（m≥3）个数的第一和第二外部电极。多个第一和第二内部电极与位于两个相对表面上并且具有与第一和第二内部电极相同的极性的两个外部电极连接，并且根据连接的外部电极的位置被分成多个组到第一和第二内部电极。与每组的内部电极连接的两个外部电极中的至少一个不同于与具有相同极性的不同组的内部电极连接的外部电极，并且一组的内部电极连接到与至少另一个连接的外部电极使得属于相同极性的所有内部电极可以电连接。

20. 发明授权

US07679882B2 Multilayered chip capacitor and capacitance tunning method of the same 失效
标题翻译：多层片式电容器和电容调谐方法相同
公开(公告)号：US07679882B2
公开(公告)日：2010-03-16
申请号：US12238688
申请日：2008-09-26
申请人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC分类号： H01G4/228
CPC分类号： H01G4/228 , H01G4/005 , H01G4/30 , H01G4/385
摘要： There is provided a multilayer chip capacitor capable of tuning capacitance, including: a capacitor body where a plurality of dielectric layers are laminated; a plurality of pairs of first and second internal electrodes arranged alternately, while interposing a corresponding one of the dielectric layers; and a plurality of pairs of first and second external electrodes connected to the first and second internal electrodes, wherein the first and second internal electrodes include a plurality of groups each including at least one pair of the first and second internal electrodes, and the first and second internal electrodes of each of the groups are connected to different pairs of the first and second external electrodes, respectively, wherein a corresponding one of the pairs of the first and second external electrodes is selectively connected to power lines so that the multilayer chip capacitor has at least two different capacitances.
摘要翻译：提供一种能够调谐电容的多层片状电容器，包括：电容器体，层叠多个电介质层; 多个成对的第一和第二内部电极交替布置，同时插入相应的一个电介质层; 以及连接到所述第一和第二内部电极的多对第一和第二外部电极，其中所述第一和第二内部电极包括多个组，每个组包括至少一对所述第一和第二内部电极，以及所述第一和第二内部电极每个组的第二内部电极分别连接到第一和第二外部电极的不同对，其中第一和第二外部电极对中的相应一个选择性地连接到电力线，使得多层片状电容器具有至少两个不同的电容。

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