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11. 发明授权

US07542043B1 Subdividing a shader program 有权
标题翻译：细分着色程序
公开(公告)号：US07542043B1
公开(公告)日：2009-06-02
申请号：US11136346
申请日：2005-05-23
申请人： John Erik Lindholm , Brett W. Coon , Gary M. Tarolli
发明人： John Erik Lindholm , Brett W. Coon , Gary M. Tarolli
IPC分类号： G06T1/20 , G06F5/80
CPC分类号： G06T1/60 , G06F8/4442 , G06F9/3834 , G06F9/3851 , G06F9/3885
摘要： Methods and apparatus for subdividing a shader program into regions or “phases” of instructions identifiable by phase identifiers (IDs) inserted into the shader program are provided. The phase IDs may be used to constrain execution of the shader program to prohibit texture fetches in later phases from being executed before a texture fetch in a current phase has completed. Other operations (e.g., math operations) within the current phase, however, may be allowed to execute while waiting for the current phase texture fetch to complete.
摘要翻译：提供了将着色器程序细分为通过插入到着色器程序中的相位标识符（ID）可识别的指令的区域或“阶段”的方法和装置。相位ID可以用于限制着色器程序的执行，以便在当前阶段的纹理提取完成之前禁止稍后阶段中的纹理提取被执行。然而，当前阶段的其他操作（例如，数学运算）可以在等待当前相位纹理提取完成的同时执行。

12. 发明授权

US07456835B2 Register based queuing for texture requests 有权
标题翻译：基于注册排队的纹理请求
公开(公告)号：US07456835B2
公开(公告)日：2008-11-25
申请号：US11339937
申请日：2006-01-25
申请人： John Erik Lindholm , John R. Nickolls , Simon S. Moy , Brett W. Coon
发明人： John Erik Lindholm , John R. Nickolls , Simon S. Moy , Brett W. Coon
IPC分类号： G06T11/40 , G06T15/00 , G06T1/00 , G09G5/00
CPC分类号： G06T11/60 , G09G5/363
摘要： A graphics processing unit can queue a large number of texture requests to balance out the variability of texture requests without the need for a large texture request buffer. A dedicated texture request buffer queues the relatively small texture commands and parameters. Additionally, for each queued texture command, an associated set of texture arguments, which are typically much larger than the texture command, are stored in a general purpose register. The texture unit retrieves texture commands from the texture request buffer and then fetches the associated texture arguments from the appropriate general purpose register. The texture arguments may be stored in the general purpose register designated as the destination of the final texture value computed by the texture unit. Because the destination register must be allocated for the final texture value as texture commands are queued, storing the texture arguments in this register does not consume any additional registers.
摘要翻译：图形处理单元可以排队大量纹理请求，以平衡纹理请求的可变性，而不需要大的纹理请求缓冲区。专用纹理请求缓冲区排队相对较小的纹理命令和参数。另外，对于每个排队的纹理命令，通常比纹理命令大得多的一组相关的纹理参数存储在通用寄存器中。纹理单元从纹理请求缓冲区中检索纹理命令，然后从相应的通用寄存器获取相关的纹理参数。纹理参数可以存储在指定为由纹理单元计算的最终纹理值的目的地的通用寄存器中。因为当纹理命令排队时，必须为目标寄存器分配最终纹理值，所以将纹理参数存储在该寄存器中不消耗任何其他寄存器。

13. 发明授权

US07366878B1 Scheduling instructions from multi-thread instruction buffer based on phase boundary qualifying rule for phases of math and data access operations with better caching 有权
标题翻译：基于具有更好缓存的数学和数据访问操作阶段的相位边界限定规则的多线程指令缓冲区的调度指令
公开(公告)号：US07366878B1
公开(公告)日：2008-04-29
申请号：US11404196
申请日：2006-04-13
申请人： Peter C. Mills , John Erik Lindholm , Brett W. Coon , Gary M. Tarolli , John Matthew Burgess
发明人： Peter C. Mills , John Erik Lindholm , Brett W. Coon , Gary M. Tarolli , John Matthew Burgess
IPC分类号： G06F9/50
CPC分类号： G06F9/3851 , G06F9/3838 , G06F9/3853 , G06F9/3867 , G06F9/3885
摘要： A processor buffers asynchronous threads. Current instructions requiring operations provided by a plurality of execution units are divided into phases, each phase having at least one math operation and at least one texture cache access operation. Instructions within each phase are qualified and prioritized, with texture cache access operations in a subsequent phase not qualified until all of the texture cache access operations in a current phase have completed. The instructions may be qualified based on the status of the execution unit needed to execute one or more of the instructions. The instructions may also be qualified based on an age of each instruction, a divergence potential, locality, thread diversity, and resource requirements. Qualified instructions may be prioritized based on execution units needed to execute current instructions and the execution units in use. One or more of the prioritized instructions is issued per cycle to the plurality of execution units.
摘要翻译：处理器缓冲异步线程。由多个执行单元提供的需要操作的当前指令被划分为相位，每个相位具有至少一个数学运算和至少一个纹理高速缓存存取操作。每个阶段内的指令都是合格的并且是优先级排序的，后续阶段的纹理高速缓存访问操作在当前阶段的所有纹理缓存访问操作都已经完成之前不合格。可以基于执行一个或多个指令所需的执行单元的状态来限制指令。指令也可以根据每个指令的年龄，分歧潜力，局部性，线程分集和资源需求进行限定。可以根据执行当前指令所需的执行单元和正在使用的执行单元，优先考虑合格的指令。每个周期向多个执行单元发出一个或多个优先指令。

14. 发明授权

US08860737B2 Programmable graphics processor for multithreaded execution of programs 有权
标题翻译：用于多线程执行程序的可编程图形处理器
公开(公告)号：US08860737B2
公开(公告)日：2014-10-14
申请号：US11458633
申请日：2006-07-19
申请人： John Erik Lindholm , Brett W. Coon , Stuart F. Oberman , Ming Y. Siu , Matthew P. Gerlach
发明人： John Erik Lindholm , Brett W. Coon , Stuart F. Oberman , Ming Y. Siu , Matthew P. Gerlach
IPC分类号： G06F15/16 , G06F15/80 , G06T1/20 , G06T15/00 , G06F12/08 , G06T15/10
CPC分类号： G06T15/005 , G06F12/0811 , G06F12/0815 , G06F12/0875 , G06T15/10
摘要： A processing unit includes multiple execution pipelines, each of which is coupled to a first input section for receiving input data for pixel processing and a second input section for receiving input data for vertex processing and to a first output section for storing processed pixel data and a second output section for storing processed vertex data. The processed vertex data is rasterized and scan converted into pixel data that is used as the input data for pixel processing. The processed pixel data is output to a raster analyzer.
摘要翻译：处理单元包括多个执行流水线，每个执行流水线连接到第一输入部分，用于接收用于像素处理的输入数据和用于接收用于顶点处理的输入数据的第二输入部分和用于存储经处理的像素数据的第一输出部分和用于存储经处理的顶点数据的第二输出部分。经处理的顶点数据被光栅化并扫描转换为用作像素处理的输入数据的像素数据。经处理的像素数据被输出到光栅分析器。

15. 发明授权

US08667256B1 Systems and method for managing divergent threads in a SIMD architecture 有权
标题翻译：用于管理SIMD架构中的发散线程的系统和方法
公开(公告)号：US08667256B1
公开(公告)日：2014-03-04
申请号：US12476088
申请日：2009-06-01
申请人： Brett W. Coon , John Erik Lindholm
发明人： Brett W. Coon , John Erik Lindholm
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00
CPC分类号： G06F9/3851 , G06F9/30181 , G06F9/322
摘要： One embodiment of a computing system configured to manage divergent threads in a thread group includes a stack configured to store at least one token and a multithreaded processing unit. The multithreaded processing unit is configured to perform the steps of fetching a program instruction, determining that the program instruction is a branch instruction, determining that the program instruction is not a return or break instruction, determining whether the program instruction includes a set-synchronization bit, and updating an active program counter, where the manner in which the active program counter is updated depends on a branch instruction type.
摘要翻译：被配置为管理线程组中的发散线程的计算系统的一个实施例包括配置成存储至少一个令牌和多线程处理单元的堆栈。多线程处理单元被配置为执行获取程序指令，确定程序指令是分支指令，确定程序指令不是返回或中断指令的步骤，确定程序指令是否包括设置同步位并且更新活动程序计数器，其中活动程序计数器的更新方式取决于分支指令类型。

16. 发明授权

US08312254B2 Indirect function call instructions in a synchronous parallel thread processor 有权
标题翻译：同步并行线程处理器中的间接函数调用指令
公开(公告)号：US08312254B2
公开(公告)日：2012-11-13
申请号：US12054255
申请日：2008-03-24
申请人： Brett W. Coon , John R. Nickolls , Lars Nyland , Peter C. Mills , John Erik Lindholm
发明人： Brett W. Coon , John R. Nickolls , Lars Nyland , Peter C. Mills , John Erik Lindholm
IPC分类号： G06F9/00
CPC分类号： G06F9/38 , G06F9/30054 , G06F9/30101 , G06F9/3851 , G06F9/3885
摘要： An indirect branch instruction takes an address register as an argument in order to provide indirect function call capability for single-instruction multiple-thread (SIMT) processor architectures. The indirect branch instruction is used to implement indirect function calls, virtual function calls, and switch statements to improve processing performance compared with using sequential chains of tests and branches.
摘要翻译：间接分支指令将地址寄存器作为参数，以便为单指令多线程（SIMT）处理器架构提供间接函数调用能力。间接分支指令用于实现间接函数调用，虚函数调用和switch语句，以提高处理性能，与使用连续的测试和分支链相比。

17. 发明授权

US08237705B2 Hierarchical processor array 有权
标题翻译：分层处理器阵列
公开(公告)号：US08237705B2
公开(公告)日：2012-08-07
申请号：US13270215
申请日：2011-10-10
申请人： John Erik Lindholm , John S. Montrym , Emmett M. Kilgariff , Simon S. Moy , Sean Jeffrey Treichler , Brett W. Coon , David Kirk , John Danskin
发明人： John Erik Lindholm , John S. Montrym , Emmett M. Kilgariff , Simon S. Moy , Sean Jeffrey Treichler , Brett W. Coon , David Kirk , John Danskin
IPC分类号： G06T5/00 , G06T15/50 , G06T15/10 , G06T1/20
CPC分类号： G06T1/20 , G06F9/3851 , G06F9/3887 , G06F9/5044 , G06T15/005
摘要： Apparatuses and methods are presented for a hierarchical processor. The processor comprises, at a first level of hierarchy, a plurality of similarly structured first level components, wherein each of the plurality of similarly structured first level components includes at least one combined function module capable of performing multiple classes of graphics operations, each of the multiple classes of graphics operations being associated with a different stage of graphics processing. The processor comprises, at a second level of hierarchy, a plurality of similarly structured second level components positioned within each one of the plurality of similarly structured first level components, wherein each of the plurality of similarly structured second level components is capable of carrying out different operations from the multiple classes of graphics operations, wherein each first level component is adapted to distribute work to the plurality of similarly structured second level components positioned within the first level component.
摘要翻译：为分级处理器提供了设备和方法。所述处理器在第一级别包括多个类似结构的第一级组件，其中所述多个类似结构的第一级组件中的每一个包括能够执行多类图形操作的至少一个组合功能模块，每个组件与不同阶段的图形处理相关联的多类图形操作。处理器在第二层次上包括定位在多个类似结构的第一级组件中的每一个内的多个类似结构的第二级组件，其中多个类似结构的第二级组件中的每一个能够执行不同的来自多类图形操作的操作，其中每个第一级组件适于将工作分配到定位在第一级组件内的多个相似结构的第二级组件。

18. 发明授权

US07836276B2 System and method for processing thread groups in a SIMD architecture 有权
标题翻译：在SIMD架构中处理线程组的系统和方法
公开(公告)号：US07836276B2
公开(公告)日：2010-11-16
申请号：US11292614
申请日：2005-12-02
申请人： Brett W. Coon , John Erik Lindholm
发明人： Brett W. Coon , John Erik Lindholm
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3885 , G06F9/3838 , G06F9/3851 , G06F9/3869 , G06F9/3887
摘要： A SIMD processor efficiently utilizes its hardware resources to achieve higher data processing throughput. The effective width of a SIMD processor is extended by clocking the instruction processing side of the SIMD processor at a fraction of the rate of the data processing side and by providing multiple execution pipelines, each with multiple data paths. As a result, higher data processing throughput is achieved while an instruction is fetched and issued once per clock. This configuration also allows a large group of threads to be clustered and executed together through the SIMD processor so that greater memory efficiency can be achieved for certain types of operations like texture memory accesses performed in connection with graphics processing.
摘要翻译： SIMD处理器有效利用其硬件资源来实现更高的数据处理吞吐量。 SIMD处理器的有效宽度通过以数据处理侧的速率的一小部分计时SIMD处理器的指令处理侧，并且通过提供多个执行流水线（每个具有多个数据路径）来扩展。因此，在每个时钟获取和发出一个指令的同时实现更高的数据处理吞吐量。该配置还允许通过SIMD处理器将大组线程聚类并一起执行，使得可以针对某些类型的操作（如结合图形处理执行的纹理存储器访问）实现更高的存储器效率。

19. 发明授权

US07834881B2 Operand collector architecture 有权
标题翻译：操作数收集架构
公开(公告)号：US07834881B2
公开(公告)日：2010-11-16
申请号：US11555649
申请日：2006-11-01
申请人： Samuel Liu , John Erik Lindholm , Ming Y Siu , Brett W. Coon , Stuart F. Oberman
发明人： Samuel Liu , John Erik Lindholm , Ming Y Siu , Brett W. Coon , Stuart F. Oberman
IPC分类号： G09G5/36 , G09G5/39 , G06F15/80
CPC分类号： G06F9/3012 , G06F9/30123 , G06F9/30167 , G06F9/3824 , G06F9/3851 , G06F9/3885
摘要： An apparatus and method for simulating a multi-ported memory using lower port count memories as banks. A collector units gather source operands from the banks as needed to process program instructions. The collector units also gather constants that are used as operands. When all of the source operands needed to process a program instruction have been gathered, a collector unit outputs the source operands to an execution unit while avoiding writeback conflicts to registers specified by the program instruction that may be accessed by other execution units.
摘要翻译：一种使用较低端口计数存储器作为存储体来模拟多端口存储器的装置和方法。收集器单元根据需要从银行收集源操作数，以处理程序指令。收集器单元还收集用作操作数的常量。当收集处理程序指令所需的所有源操作数时，收集器单元将源操作数输出到执行单元，同时避免与由其他执行单元访问的程序指令指定的寄存器的写回冲突。

20. 发明授权

US07353369B1 System and method for managing divergent threads in a SIMD architecture 有权
标题翻译：用于管理SIMD架构中的发散线程的系统和方法
公开(公告)号：US07353369B1
公开(公告)日：2008-04-01
申请号：US11180388
申请日：2005-07-13
申请人： Brett W. Coon , John Erik Lindholm
发明人： Brett W. Coon , John Erik Lindholm
IPC分类号： G06F9/00
CPC分类号： G06F9/3851 , G06F9/30072 , G06F9/30101 , G06F9/30145 , G06F9/321 , G06F9/3887
摘要： One embodiment of a computing system configured to manage divergent threads in a thread group includes a stack configured to store at least one token and a multithreaded processing unit. The multithreaded processing unit is configured to perform the steps of fetching a program instruction, determining that the program instruction is not a branch instruction, determining whether the program instruction includes a pop-synchronization bit, and updating an active program counter, where the fashion in which the active program counter is updated relates to whether the program instruction includes a pop-synchronization bit.
摘要翻译：被配置为管理线程组中的发散线程的计算系统的一个实施例包括配置成存储至少一个令牌和多线程处理单元的堆栈。多线程处理单元被配置为执行获取程序指令，确定程序指令不是分支指令，确定程序指令是否包括弹出同步位，以及更新活动程序计数器的步骤，其中，活动程序计数器的更新涉及程序指令是否包括弹出同步位。

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