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11. 发明授权

US6151671A System and method of maintaining and utilizing multiple return stack buffers 失效
公开(公告)号：US6151671A
公开(公告)日：2000-11-21
申请号：US27407
申请日：1998-02-20
申请人： Reynold V. D'Sa , Rebecca E. Hebda , Stavros Kalafatis , Alan B. Kyker , Robert B. Chaput
发明人： Reynold V. D'Sa , Rebecca E. Hebda , Stavros Kalafatis , Alan B. Kyker , Robert B. Chaput
IPC分类号： G06F9/38 , G06F9/42
CPC分类号： G06F9/3806 , G06F9/30054
摘要： An instruction pipeline in a microprocessor is provided. The instruction pipeline includes a plurality of pipeline units, each of the plurality of pipeline units processing a plurality of instructions. At least two of the plurality of pipeline units are a source of at least some of the instructions for the pipeline. The pipeline further includes at least two speculative return address stacks, each of the speculative return address stacks coupled is coupled to at least one of the instruction source units. Each of the speculative return return address stacks are capable of storing at least two speculative return addresses.

12. 发明授权

US6055630A System and method for processing a plurality of branch instructions by a plurality of storage devices and pipeline units 失效
标题翻译：用于通过多个存储设备和流水线单元处理多个分支指令的系统和方法
公开(公告)号：US6055630A
公开(公告)日：2000-04-25
申请号：US63205
申请日：1998-04-20
申请人： Reynold V. D'Sa , Alan B. Kyker , Gad S. Sheaffer , Gustavo P. Espinosa , Stavros Kalafatis , Rebecca E. Hebda
发明人： Reynold V. D'Sa , Alan B. Kyker , Gad S. Sheaffer , Gustavo P. Espinosa , Stavros Kalafatis , Rebecca E. Hebda
IPC分类号： G06F9/38 , G06F13/14
CPC分类号： G06F9/3808 , G06F9/3802 , G06F9/3806 , G06F9/3844 , G06F9/3863 , G06F9/3867
摘要： An instruction pipeline in a microprocessor is provided. The instruction pipeline includes a plurality of pipeline units, each of the pipeline units processing a plurality of instructions including branch instructions. The instruction pipeline further includes a plurality of storage device which store a respective branch information data. Each of the storage devices are associated with at least one of pipeline units. Each respective branch information data is determined as a function of at least one of the branch instructions processed. Two of the pipeline units include branch prediction circuitry for predicting branch direction as a function of the stored branch information data.
摘要翻译：提供微处理器中的指令流水线。指令流水线包括多个流水线单元，每个流水线单元处理包含分支指令的多个指令。指令流水线还包括存储各个分支信息数据的多个存储装置。每个存储设备与管道单元中的至少一个相关联。根据所处理的分支指令中的至少一个来确定各个分支信息数据。两个流水线单元包括用于根据存储的分支信息数据预测分支方向的分支预测电路。

13. 发明授权

US10025343B2 Data transfer between asynchronous clock domains 有权
公开(公告)号：US10025343B2
公开(公告)日：2018-07-17
申请号：US13991602
申请日：2011-12-28
申请人： Michael C. Rifani , Alan B. Kyker , Alan S. Geist , David M. Lee
发明人： Michael C. Rifani , Alan B. Kyker , Alan S. Geist , David M. Lee
IPC分类号： G06F1/12 , G06F13/42
摘要： Some implementations disclosed herein provide techniques and arrangements for transferring data between asynchronous clock domains. A synchronization signal may be generated by a first of the clock domains, and data may be transferred between the domains in response to the synchronization signal. Clock cycles of the second of the clock domains may be monitored in comparison to the synchronization signal to report the number of second clock domain cycles occurring per occurrence of the synchronization signal. This information may be recorded by testing and validation equipment to facilitate error analyses.

14. 发明授权

US07730281B2 System and method for storing immediate data 失效
标题翻译：用于存储即时数据的系统和方法
公开(公告)号：US07730281B2
公开(公告)日：2010-06-01
申请号：US11974995
申请日：2007-10-17
申请人： Alan B. Kyker , Per Hammarlund , Chan Lee , Robert F. Krick , Hitesh Ahuja , William Alexander , Joseph Rohlman
发明人： Alan B. Kyker , Per Hammarlund , Chan Lee , Robert F. Krick , Hitesh Ahuja , William Alexander , Joseph Rohlman
IPC分类号： G06F9/318 , G06F9/28
CPC分类号： G06F9/30178 , G06F9/30156 , G06F9/3016 , G06F9/30167
摘要： An article comprising an instruction stored on a storage medium. The instruction includes opcode field storing an opcode signal and an operand field storing an operand signal. The operand is compressed prior to being stored in the operand field.
摘要翻译：一种包含存储在存储介质上的指令的物品。该指令包括存储操作码信号的操作码字段和存储操作数信号的操作数字段。操作数在存储在操作数字段之前被压缩。

15. 发明授权

US06850961B2 Method and system to perform a thread switching operation within a multithreaded processor based on detection of a stall condition 有权
标题翻译：基于检测失速条件在多线程处理器内执行线程切换操作的方法和系统
公开(公告)号：US06850961B2
公开(公告)日：2005-02-01
申请号：US10251583
申请日：2002-09-20
申请人： Stavros Kalafatis , Alan B. Kyker , Robert D. Fisch
发明人： Stavros Kalafatis , Alan B. Kyker , Robert D. Fisch
IPC分类号： G06F9/38 , G06F9/48 , G06R9/60
CPC分类号： G06F9/3802 , G06F9/3808 , G06F9/3844 , G06F9/3851
摘要： A method of performing a thread switching operation within a multithreaded processor includes detecting dispatch of a first predetermined quantity of instruction information of a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor. A stall condition relating to the first thread within a processor pipeline of the multithreaded processor is detected. The elapsing of a predetermined time interval subsequent to the detection of the stall condition is also detected. Responsive to the detection of the dispatch of the first predetermined quantity of instruction information for the first thread and the elapsing of the predetermined time interval, a thread switching operation is performed with respect to the output of the instruction streaming buffer.
摘要翻译：一种在多线程处理器内执行线程切换操作的方法，包括检测第一线程的第一预定量指令信息从指令流缓冲器到多线程处理器内的指令预解码器的调度。检测与多线程处理器的处理器流水线内的第一线程有关的失速状态。也检测到在停止状态的检测之后的预定时间间隔的经过。响应于检测第一线程的第一预定量指令信息的调度和预定时间间隔的经过，对指令流缓冲器的输出进行线程切换操作。

16. 发明授权

US06795845B2 Method and system to perform a thread switching operation within a multithreaded processor based on detection of a branch instruction 有权
标题翻译：基于检测到分支指令，在多线程处理器内执行线程切换操作的方法和系统
公开(公告)号：US06795845B2
公开(公告)日：2004-09-21
申请号：US10251204
申请日：2002-09-20
申请人： Stavros Kalafatis , Alan B. Kyker , Robert D. Fisch
发明人： Stavros Kalafatis , Alan B. Kyker , Robert D. Fisch
IPC分类号： G06F900
CPC分类号： G06F9/3802 , G06F9/3808 , G06F9/3844 , G06F9/3851
摘要： A method of performing a thread switching operation within a multithreaded processor includes detecting dispatch of a first predetermined quantity of instruction information of a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor. A branch instruction within the instruction information of the first thread to be dispatched from the instruction information source is also detected. Responsive to the detection of the branch instruction and the detection of the dispatch of the first predetermined quantity of instruction information of the first thread, a thread switching operation is performed with respect to the output of the instruction streaming buffer. The dispatch of instruction information of a second thread from the instruction streaming buffer is thus commenced.
摘要翻译：一种在多线程处理器内执行线程切换操作的方法，包括检测第一线程的第一预定量指令信息从指令流缓冲器到多线程处理器内的指令预解码器的调度。还检测从指令信息源发送的第一线程的指令信息内的分支指令。响应于分支指令的检测和对第一线程的第一预定量指令信息的调度的检测，针对指令流缓冲器的输出执行线程切换操作。因此开始从指令流缓存器发送第二线程的指令信息。

17. 发明授权

US06785890B2 Method and system to perform a thread switching operation within a multithreaded processor based on detection of the absence of a flow of instruction information for a thread 有权
标题翻译：在多线程处理器内执行线程切换操作的方法和系统，该方法和系统基于检测到一条线程的指令信息流不存在
公开(公告)号：US06785890B2
公开(公告)日：2004-08-31
申请号：US10251527
申请日：2002-09-20
申请人： Stavros Kalafatis , Alan B. Kyker , Robert D. Fisch
发明人： Stavros Kalafatis , Alan B. Kyker , Robert D. Fisch
IPC分类号： G06F1500
CPC分类号： G06F9/3802 , G06F9/3808 , G06F9/3844 , G06F9/3851
摘要： A method of performing a thread switching operation within a multithreaded processor includes detecting the dispatch of a first predetermined quantity of instruction information of a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor. An absence of a flow of instruction information of the first thread into the instruction information source from an upstream source in a processor pipeline is detected. The elapsing of a predetermined time interval subsequent to the detection of the absence of the flow of the instruction information is also detected. Responsive to the detection of the dispatch of the first predetermined quantity of instruction information of the first thread, and responsive to the elapsing of the predetermined time interval, a thread switching operation is performed with respect to the output of the instruction streaming buffer. The dispatch of instruction information for a second thread from the instruction streaming buffer is thus commenced.
摘要翻译：一种在多线程处理器内执行线程切换操作的方法包括检测第一线程的第一预定量指令信息从指令流缓冲器到多线程处理器内的指令预解码器的调度。检测到来自处理器管线中的上游源的第一线程的指令信息流不存在于指令信息源中。还检测到在检测到指令信息的流动之后的预定时间间隔的经过。响应于检测第一线程的第一预定量指令信息的调度，并且响应于预定时间间隔的经过，针对指令流缓冲器的输出执行线程切换操作。因此开始从指令流缓存器发送第二线程的指令信息。

18. 发明授权

US07114057B2 System and method for storing immediate data 失效
公开(公告)号：US07114057B2
公开(公告)日：2006-09-26
申请号：US09984525
申请日：2001-10-30
申请人： Alan B. Kyker , Per Hammarlund , Chan Lee , Robert F. Krick , Hitesh Ahuja , William Alexander , Joseph Rohlman
发明人： Alan B. Kyker , Per Hammarlund , Chan Lee , Robert F. Krick , Hitesh Ahuja , William Alexander , Joseph Rohlman
IPC分类号： G06F9/318 , G06F9/28
CPC分类号： G06F9/30178 , G06F9/30156 , G06F9/3016 , G06F9/30167
摘要： An article comprising an instruction stored on a storage medium. The instruction includes opcode field storing an opcode signal and an operand field storing an operand signal. The operand is compressed prior to being stored in the operand field.

19. 发明授权

US06971104B2 Method and system to perform a thread switching operation within a multithreaded processor based on dispatch of a quantity of instruction information for a full instruction 失效
标题翻译：在多线程处理器内执行线程切换操作的方法和系统，该方法和系统基于用于完整指令的指令信息量的分派
公开(公告)号：US06971104B2
公开(公告)日：2005-11-29
申请号：US10251508
申请日：2002-09-20
申请人： Stavros Kalafatis , Alan B. Kyker , Robert D. Fisch
发明人： Stavros Kalafatis , Alan B. Kyker , Robert D. Fisch
IPC分类号： G06F9/38 , G06F9/48 , G06F9/00
CPC分类号： G06F9/3802 , G06F9/3808 , G06F9/3844 , G06F9/3851
摘要： A method of performing a thread switching operation within a multithreaded processor includes detecting dispatch of a first predetermined quantity of instruction information of a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor. Responsive to the detection of the dispatch of the first predetermined quantity of instruction information for the first thread, a thread switching operation is performed with respect to the output of the instruction streaming buffer. The dispatch of instruction information for a second thread from the instruction streaming buffer is thus commenced. The predetermined quantity of the instruction information may be equal to or greater than a minimum quantity of instruction information for a full instruction of a first instruction set.
摘要翻译：一种在多线程处理器内执行线程切换操作的方法，包括检测第一线程的第一预定量指令信息从指令流缓冲器到多线程处理器内的指令预解码器的调度。响应于对第一线程的第一预定量的指令信息的调度的检测，针对指令流缓冲器的输出执行线程切换操作。因此开始从指令流缓存器发送第二线程的指令信息。指令信息的预定量可以等于或大于用于第一指令集的完整指令的指令信息的最小量。

20. 发明授权

US06854118B2 Method and system to perform a thread switching operation within a multithreaded processor based on detection of a flow marker within an instruction information 有权
标题翻译：基于在指令信息内的流标记的检测来执行多线程处理器内的线程切换操作的方法和系统
公开(公告)号：US06854118B2
公开(公告)日：2005-02-08
申请号：US10251599
申请日：2002-09-20
申请人： Stavros Kalafatis , Alan B. Kyker , Robert D. Fisch
发明人： Stavros Kalafatis , Alan B. Kyker , Robert D. Fisch
IPC分类号： G06F9/38 , G06F9/48 , G06F9/00
CPC分类号： G06F9/3802 , G06F9/3808 , G06F9/3844 , G06F9/3851
摘要： A method of performing a thread switching operation within a multithreaded processor includes detecting dispatch of a first predetermined quantity of instruction information of a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor. A flow marker within instruction information for the first thread received at the instruction information source is also detected. Responsive to the detection of the dispatch of the first predetermined quantity of instruction information of the first thread, and responsive to the detection of the flow marker, a thread switching operation is performed with respect to the output of the instruction streaming buffer. The dispatch of instruction information of a second thread from the instruction streaming buffer is thus commenced.
摘要翻译：一种在多线程处理器内执行线程切换操作的方法，包括检测第一线程的第一预定量指令信息从指令流缓冲器到多线程处理器内的指令预解码器的调度。还检测在指令信息源处接收到的第一线程的指令信息内的流标记。响应于检测第一线程的第一预定量的指令信息的调度，并且响应于流标记的检测，针对指令流缓冲器的输出执行线程切换操作。因此开始从指令流缓存器发送第二线程的指令信息。

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