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11. 发明申请

US20070108537A1 CORNER DOMINATED TRIGATE FIELD EFFECT TRANSISTOR 有权
标题翻译：角陶瓷触发场效应晶体管
公开(公告)号：US20070108537A1
公开(公告)日：2007-05-17
申请号：US11164216
申请日：2005-11-15
申请人： Brent Anderson , Andres Bryant , Jeffrey Johnson , Edward Nowak
发明人： Brent Anderson , Andres Bryant , Jeffrey Johnson , Edward Nowak
IPC分类号： H01L21/8244
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/66795
摘要： Disclosed are embodiments of a trigate field effect transistor that comprises a fin-shaped semiconductor body with a channel region and source/drain regions on either side of the channel region. Thick gate dielectric layers separate the top surface and opposing sidewalls of the channel region from the gate conductor in order to suppress conductivity in the channel planes. A thin gate dielectric layer separates the upper corners of the channel region from the gate conductor in order to optimize conductivity in the channel corners. To further emphasize the current flow in the channel corners, the source/drain regions can be formed in the upper corners of the semiconductor body alone. Alternatively, source/drain extension regions can be formed only in the upper corners of the semiconductor body adjacent to the gate conductor and deep source/drain diffusion regions can be formed in the ends of the semiconductor body.
摘要翻译：公开了一种触发场效应晶体管的实施例，其包括具有沟道区的鳍状半导体本体和沟道区两侧的源极/漏极区。厚栅电介质层将沟道区的顶表面和相对的侧壁与栅极导体分开，以便抑制沟道平面中的导电性。薄栅极电介质层将沟道区的上角与栅极导体分开，以便优化沟道角中的导电性。为了进一步强调通道角中的电流流动，源极/漏极区域可以单独形成在半导体主体的上角部。或者，源极/漏极延伸区域仅可以形成在与栅极导体相邻的半导体本体的上角处，并且可以在半导体本体的端部形成深的源极/漏极扩散区域。

12. 发明申请

US20070085134A1 SEMICONDUCTOR MEMORY DEVICE WITH INCREASED NODE CAPACITANCE 有权
标题翻译：具有增加的节点电容的半导体存储器件
公开(公告)号：US20070085134A1
公开(公告)日：2007-04-19
申请号：US10596029
申请日：2003-12-08
申请人： Brent Anderson , Andres Bryant , Edward Nowak
发明人： Brent Anderson , Andres Bryant , Edward Nowak
IPC分类号： H01L29/792 , H01L27/12 , H01L27/01 , H01L31/0392
CPC分类号： H01L27/1211 , H01L27/11 , H01L29/66795 , H01L29/785
摘要： An integrated circuit semiconductor memory device (100) has a first dielectric layer (116) characterized as the BOX layer absent from a portion (130) of the substrate (112) under the gate of a storage transistor to increase the gate-to-substrate capacitance and thereby reduce the soft error rate. A second dielectric layer (132) having a property different from the first dielectric layer at least partly covers that portion (130) of the substrate. The device may be a FinFET device including a fin (122) and a gate dielectric layer (124, 126) between the gate and the fin, with the second dielectric layer having less leakage than the gate dielectric layer.
摘要翻译：集成电路半导体存储器件（100）具有第一介电层（116），其特征在于，在存储晶体管的栅极下方的衬底（112）的部分（130）中不存在BOX层，以增加栅极到衬底电容，从而降低软错误率。具有不同于第一电介质层的性质的第二电介质层（132）至少部分地覆盖衬底的该部分（130）。器件可以是FinFET器件，其包括在栅极和鳍之间的鳍（122）和栅极电介质层（124,126），其中第二介电层具有比栅极电介质层更少的泄漏。

13. 发明申请

US20060267111A1 Double-gate FETs (Field Effect Transistors) 失效
标题翻译：双栅极FET（场效应晶体管）
公开(公告)号：US20060267111A1
公开(公告)日：2006-11-30
申请号：US11436480
申请日：2006-05-18
申请人： Brent Anderson , Andres Bryant , Edward Nowak
发明人： Brent Anderson , Andres Bryant , Edward Nowak
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/66795
摘要： A semiconductor structure and method for forming the same. The structure includes multiple fin regions disposed between first and second source/drain (S/D) regions. The structure further includes multiple front gates and back gates, each of which is sandwiched between two adjacent fin regions such that the front gates and back gates are alternating (i.e., one front gate then one back gate and then one front gate, and so on). The widths of the front gates are greater than the widths of the back gates. The capacitances of between the front gates and the S/D regions are smaller than the capacitances of between the back gates and the S/D regions. The distances between the front gates and the S/D regions are greater than the distances between the back gates and the S/D regions.
摘要翻译：一种半导体结构及其形成方法。该结构包括设置在第一和第二源极/漏极（S / D）区域之间的多个鳍片区域。该结构还包括多个前门和后门，每个前门和后门夹在两个相邻鳍片区域之间，使得前门和后门交替（即，一个前门，然后一个后门，然后一个前门，等等）。前门的宽度大于后门的宽度。前门和S / D区之间的电容小于后门和S / D区之间的电容。前门和S / D区之间的距离大于后门和S / D区之间的距离。

14. 发明申请

US20060043616A1 FINFET WITH LOW GATE CAPACITANCE AND LOW EXTRINSIC RESISTANCE 有权
标题翻译：具有低门电容和低极限电阻的FINFET
公开(公告)号：US20060043616A1
公开(公告)日：2006-03-02
申请号：US10711170
申请日：2004-08-30
申请人： Brent Anderson , Andres Bryant , Edward Nowak
发明人： Brent Anderson , Andres Bryant , Edward Nowak
IPC分类号： H01L31/109
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/66795 , Y10S257/90
摘要： A FinFET device and a method of lowering a gate capacitance and extrinsic resistance in a field effect transistor, wherein the method comprises forming an isolation layer comprising a BOX layer over a substrate, configuring source/drain regions above the isolation layer, forming a fin structure over the isolation layer, configuring a first gate electrode adjacent to the fin structure, disposing a gate insulator between the first gate electrode and the fin structure, positioning a second gate electrode transverse to the first gate electrode, and depositing a third gate electrode on the fin structure, the first gate electrode, and the second gate electrode, wherein the isolation layer is formed beneath the insulator, the first gate electrode, and the fin structure. The method further comprises sandwiching the second gate electrode with a dielectric material. The fin structure is formed by depositing an oxide layer over a silicon layer.
摘要翻译： FinFET器件和降低场效应晶体管中的栅极电容和非固有电阻的方法，其中所述方法包括在衬底上形成包括BOX层的隔离层，在隔离层上方构成源/漏区，形成鳍结构在所述隔离层上方配置与所述鳍结构相邻的第一栅电极，在所述第一栅电极和所述鳍结构之间设置栅极绝缘体，将第二栅电极定位成横向于所述第一栅电极，以及将第三栅电极鳍结构，第一栅电极和第二栅电极，其中隔离层形成在绝缘体下方，第一栅电极和鳍结构之下。该方法还包括用电介质材料夹住第二栅电极。翅片结构通过在硅层上沉积氧化物层而形成。

15. 发明申请

US20060097329A1 FIN DEVICE WITH CAPACITOR INTEGRATED UNDER GATE ELECTRODE 有权
标题翻译：具有集成在门电极下的电容器的FIN器件
公开(公告)号：US20060097329A1
公开(公告)日：2006-05-11
申请号：US10904357
申请日：2004-11-05
申请人： Brent Anderson , Andres Bryant , Edward Nowak
发明人： Brent Anderson , Andres Bryant , Edward Nowak
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L27/1203 , H01L29/66795
摘要： A fin-type field effect transistor (FinFET) has a fin having a center channel portion, end portions comprising source and drain regions, and channel extensions extending from sidewalls of the channel portion of the fin. The structure also includes a gate insulator covering the channel portion and the channel extensions, and a gate conductor on the gate insulator. The channel extensions increase capacitance of the channel portion of the fin.
摘要翻译：翅片型场效应晶体管（FinFET）具有鳍状物，其具有中心沟道部分，端部包括源极和漏极区域以及从鳍片的沟道部分的侧壁延伸的沟道延伸部。该结构还包括覆盖沟道部分和沟道延伸部的栅极绝缘体以及栅极绝缘体上的栅极导体。通道扩展增加了鳍片的通道部分的电容。

16. 发明申请

US20050275045A1 LOW CAPACITANCE FET FOR OPERATION AT SUBTHRESHOLD VOLTAGES 有权
标题翻译：用于低压电压运行的低电容FET
公开(公告)号：US20050275045A1
公开(公告)日：2005-12-15
申请号：US10710007
申请日：2004-06-11
申请人： Brent Anderson , Andres Bryant , William Clark , Edward Nowak
发明人： Brent Anderson , Andres Bryant , William Clark , Edward Nowak
IPC分类号： H01L21/336 , H01L29/10 , H01L29/76 , H01L29/78 , H01L29/786
CPC分类号： H01L29/7833 , H01L29/1045 , H01L29/66537 , H01L29/6656 , H01L29/66583 , H01L29/7835 , H01L29/785
摘要： A field effect transistor (FET) has underlap regions adjacent to the channel doping region. The underlap regions have very low dopant concentrations of less than 1×1017/cc or 5×1016/cc and so tend to have a high resistance. The underlap regions reduce overlap capacitance and thereby increase switching speed. High resistance of the underlap regions is not problematic at subthreshold voltages because the channel doping region also has a high resistance at subthreshold voltages. Consequently, the present FET has low capacitance and high speed and is particularly well suited for operation in the subthreshold regime.
摘要翻译：场效应晶体管（FET）具有与沟道掺杂区域相邻的底部区域。底层区域具有小于1×10 17 / cc或5×10 16 / cc的非常低的掺杂剂浓度，因此倾向于具有高电阻。下层区域减少重叠电容，从而提高开关速度。欠电压区域的高电阻在亚阈值电压下是没有问题的，因为沟道掺杂区域在亚阈值电压下也具有高电阻。因此，本FET具有低电容和高速度，并且特别适合于在亚阈值状态下操作。

17. 发明申请

US20070020837A1 HIGH PERFORMANCE CAPACITORS IN PLANAR BACK GATES CMOS 失效
标题翻译：高性能电容器在平面背栅CMOS
公开(公告)号：US20070020837A1
公开(公告)日：2007-01-25
申请号：US11160999
申请日：2005-07-19
申请人： Andres Bryant , Edward Nowak , Richard Williams
发明人： Andres Bryant , Edward Nowak , Richard Williams
IPC分类号： H01L21/8238
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/0811 , H01L28/40 , H01L29/78648 , Y10T436/235 , Y10T436/25125 , Y10T436/2525 , Y10T436/25375
摘要： A method of manufacture and device for a dual-gate CMOS structure. The structure includes a first plate in an insulating layer and a second plate above the insulating layer electrically corresponding to the first plate. An isolation structure is between the first plate and the second plate.
摘要翻译：一种双栅极CMOS结构的制造方法和器件。该结构包括绝缘层中的第一板和与第一板电对应的绝缘层之上的第二板。隔离结构在第一板和第二板之间。

18. 发明申请

US20050245009A1 BACKGATED FINFET HAVING DIFERENT OXIDE THICKNESSES 失效
标题翻译：具有不同氧化层厚度的背面金属氧化物半导体
公开(公告)号：US20050245009A1
公开(公告)日：2005-11-03
申请号：US10709323
申请日：2004-04-28
申请人： Andres Bryant , Omer Dokumaci , Hussein Hanafi , Edward Nowak
发明人： Andres Bryant , Omer Dokumaci , Hussein Hanafi , Edward Nowak
IPC分类号： H01L21/265 , H01L21/00 , H01L21/335 , H01L21/336 , H01L21/84 , H01L29/423 , H01L29/786
CPC分类号： H01L29/785 , H01L29/42368 , H01L29/42384 , H01L29/66795 , H01L29/7856
摘要： A method of producing a backgated FinFET having different dielectric layer thickness on the front and back gate sides includes steps of introducing impurities into at least one side of a fin of a FinFET to enable formation of dielectric layers with different thicknesses. The impurity, which may be introduced by implantation, either enhances or retards dielectric formation.
摘要翻译：在前栅侧和后栅极侧制造具有不同介电层厚度的背景FinFET的方法包括将杂质引入FinFET的鳍的至少一侧的步骤，以形成具有不同厚度的电介质层。可以通过注入引入的杂质增强或延迟电介质形成。

19. 发明申请

US20080096384A1 METHOD OF FORMING DAMASCENE FILAMENT WIRES 有权
标题翻译：形成大片纤维线的方法
公开(公告)号：US20080096384A1
公开(公告)日：2008-04-24
申请号：US11839767
申请日：2007-08-16
申请人： Brent Anderson , Andres Bryant , Jeffrey Gambino , Anthony Stamper
发明人： Brent Anderson , Andres Bryant , Jeffrey Gambino , Anthony Stamper
IPC分类号： H01L21/4763
CPC分类号： H01L21/31144 , H01L21/76808 , H01L21/76811 , H01L21/76816 , H01L21/76831 , H01L21/76835 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a semiconductor device. A first dielectric layer is deposited on and in direct mechanical contact with the substrate. A first hard mask is deposited on the first dielectric layer. A first and second trench is formed within the first dielectric layer and the first hard mask. The second trench is wider than the first trench. A first conformal liner is deposited over the first hard mask and within the first and second trenches, a portion of which is removed, leaving a remaining portion of the first conformal liner in direct physical contact with the substrate, the first dielectric layer, and the first hard mask, and not on the first hard mask. Copper is deposited over the first conformal liner to overfill fill the first and second trenches and is planarized to remove an excess thereof to form a planar surface of the copper.
摘要翻译：一种形成半导体器件的方法。第一电介质层沉积在衬底上并与衬底直接机械接触。第一硬掩模沉积在第一介电层上。第一和第二沟槽形成在第一介电层和第一硬掩模内。第二沟槽比第一沟槽宽。第一保形衬垫沉积在第一硬掩模之上并且在第一和第二沟槽内，其一部分被去除，留下第一保形衬垫的剩余部分与衬底，第一介电层和第一个硬面罩，而不是在第一个硬面罩。铜沉积在第一保形衬垫上以过满填充第一和第二沟槽，并被平坦化以除去其过量以形成铜的平坦表面。

20. 发明申请

US20070254438A1 DOUBLE GATED TRANSISTOR AND METHOD OF FABRICATION 有权
标题翻译：双栅极晶体管和制造方法
公开(公告)号：US20070254438A1
公开(公告)日：2007-11-01
申请号：US11774663
申请日：2007-07-09
申请人： Andres Bryant , Meikei Ieong , K. Muller , Edward Nowak , David Fried , Jed Rankin
发明人： Andres Bryant , Meikei Ieong , K. Muller , Edward Nowak , David Fried , Jed Rankin
IPC分类号： H01L21/336
CPC分类号： H01L29/4908 , H01L21/823842 , H01L27/092 , H01L29/66795 , H01L29/785
摘要： A method for forming a transistor. A semiconductor substrate is provided. The semiconductor substrate is patterned to provide a first body edge. A first gate structure of a first fermi level is provided adjacent the first body edge. The semiconductor substrate is patterned to provide a second body edge. The first and second body edges of the semiconductor substrate define a transistor body. A second gate structure of a second fermi level is provided adjacent the second body edge. A substantially uniform dopant concentration density is formed throughout the transistor body.
摘要翻译：一种形成晶体管的方法。提供半导体衬底。图案化半导体衬底以提供第一本体边缘。在第一身体边缘附近提供第一费米能级的第一门结构。图案化半导体衬底以提供第二本体边缘。半导体衬底的第一和第二主体边缘限定晶体管体。在第二身体边缘附近设置第二费米能级的第二门结构。在整个晶体管本体中形成基本均匀的掺杂剂浓度密度。

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