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11. 发明申请

US20080265922A1 WAFER LEVEL INTERPOSER 失效
公开(公告)号：US20080265922A1
公开(公告)日：2008-10-30
申请号：US12169538
申请日：2008-07-08
申请人： Benjamin N. Eldridge , Carl V. Reynolds
发明人： Benjamin N. Eldridge , Carl V. Reynolds
IPC分类号： G01R1/073
CPC分类号： G01R1/07378 , G01R1/07307 , H01L2924/0002 , H01L2924/00
摘要： Double-sided interposer assemblies and methods for forming and using them. In one example of the invention, an interposer comprises a substrate having a first surface and a second surface opposite of said first surface, a first plurality of contact elements disposed on said first side of said substrate, and a second plurality of contact elements disposed on said second surface of said substrate, wherein said interposer connects electronic devices via said first and said second plurality of contact elements.
摘要翻译：双面插入器组件及其形成和使用方法。在本发明的一个示例中，插入器包括具有第一表面和与所述第一表面相对的第二表面的基板，设置在所述基板的所述第一侧上的第一多个接触元件和设置在所述第一表面上的第二多个接触元件所述基板的所述第二表面，其中所述插入件经由所述第一和第二多个接触元件连接电子器件。

12. 发明授权

US07084650B2 Apparatus and method for limiting over travel in a probe card assembly 失效
公开(公告)号：US07084650B2
公开(公告)日：2006-08-01
申请号：US10321743
申请日：2002-12-16
申请人： Timothy E. Cooper , Benjamin N. Eldridge , Carl V. Reynolds , Ravindra Vaman Shenoy
发明人： Timothy E. Cooper , Benjamin N. Eldridge , Carl V. Reynolds , Ravindra Vaman Shenoy
IPC分类号： G01R31/02
CPC分类号： G01R31/2887 , G01R3/00 , G01R31/2886
摘要： Methods and apparatuses for testing semiconductor devices are disclosed. Over travel stops limit over travel of a device to be tested with respect to probes of a probe card assembly. Feedback control techniques are employed to control relative movement of the device and the probe card assembly. A probe card assembly includes flexible base for absorbing excessive over travel of the device to be tested with respect to the probe card assembly.

13. 发明申请

US20090134897A1 APPARATUS AND METHOD FOR LIMITING OVER TRAVEL IN A PROBE CARD ASSEMBLY 审中-公开
标题翻译：用于在探针卡组件中限制行驶的装置和方法
公开(公告)号：US20090134897A1
公开(公告)日：2009-05-28
申请号：US12360433
申请日：2009-01-27
申请人： Timothy E. Cooper , Benjamin N. Eldridge , Carl V. Reynolds , Ravindra Vaman Shenoy
发明人： Timothy E. Cooper , Benjamin N. Eldridge , Carl V. Reynolds , Ravindra Vaman Shenoy
IPC分类号： G01R31/02
CPC分类号： G01R31/2887 , G01R3/00 , G01R31/2886
摘要： Methods and apparatuses for testing semiconductor devices are disclosed. Over travel stops limit over travel of a device to be tested with respect to probes of a probe card assembly. Feedback control techniques are employed to control relative movement of the device and the probe card assembly. A probe card assembly includes flexible base for absorbing excessive over travel of the device to be tested with respect to the probe card assembly.
摘要翻译：公开了用于测试半导体器件的方法和装置。相对于探针卡组件的探针，超行程停止限制要测试的设备的行程。采用反馈控制技术来控制装置和探针卡组件的相对运动。探针卡组件包括用于吸收相对于探针卡组件的待测试装置的过度行进的柔性基座。

14. 发明授权

US07047638B2 Method of making microelectronic spring contact array 失效
标题翻译：制造微电子弹簧接触阵列的方法
公开(公告)号：US07047638B2
公开(公告)日：2006-05-23
申请号：US10202712
申请日：2002-07-24
申请人： Benjamin N. Eldridge , Gaetan L. Mathieu , Carl V. Reynolds
发明人： Benjamin N. Eldridge , Gaetan L. Mathieu , Carl V. Reynolds
IPC分类号： H01R43/00
CPC分类号： G01R1/06744 , G01R1/06733 , G01R3/00 , Y10T29/49139 , Y10T29/49155 , Y10T29/49204 , Y10T29/49208 , Y10T29/49222 , Y10T29/49224
摘要： A method of making a microelectronic spring contact array comprises forming a plurality of spring contacts on a sacrificial substrate and then releasing the spring contacts from the sacrificial substrate. Each of the spring contacts has an elongated beam having a base end. The method of making the array includes attaching the spring contacts at their base ends to a base substrate after they have been released entirely from the sacrificial substrate, so that each contact extends from the base substrate to a distal end of its beams. The distal ends are aligned with a predetermined array of tip positions. In an embodiment of the invention, the spring contacts are formed by patterning contours of the spring contacts in a sacrificial layer on the sacrificial substrate. The walls of patterned recesses in the sacrificial layer define side profiles of the spring contacts, and a conductive material is deposited in the recesses to form the elongated beams of the spring contacts.
摘要翻译：制造微电子弹簧接触阵列的方法包括在牺牲衬底上形成多个弹簧触点，然后从牺牲衬底释放弹簧触头。每个弹簧触点具有带有基端的细长梁。制造阵列的方法包括在它们已经从牺牲基板完全释放之后将其基端处的弹簧触点附接到基底基板，使得每个触点从基底延伸到其波束的远端。远端与预定阵列的尖端位置对准。在本发明的一个实施例中，通过在牺牲衬底上的牺牲层中图形地形成弹簧触点的轮廓来形成弹簧触点。牺牲层中的图案化凹槽的壁限定弹簧触点的侧面轮廓，并且导电材料沉积在凹部中以形成弹簧触点的细长梁。

15. 发明授权

US07396236B2 Wafer level interposer 有权
标题翻译：晶圆级内插器
公开(公告)号：US07396236B2
公开(公告)日：2008-07-08
申请号：US09810871
申请日：2001-03-16
申请人： Benjamin N. Eldridge , Carl V. Reynolds
发明人： Benjamin N. Eldridge , Carl V. Reynolds
IPC分类号： H01R12/00
CPC分类号： G01R1/07378 , G01R1/07307 , H01L2924/0002 , H01L2924/00
摘要： Double-sided interposer assemblies and methods for forming and using them. In one example of the invention, an interposer comprises a substrate having a first surface and a second surface opposite of said first surface, a first plurality of contact elements disposed on said first side of said substrate, and a second plurality of contact elements disposed on said second surface of said substrate, wherein said interposer connects electronic devices via said first and said second plurality of contact elements.
摘要翻译：双面插入器组件及其形成和使用方法。在本发明的一个示例中，插入器包括具有第一表面和与所述第一表面相对的第二表面的基板，设置在所述基板的所述第一侧上的第一多个接触元件和设置在所述第一表面上的第二多个接触元件所述基板的所述第二表面，其中所述插入件经由所述第一和第二多个接触元件连接电子器件。

16. 发明授权

US06960923B2 Probe card covering system and method 失效
标题翻译：探针卡覆盖系统和方法
公开(公告)号：US06960923B2
公开(公告)日：2005-11-01
申请号：US10025303
申请日：2001-12-19
申请人： Benjamin N. Eldridge , Carl V. Reynolds
发明人： Benjamin N. Eldridge , Carl V. Reynolds
IPC分类号： G01R1/06 , G01R31/28 , H01L21/66 , G01R31/02
CPC分类号： G01R31/2851 , G01R31/2886
摘要： A probe card covering system includes a probe card for testing a die on a wafer, the probe card having contacts adapted for electrical engagement with the die; a removable cover connected to the probe card and positionable in a first position over the contacts of the probe card, the cover being movable to a second position exposing said contacts for the engagement with the die; and, wherein the cover is movable from the first position to the second position while the probe card is located in a wafer testing machine.
摘要翻译：探针卡覆盖系统包括用于测试晶片上的管芯的探针卡，探针卡具有适于与管芯电接合的触点; 可拆卸盖，其连接到探针卡并且可定位在探针卡的触点上方的第一位置，所述盖可移动到暴露所述触点以与模具接合的第二位置; 并且其中所述盖可以在所述探针卡位于晶片测试机中时从所述第一位置移动到所述第二位置。

17. 发明授权

US07843202B2 Apparatus for testing devices 有权
标题翻译：用于测试设备的设备
公开(公告)号：US07843202B2
公开(公告)日：2010-11-30
申请号：US11864690
申请日：2007-09-28
申请人： Eric D. Hobbs , Nobuhiro Kawamata , Andrew W. McFarland , Carl V. Reynolds , Yoichi Urakawa
发明人： Eric D. Hobbs , Nobuhiro Kawamata , Andrew W. McFarland , Carl V. Reynolds , Yoichi Urakawa
IPC分类号： G01R31/02
CPC分类号： G01R31/2863 , G01R31/2889 , G01R31/31905
摘要： Methods and apparatus for testing semiconductor devices are provided herein. In some embodiments, an assembly for testing semiconductor devices can include a probe card assembly; and a thermal barrier disposed proximate an upper surface of the probe card assembly, the thermal barrier can restrict thermal transfer between tester side boundary conditions and portions of the probe card assembly disposed beneath the thermal barrier.
摘要翻译：本文提供了测试半导体器件的方法和装置。在一些实施例中，用于测试半导体器件的组件可以包括探针卡组件; 以及设置在探针卡组件的上表面附近的热障，热障可以限制测试仪侧边界条件与布置在热障下方的探针卡组件的部分之间的热传递。

18. 发明授权

US06090237A Apparatus for restraining adhesive overflow in a multilayer substrate assembly during lamination 失效
标题翻译：用于在层压期间抑制多层基板组件中的粘合剂溢出的装置
公开(公告)号：US06090237A
公开(公告)日：2000-07-18
申请号：US13246
申请日：1998-01-26
申请人： Carl V. Reynolds , Alex M. Neussendorfer , Jeffrey K. Kennedy
发明人： Carl V. Reynolds , Alex M. Neussendorfer , Jeffrey K. Kennedy
IPC分类号： H01L21/48 , H05K1/18 , H05K3/46 , B32B31/20
CPC分类号： H01L21/4857 , B32B37/0023 , B32B37/26 , H01L21/481 , H01L24/49 , H05K3/4697 , H01L2223/54406 , H01L2223/54486 , H01L2224/48095 , H01L2224/48227 , H01L2224/48465 , H01L2224/49109 , H01L2924/00014 , H01L2924/01013 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/15153 , H01L2924/1517 , H01L2924/15331 , H01L2924/3011 , H05K1/183 , H05K2201/0133 , H05K2201/09845 , H05K3/4611 , Y10T29/49158
摘要： Resin overflow in the interior cavity of a multilayer substrate assembly during lamination is restricted and controlled by a plug inserted into the cavity prior to bonding. The plug is shaped to mate with the stepped vertical profile of the cavity. The plug may include sections of materials of different hardness to support the stepped vertical profile of the plug and to facilitate removal of the plug after lamination. The plug may also include textured surfaces to facilitate removal of the plug. Pressurized gas is introduced at the interface between the plug and the cavity surface to dislodge the plug and a vacuum may be applied to the top of the plug to facilitate removal. The cavity may also be coated with layer of photo sensitive material to protect the metal bonding surfaces in the cavity from damage by the plug and to prevent particulate contamination during lamination.
摘要翻译：层压期间多层基板组件的内腔中的树脂溢流被限制并通过在粘合之前插入空腔中的插塞来控制。插头被成形为与空腔的阶梯式垂直轮廓配合。塞子可以包括不同硬度的材料部分，以支撑塞子的阶梯式垂直轮廓，并且有助于在层压之后移除塞子。插头还可以包括纹理表面以便于移除插头。加压气体在插塞和腔体表面之间的界面处引入以移除插塞，并且可以将真空施加到插塞的顶部以便于移除。空腔还可以涂覆有感光材料层，以保护空腔中的金属粘结表面免受插塞的损坏并防止层压期间的颗粒污染。

19. 发明授权

US07330039B2 Method for making a socket to perform testing on integrated circuits 失效
标题翻译：一种套接字在集成电路上进行测试的方法
公开(公告)号：US07330039B2
公开(公告)日：2008-02-12
申请号：US11090614
申请日：2005-03-25
申请人： Igor Y. Khandros , Gaetan L. Mathieu , Carl V. Reynolds
发明人： Igor Y. Khandros , Gaetan L. Mathieu , Carl V. Reynolds
IPC分类号： G01R31/02
CPC分类号： G01R3/00 , G01R1/0433 , G01R1/0483 , G01R1/07378 , G01R31/2863 , H01L24/13 , H01L2224/131 , H01L2924/01046 , H01L2924/01055 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , Y10T29/49117 , Y10T29/4913 , Y10T29/49144 , Y10T29/49149 , Y10T29/49169 , Y10T29/49179 , Y10T29/49197 , Y10T29/49204 , Y10T29/4921 , Y10T29/49211 , Y10T29/49224 , Y10T29/53217 , Y10T29/53265 , H01L2924/014
摘要： A interconnect structure is inexpensively manufactured and easily insertable into a socket. The interconnect structure is manufactured by forming a sacrificial substrate with cavities that is covered by a masking material having openings corresponding to the cavities. A first plating process is performed by depositing conductive material, followed by coupling wires within the openings and performing another plating process by depositing more conductive material. The interconnect structure is completed by first removing the masking material and sacrificial substrate. Ends of the wires are coupled opposite now-formed contact structures to a board. To complete the socket, a support device is coupled to the board to hold a tested integrated circuit.
摘要翻译：互连结构廉价地制造并且容易地插入到插座中。通过形成具有由具有与空腔对应的开口的掩模材料覆盖的空腔的牺牲衬底来制造互连结构。通过沉积导电材料，然后在开口内连接线并通过沉积更多导电材料进行另一电镀工艺来执行第一电镀工艺。通过首先去除掩模材料和牺牲衬底来完成互连结构。电线的端部与现在形成的接触结构相对联接到电路板。要完成插座，支持设备耦合到电路板以保持测试的集成电路。

20. 发明授权

US06920689B2 Method for making a socket to perform testing on integrated circuits 失效
标题翻译：一种套接字在集成电路上进行测试的方法
公开(公告)号：US06920689B2
公开(公告)日：2005-07-26
申请号：US10310791
申请日：2002-12-06
申请人： Igor Y. Khandros , Gaetan L. Mathieu , Carl V. Reynolds
发明人： Igor Y. Khandros , Gaetan L. Mathieu , Carl V. Reynolds
IPC分类号： G01R1/04 , G01R1/073 , G01R3/00 , H01R43/02
CPC分类号： G01R3/00 , G01R1/0433 , G01R1/0483 , G01R1/07378 , G01R31/2863 , H01L24/13 , H01L2224/131 , H01L2924/01046 , H01L2924/01055 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , Y10T29/49117 , Y10T29/4913 , Y10T29/49144 , Y10T29/49149 , Y10T29/49169 , Y10T29/49179 , Y10T29/49197 , Y10T29/49204 , Y10T29/4921 , Y10T29/49211 , Y10T29/49224 , Y10T29/53217 , Y10T29/53265 , H01L2924/014
摘要： A interconnect structure is inexpensively manufactured and easily insertable into a socket. The interconnect structure is manufactured by forming a sacrificial substrate with cavities that is covered by a masking material having openings corresponding to the cavities. A first plating process is performed by depositing conductive material, followed by coupling wires within the openings and performing another plating process by depositing more conductive material. The interconnect structure is completed by first removing the masking material and sacrificial substrate. Ends of the wires are coupled opposite now-formed contact structures to a board. To complete the socket, a support device is coupled to the board to hold a tested integrated circuit.
摘要翻译：互连结构廉价地制造并且容易地插入到插座中。通过形成具有由具有与空腔对应的开口的掩模材料覆盖的空腔的牺牲衬底来制造互连结构。通过沉积导电材料，然后在开口内连接线并通过沉积更多导电材料进行另一电镀工艺来执行第一电镀工艺。通过首先去除掩模材料和牺牲衬底来完成互连结构。电线的端部与现在形成的接触结构相对联接到电路板。要完成插座，支持设备耦合到电路板以保持测试的集成电路。

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