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11. 发明授权

US07183156B2 Transistor structure, memory cell, DRAM, and method for fabricating a transistor structure in a semiconductor substrate 有权
标题翻译：晶体管结构，存储单元，DRAM以及在半导体衬底中制造晶体管结构的方法
公开(公告)号：US07183156B2
公开(公告)日：2007-02-27
申请号：US10975085
申请日：2004-10-28
申请人： Matthias Goldbach , Ulrich Frey , Björn Fischer
发明人： Matthias Goldbach , Ulrich Frey , Björn Fischer
IPC分类号： H01L21/8242
CPC分类号： H01L27/10888 , H01L27/10855 , H01L27/10867 , H01L27/10873 , H01L29/42368
摘要： Transistor structures, with one source/drain region connected to a charge storage device to be insulated includes an asymmetric gate conductor structure. At a first side wall, which faces the one source/drain region, the asymmetric gate conductor structure has a side wall oxide with a greater thickness and a bird's beak structure with a greater length than at an opposite, second side wall. An effective channel length is increased for the same feature size of the gate conductor structure. Memory cells can be realized in a higher density.
摘要翻译：晶体管结构，具有连接到待绝缘的电荷存储装置的一个源极/漏极区域包括非对称栅极导体结构。在面向一个源极/漏极区域的第一侧壁处，不对称栅极导体结构具有较大厚度的侧壁氧化物和具有比相对的第二侧壁长的长度的鸟嘴结构。对于栅极导体结构的相同特征尺寸，有效沟道长度增加。可以以更高的密度实现存储单元。

12. 发明申请

US20050173729A1 Fabrication method for a semiconductor structure and corresponding semiconductor structure 有权
标题翻译：半导体结构的制造方法和相应的半导体结构
公开(公告)号：US20050173729A1
公开(公告)日：2005-08-11
申请号：US11035705
申请日：2005-01-14
申请人： Ulrich Frey , Matthias Goldbach , Dirk Offenberg
发明人： Ulrich Frey , Matthias Goldbach , Dirk Offenberg
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8234 , H01L21/8239 , H01L27/085 , H01L27/105 , H01L29/49 , H01L29/739 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L29/4983 , H01L21/28247 , H01L21/823468 , H01L27/105 , H01L27/1052 , H01L29/6656
摘要： The present invention provides a fabrication method for a semiconductor structure and a corresponding semiconductor structure. The fabrication method comprises the following steps: provision of a semiconductor substrate (1) with a gate dielectric (5); provision of a plurality of multilayered, elongate gate stacks (GS1; GS2) which essentially run parallel to one another on the gate dielectric (5), which gate stacks have a bottommost layer (10) made of silicon; provision of a first liner layer (60) made of a first material over the gate stacks (GS1; GS2) and the gate dielectric (5) uncovered beside the latter, the thickness (h) of which liner layer is less than a thickness (h′) of the bottommost layer (10) made of silicon; provision of sidewall spacers (70) made of a second material on the vertical sidewalls of the gate stacks (GS1; GS2) over the first liner layer (60), a region of the first liner layer (60) over the gate dielectric (5) between the gate stacks (GS1; GS2) remaining free; selective removal of the first liner layer (60) with respect to the sidewall spacers (70) for the purpose of laterally uncovering the bottommost layer (10) made of silicon of the gate stacks (GS1; GS2); and selective oxidation of the uncovered bottommost layer (10) for the purpose of forming sidewall oxide regions (50′) on the gate stacks (GS1; GS2).
摘要翻译：本发明提供一种用于半导体结构和相应的半导体结构的制造方法。制造方法包括以下步骤：提供具有栅极电介质（5）的半导体衬底（1）; 提供多个多层细长的栅极叠层（GS1; GS2），其基本上在栅极电介质（5）上彼此平行地延伸，该栅极堆叠具有由硅制成的最底层（10）; 提供由栅极叠层（GS1; GS2）和栅极电介质（5）制成的由第一材料制成的第一衬垫层（60）未被覆盖在其后面，衬垫层的厚度（h）小于由硅制成的最下层（10）的厚度（h'）; 在第一衬垫层（60）上设置由栅极堆叠（GS1; GS2）的垂直侧壁上的由第二材料制成的侧壁间隔物（70），第一衬里层（60）的位于栅极电介质（5）在栅极堆栈（GS 1; GS 2）之间保持自由; 为了横向露出由栅极堆叠（GS1; GS2）的硅制成的最底层（10）的目的，相对于侧壁间隔物（70）选择性地去除第一衬里层（60）以及为了在栅极堆叠（GS1; GS2）上形成侧壁氧化物区域（50'），未覆盖的最底层（10）的选择性氧化。

13. 发明授权

US06642602B2 Self-terminating blow process of electrical anti-fuses 有权
标题翻译：电气自保险的自终止吹风过程
公开(公告)号：US06642602B2
公开(公告)日：2003-11-04
申请号：US10017036
申请日：2001-12-14
申请人： Gunther Lehmann , Ulrich Frey , Oliver Weinfurtner
发明人： Gunther Lehmann , Ulrich Frey , Oliver Weinfurtner
IPC分类号： H01L2900
CPC分类号： G11C17/18
摘要： An anti-fuse system composed of a multiplicity of anti-fuse circuits (24, 26, 28, N) connected across a voltage source (10) by a pair of conductors (16, 18). Each anti-fuse circuit comprising an anti-fuse (30) connected in a series with a blow or control transistor (36) and a control circuit (44) for monitoring the status of the anti-fuse (30), Control circuit (44) provides an “on” signal to the gate (38) of control transistor (36) only when a_“select_” signal is received at an input (46) of control circuit (44) and if anti-fuse (30) has not been blown. After the anti-fuse (30) is blown, control circuit (44) turns off the control transistor (36) thereby providing a constant power source voltage across each anti-fuse circuit (24, 26, 28, N) regardless of the number of parallel anti-fuses which have been blown.
摘要翻译：由多个由一对导体（16,18）跨过电压源（10）连接的反熔丝电路（24,26,28，N）组成的反熔丝系统。每个反熔丝电路包括与吹扫或控制晶体管（36）串联连接的反熔丝（30）和用于监视反熔丝（30）的状态的控制电路（44），控制电路（44）只有当控制电路（44）的输入端（46）接收到a_“select_”信号，并且如果反熔丝（30）没有被接收，则仅向控制晶体管（36）的栅极（38）提供“接通”信号被吹了在防熔丝（30）熔断之后，控制电路（44）关闭控制晶体管（36），从而在每个反熔丝电路（24,26,28，N）上提供恒定的电源电压，而不管数量如何平行的保险丝已被吹制。

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