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11. 发明授权

US08738891B1 Methods and systems for command acceleration in a video processor via translation of scalar instructions into vector instructions 有权
标题翻译：用于通过将标量指令转换为向量指令的视频处理器中的命令加速的方法和系统
公开(公告)号：US08738891B1
公开(公告)日：2014-05-27
申请号：US11267640
申请日：2005-11-04
申请人： Ashish Karandikar , Shirish Gadre , Amir H. Salek
发明人： Ashish Karandikar , Shirish Gadre , Amir H. Salek
IPC分类号： G06F9/00
CPC分类号： G06T1/60 , G06F3/14 , G06F9/3851 , G06F9/3887 , G06F12/0877 , G06T1/20 , G09G5/37 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/61 , H04N19/82 , H04N19/85 , H04N19/86
摘要： A method for implementing command acceleration. The method includes receiving a first set of instructions from a first processor, wherein the first set of instructions are formatted in accordance with a microarchitecture of the first processor. The first set of instructions are translated into a second set of instructions, wherein the second set of instructions are formatted in accordance with a microarchitecture of a second processor. The second set instructions are then transmitted to the second processor for execution by the second processor.
摘要翻译：一种实现命令加速的方法。该方法包括从第一处理器接收第一组指令，其中根据第一处理器的微架构对第一组指令进行格式化。第一组指令被转换成第二组指令，其中第二组指令根据第二处理器的微架构进行格式化。然后将第二组指令发送到第二处理器，以供第二处理器执行。

12. 发明申请

US20060176308A1 Multidimensional datapath processing in a video processor 有权
公开(公告)号：US20060176308A1
公开(公告)日：2006-08-10
申请号：US11267638
申请日：2005-11-04
申请人： Ashish Karandikar , Shirish Gadre , Stephen Lew , Christopher Cheng
发明人： Ashish Karandikar , Shirish Gadre , Stephen Lew , Christopher Cheng
IPC分类号： G06T1/00
CPC分类号： G06T1/60 , G06F3/14 , G06F9/3851 , G06F9/3887 , G06F12/0877 , G06T1/20 , G09G5/37 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/61 , H04N19/82 , H04N19/85 , H04N19/86
摘要： A multidimensional datapath processing system for a video processor for executing video processing operations. The video processor includes a scalar execution unit configured to execute scalar video processing operations and a vector execution unit configured to execute vector video processing operations. A data store memory is included for storing data for the vector execution unit. The data store memory includes a plurality of tiles having symmetrical bank data structures arranged in an array. The bank data structures are configured to support accesses to different tiles of each bank.

13. 发明申请

US20060176309A1 Video processor having scalar and vector components 有权
标题翻译：具有标量和矢量分量的视频处理器
公开(公告)号：US20060176309A1
公开(公告)日：2006-08-10
申请号：US11267700
申请日：2005-11-04
申请人： Shirish Gadre , Ashish Karandikar , Stephen Lew , Christopher Cheng
发明人： Shirish Gadre , Ashish Karandikar , Stephen Lew , Christopher Cheng
IPC分类号： G06T1/00
CPC分类号： G06T1/60 , G06F3/14 , G06F9/3851 , G06F9/3887 , G06F12/0877 , G06T1/20 , G09G5/37 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/61 , H04N19/82 , H04N19/85 , H04N19/86
摘要： A video processor for executing video processing operations. The video processor includes a host interface for implementing communication between the video processor and a host CPU. A memory interface is included for implementing communication between the video processor and a frame buffer memory. A scalar execution unit is coupled to the host interface and the memory interface and is configured to execute scalar video processing operations. A vector execution unit is coupled to the host interface and the memory interface and is configured to execute vector video processing operations.
摘要翻译：一种用于执行视频处理操作的视频处理器。视频处理器包括用于实现视频处理器和主机CPU之间的通信的主机接口。包括用于实现视频处理器和帧缓冲存储器之间的通信的存储器接口。标量执行单元耦合到主机接口和存储器接口，并且被配置为执行标量视频处理操作。向量执行单元耦合到主机接口和存储器接口，并被配置为执行向量视频处理操作。

14. 发明授权

US08725990B1 Configurable SIMD engine with high, low and mixed precision modes 有权
标题翻译：具有高，低和混合精度模式的可配置SIMD引擎
公开(公告)号：US08725990B1
公开(公告)日：2014-05-13
申请号：US11267393
申请日：2005-11-04
申请人： Ashish Karandikar , Pooja Agarwal
发明人： Ashish Karandikar , Pooja Agarwal
IPC分类号： G06F15/80
CPC分类号： G06T1/60 , G06F3/14 , G06F9/3851 , G06F9/3887 , G06F12/0877 , G06T1/20 , G09G5/37 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/61 , H04N19/82 , H04N19/85 , H04N19/86
摘要： A configurable SIMD engine in a video processor for executing video processing operations. The engine includes a SIMD component having a plurality of inputs for receiving input data and a plurality of outputs for providing output data. A plurality of execution units are included in the SIMD component. Each of the execution units comprise a first and a second data path, and are configured for selectively implementing arithmetic operations on a set of low precision or high precision inputs. Each of the execution units have a first configuration and a second configuration, such that the first data path and the second data path are combined to produce a single high precision output in the first configuration, and such that the first data path and the second data path are partitioned to produce a respective first low precision output and second low precision output in the second configuration.
摘要翻译：视频处理器中可配置的SIMD引擎，用于执行视频处理操作。引擎包括具有用于接收输入数据的多个输入和用于提供输出数据的多个输出的SIMD分量。多个执行单元包括在SIMD组件中。每个执行单元包括第一和第二数据路径，并且被配置为选择性地对一组低精度或高精度输入进行算术运算。每个执行单元具有第一配置和第二配置，使得第一数据路径和第二数据路径被组合以在第一配置中产生单个高精度输出，并且使得第一数据路径和第二数据路径被分割以在第二配置中产生相应的第一低精度输出和第二低精度输出。

15. 发明授权

US08493397B1 State machine control for a pipelined L2 cache to implement memory transfers for a video processor 有权
标题翻译：用于流水线L2缓存的状态机控制，以实现视频处理器的存储器传输
公开(公告)号：US08493397B1
公开(公告)日：2013-07-23
申请号：US11267119
申请日：2005-11-04
申请人： Zhiqiang Jonathan Su , Ashish Karandikar
发明人： Zhiqiang Jonathan Su , Ashish Karandikar
IPC分类号： G09G5/36 , G06T1/60 , G06F13/00
CPC分类号： G06T1/60 , G06F3/14 , G06F9/3851 , G06F9/3887 , G06F12/0877 , G06T1/20 , G09G5/37 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/61 , H04N19/82 , H04N19/85 , H04N19/86
摘要： A method for using a state machine to control a pipelined L2 cache to implement memory transfers for a video processor. The method includes accessing a queue of read requests from a video processor, and tracking each of a plurality of cache lines stored within the cache using a least recently used variable. For each a cache line hit out of the plurality of cache lines and corresponding to one of the read requests, the least recently used variable is adjusted for a remainder of the plurality of cache lines. A replacement cache line is determined by examining the least recently used variables for each of the plurality of cache lines. For each cache line miss, a cache line slot corresponding to the replacement cache line is allocated to store a new cache line responsive to the cache line miss.
摘要翻译：一种使用状态机来控制流水线L2高速缓存以实现视频处理器的存储器传输的方法。该方法包括访问来自视频处理器的读取请求的队列，并且使用最近最少使用的变量来跟踪存储在高速缓存内的多个高速缓存行中的每一条。对于每个从多个高速缓存线中打出并对应于读取请求之一的高速缓存行，对于多条高速缓存行的其余部分调整最近最少使用的变量。通过检查多个高速缓存行中的每一个的最近最少使用的变量来确定替换高速缓存行。对于每个高速缓存行缺失，分配与替换高速缓存行相对应的高速缓存行时隙，以响应于高速缓存行缺失来存储新的高速缓存行。

16. 发明申请

US20070079104A1 Dynamic detection of block boundaries on memory reads 有权
标题翻译：动态检测存储器读取中的块边界
公开(公告)号：US20070079104A1
公开(公告)日：2007-04-05
申请号：US11240854
申请日：2005-09-30
申请人： Mark Heuchert , Anujan Varma , Ashish Karandikar
发明人： Mark Heuchert , Anujan Varma , Ashish Karandikar
IPC分类号： G06F12/00
CPC分类号： G06F12/06
摘要： In some embodiments a processing device is disclosed. The processing device is configured to read data from a memory device. The processing device transmits a read request to the memory device for a data block at a certain address and reads the data block for the certain address from the memory device. The processing device dynamically detects boundaries for the data block read by detecting an alignment pattern in data received from the memory device. Other embodiments are otherwise disclosed herein.
摘要翻译：在一些实施例中，公开了一种处理装置。处理装置被配置为从存储装置读取数据。处理装置向特定地址的数据块向存储装置发送读取请求，并从存储装置读出特定地址的数据块。处理设备通过检测从存储设备接收的数据中的对准模式来动态地检测数据块读取的边界。其他实施例在此另外公开。

17. 发明授权

US08489839B1 Increasing memory capacity of a frame buffer via a memory splitter chip 有权
标题翻译：通过存储器分配器芯片增加帧缓冲器的存储容量
公开(公告)号：US08489839B1
公开(公告)日：2013-07-16
申请号：US12639728
申请日：2009-12-16
申请人： Ashish Karandikar , Kaustubh Sanghani , Jonah M. Alben , Shane Keil
发明人： Ashish Karandikar , Kaustubh Sanghani , Jonah M. Alben , Shane Keil
IPC分类号： G06F13/16
CPC分类号： G09G5/39 , G09G5/363 , G09G2360/06
摘要： The memory splitter chip couples multiple DRAM units to the PPU, thereby expanding the memory capacity available to the PPU for storing data and increasing the overall performance of the graphics processing system. The memory splitter chip includes logic for managing the transmission of data between the PPU and the DRAM units when the transmission frequencies and the burst lengths of the PPU interface and the DRAM interfaces differ. Specifically, the memory splitter chip implements an overlapping transmission mode, a pairing transmission mode or a combination of the two modes when the transmission frequencies or the burst lengths differ.
摘要翻译：存储器分配器芯片将多个DRAM单元耦合到PPU，从而扩展用于存储数据的PPU的可用存储器容量并增加图形处理系统的整体性能。当PPU接口和DRAM接口的传输频率和突发长度不同时，存储器分离器芯片包括用于在PPU和DRAM单元之间管理数据传输的逻辑。具体地，当传输频率或突发长度不同时，存储器分离器芯片实现重叠传输模式，配对传输模式或两种模式的组合。

18. 发明授权

US07380084B2 Dynamic detection of block boundaries on memory reads 有权
标题翻译：动态检测存储器读取中的块边界
公开(公告)号：US07380084B2
公开(公告)日：2008-05-27
申请号：US11240854
申请日：2005-09-30
申请人： Mark Heuchert , Anujan Varma , Ashish Karandikar
发明人： Mark Heuchert , Anujan Varma , Ashish Karandikar
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F9/26 , G06F9/34
CPC分类号： G06F12/06
摘要： In some embodiments a processing device is disclosed. The processing device is configured to read data from a memory device. The processing device transmits a read request to the memory device for a data block at a certain address and reads the data block for the certain address from the memory device. The processing device dynamically detects boundaries for the data block read by detecting an alignment pattern in data received from the memory device. Other embodiments are otherwise disclosed herein.
摘要翻译：在一些实施例中，公开了一种处理装置。处理装置被配置为从存储装置读取数据。处理装置向特定地址的数据块向存储装置发送读取请求，并从存储装置读出特定地址的数据块。处理设备通过检测从存储设备接收的数据中的对准模式来动态地检测数据块读取的边界。其他实施例在此另外公开。

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