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11. 发明授权

US07221195B2 MOSFET for synchronous rectification 有权
标题翻译： MOSFET用于同步整流
公开(公告)号：US07221195B2
公开(公告)日：2007-05-22
申请号：US11083470
申请日：2005-03-18
申请人： Anup Bhalla , Sik K. Lui
发明人： Anup Bhalla , Sik K. Lui
IPC分类号： H03B1/00
CPC分类号： H01L27/088 , H01L27/0629 , H01L29/7803 , H01L29/7813 , H01L2223/6644 , H01L2224/16145 , H01L2224/45144 , H01L2224/48247 , H03K17/165 , H01L2924/00
摘要： This invention discloses a new MOSFET device. The MOSFET device has an improved operation characteristic achieved by connecting a shunt FET of low impedance to the MOSFET device. The shunt FET is to shunt a transient current therethrough. The shunt FET is employed for preventing an inadvertent turning on of the MOSFET device. The inadvertent turning on of the MOSFET may occur when a large voltage transient occurs at the drain of the MOSFET device. By connecting the gate of the shunt FET to the drain of the MOSFET device, a low impedance path is provided at the right point of time during the circuit operation to shunt the current without requiring any external circuitry.
摘要翻译：本发明公开了一种新的MOSFET器件。 MOSFET器件具有通过将低阻抗的并联FET连接到MOSFET器件而实现的改进的操作特性。并联FET分流瞬态电流。分流FET用于防止MOSFET器件无意中导通。当在MOSFET器件的漏极处发生大的电压瞬变时，可能会发生MOSFET的无意开启。通过将分流FET的栅极连接到MOSFET器件的漏极，在电路操作期间在正确的时间点提供低阻抗路径，以分流电流而不需要任何外部电路。

12. 发明授权

US06841852B2 Integrated circuit package for semiconductor devices with improved electric resistance and inductance 有权
标题翻译：具有改善的电阻和电感的半导体器件的集成电路封装
公开(公告)号：US06841852B2
公开(公告)日：2005-01-11
申请号：US10189333
申请日：2002-07-02
申请人： Leeshawn Luo , Anup Bhalla , Yueh-Se Ho , Sik K. Lui , Mike Chang
发明人： Leeshawn Luo , Anup Bhalla , Yueh-Se Ho , Sik K. Lui , Mike Chang
IPC分类号： H01L21/60 , H01L23/485 , H01L23/495 , H01L23/50 , H01L23/48
CPC分类号： H01L24/85 , H01L23/49575 , H01L23/50 , H01L24/05 , H01L24/06 , H01L24/48 , H01L24/49 , H01L2224/04042 , H01L2224/05552 , H01L2224/05599 , H01L2224/05647 , H01L2224/0603 , H01L2224/48137 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/4903 , H01L2224/49111 , H01L2224/49171 , H01L2224/49431 , H01L2224/85447 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01029 , H01L2924/01047 , H01L2924/01075 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30107 , H01L2224/78 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor integrated circuit package having a leadframe (108) that includes a leadframe pad (103a) disposed under a die (100) and a bonding metal area (101a) that is disposed over at least two adjacent sides of the die. The increase in the bonding metal area (101a) increases the number of interconnections between the metal area (101a) and the die (100) to reduce the electric resistance and inductance. Furthermore, the surface area of the external terminals radiating from the package's plastic body (106) is increased if not maximized so that heat can be dissipated quicker and external terminal resistances reduced. The integrated circuit is applicable for MOSFET devices and the bonding metal area (101a) is used for the source terminal (101). The bonding metal area may have a “L” shape, a “C” shape, a “J” shape, an “I” shape or any combination thereof.
摘要翻译：一种半导体集成电路封装，具有引线框架（108），该引线框架（108）包括设置在管芯（100）下方的引线框架（103a）和设置在管芯的至少两个相邻侧面上的接合金属区域（101a）。接合金属区域（101a）的增加增加了金属区域（101a）和模具（100）之间的互连次数，以降低电阻和电感。此外，从封装的塑料体（106）辐射的外部端子的表面积如果没有最大化则增加，使得能够更快地消散热量并且降低外部端子电阻。集成电路适用于MOSFET器件，并且用于源极端子（101）的接合金属区域（101a）。接合金属区域可以具有“L”形，“C”形，“J”形，“I”形或其任何组合。

13. 发明申请

US20160247899A1 POWER MOSFET DEVICE STRUCTURE FOR HIGH FREQUENCY APPLICATIONS 审中-公开
标题翻译：功率MOSFET器件结构高频应用
公开(公告)号：US20160247899A1
公开(公告)日：2016-08-25
申请号：US14629229
申请日：2015-02-23
申请人： Anup Bhalla , Daniel Ng , Tiesheng Li , Sik K. Lui
发明人： Anup Bhalla , Daniel Ng , Tiesheng Li , Sik K. Lui
IPC分类号： H01L29/66 , H01L29/06 , H01L29/10 , H01L29/423 , H01L21/3213 , H01L29/08
CPC分类号： H01L29/66712 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/41775 , H01L29/42368 , H01L29/42372 , H01L29/42376 , H01L29/66719 , H01L29/66727 , H01L29/7802 , H01L29/7811 , H01L29/7827
摘要： This invention discloses a new switching device supported on a semiconductor that includes a drain disposed on a first surface and a source region disposed near a second surface of said semiconductor opposite the first surface. The switching device further includes an insulated gate electrode disposed on top of the second surface for controlling a source to drain current. The switching device further includes a source electrode interposed into the insulated gate electrode for substantially preventing a coupling of an electrical field between the gate electrode and an epitaxial region underneath the insulated gate electrode. The source electrode further covers and extends over the insulated gate for covering an area on the second surface of the semiconductor to contact the source region. The semiconductor substrate further includes an epitaxial layer disposed above and having a different dopant concentration than the drain region. The insulated gate electrode further includes an insulation layer for insulating the gate electrode from the source electrode wherein the insulation layer having a thickness depending on a Vgsmax rating of the vertical power device.
摘要翻译：本发明公开了一种支撑在半导体上的新开关装置，其包括设置在第一表面上的漏极和设置在与第一表面相对的所述半导体的第二表面附近的源极区域。开关装置还包括设置在第二表面顶部的用于控制源极到漏极电流的绝缘栅电极。开关装置还包括插入到绝缘栅电极中的源电极，用于基本上防止栅电极和绝缘栅电极下方的外延区之间的电场的耦合。源电极进一步覆盖并延伸在绝缘栅上，以覆盖半导体的第二表面上的区域以接触源区。半导体衬底还包括设置在漏极区以上且具有与漏极区不同的掺杂浓度的外延层。绝缘栅电极还包括用于使栅电极与源电极绝缘的绝缘层，其中绝缘层的厚度取决于垂直功率器件的Vgsmax等级。

14. 发明授权

US08597998B2 Power MOS device fabrication 有权
标题翻译：功率MOS器件制造
公开(公告)号：US08597998B2
公开(公告)日：2013-12-03
申请号：US13604286
申请日：2012-09-05
申请人： Anup Bhalla , Sik K. Lui , Tiesheng Li
发明人： Anup Bhalla , Sik K. Lui , Tiesheng Li
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/4236 , H01L29/456 , H01L29/47 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811
摘要： Fabricating a semiconductor device includes forming a mask on a substrate having a top substrate surface; forming a gate trench in the substrate, through the mask; depositing gate material in the gate trench; removing the mask to leave a gate structure; implanting a body region; implanting a source region; forming a source body contact trench having a trench wall and a trench bottom; forming a plug in the source body contact trench, wherein the plug extends below a bottom of the body region; and disposing conductive material in the source body contact trench, on top of the plug.
摘要翻译：制造半导体器件包括在具有顶部衬底表面的衬底上形成掩模; 通过掩模在衬底中形成栅极沟槽; 在栅极沟槽中沉积栅极材料; 取下面罩离开门结构; 植入人体区域; 植入源区; 形成具有沟槽壁和沟槽底部的源体接触沟槽; 在源体接触沟槽中形成插塞，其中插头延伸到身体区域的底部下方; 并且在所述源体接触沟槽中，在所述插头的顶部上设置导电材料。

15. 发明授权

US08288229B2 Power MOS device fabrication 有权
标题翻译：功率MOS器件制造
公开(公告)号：US08288229B2
公开(公告)日：2012-10-16
申请号：US13043721
申请日：2011-03-09
申请人： Anup Bhalla , Sik K. Lui , Tiesheng Li
发明人： Anup Bhalla , Sik K. Lui , Tiesheng Li
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/4236 , H01L29/456 , H01L29/47 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811
摘要： Fabricating a semiconductor device includes forming a hard mask on the substrate having a top substrate surface; forming a gate trench in the substrate, through the hard mask; depositing gate material in the gate trench; removing the hard mask to leave a gate structure; implanting a body region; implanting a source region; forming a source body contact trench having a trench wall and a trench bottom; and disposing an anti-punch through implant along at least a section of the trench wall but not along the trench bottom.
摘要翻译：制造半导体器件包括在具有顶部衬底表面的衬底上形成硬掩模; 通过硬掩模在衬底中形成栅极沟槽; 在栅极沟槽中沉积栅极材料; 去除硬掩模离开门结构; 植入人体区域; 植入源区; 形成具有沟槽壁和沟槽底部的源体接触沟槽; 以及沿着所述沟槽壁的至少一部分而不是沿着所述沟槽底部布置抗穿孔植入物。

16. 发明授权

US08169062B2 Integrated circuit package for semiconductior devices with improved electric resistance and inductance 有权
标题翻译：具有改善电阻和电感的半导体器件的集成电路封装
公开(公告)号：US08169062B2
公开(公告)日：2012-05-01
申请号：US13114063
申请日：2011-05-24
申请人： Leeshawn Luo , Anup Bhalla , Yueh-Se Ho , Sik K. Lui , Mike Chang
发明人： Leeshawn Luo , Anup Bhalla , Yueh-Se Ho , Sik K. Lui , Mike Chang
IPC分类号： H01L23/495 , H01L23/48 , H01L29/40 , H01L23/52
CPC分类号： H01L23/4952 , H01L23/49562 , H01L23/49575 , H01L23/50 , H01L24/05 , H01L24/06 , H01L24/48 , H01L24/49 , H01L24/85 , H01L2224/04042 , H01L2224/05599 , H01L2224/05647 , H01L2224/0603 , H01L2224/48137 , H01L2224/48247 , H01L2224/48465 , H01L2224/4903 , H01L2224/49051 , H01L2224/49111 , H01L2224/49171 , H01L2224/49431 , H01L2224/85447 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/01082 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30107 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor integrated circuit package having a leadframe (108) that includes a leadframe pad (103a) disposed under a die (100) and a bonding metal area (101a) that is disposed over at least two adjacent sides of the die. The increase in the bonding metal area (101a) increases the number of interconnections between the metal area (101a) and the die (100) to reduce the electric resistance and inductance. Furthermore, the surface area of the external terminals radiating from the package's plastic body (106) is increased if not maximized so that heat can be dissipated quicker and external terminal resistances reduced. The integrated circuit is applicable for MOSFET devices and the bonding metal area (101a) is used for the source terminal (101). The bonding metal area may have a “L” shape, a “C” shape, a “J” shape, an “I” shape or any combination thereof.
摘要翻译：一种半导体集成电路封装，具有引线框架（108），该引线框架（108）包括设置在管芯（100）下方的引线框架（103a）和设置在管芯的至少两个相邻侧面上的接合金属区域（101a）。接合金属区域（101a）的增加增加了金属区域（101a）和模具（100）之间的互连次数，以降低电阻和电感。此外，从封装的塑料体（106）辐射的外部端子的表面积如果没有最大化则增加，使得能够更快地消散热量并且降低外部端子电阻。集成电路适用于MOSFET器件，并且用于源极端子（101）的接合金属区域（101a）。接合金属区域可以具有“L”形，“C”形，“J”形，“I”形或其任何组合。

17. 发明授权

US08163618B2 Power MOSFET device structure for high frequency applications 有权
标题翻译：功率MOSFET器件结构用于高频应用
公开(公告)号：US08163618B2
公开(公告)日：2012-04-24
申请号：US12658450
申请日：2010-02-09
申请人： Anup Bhalla , Daniel Ng , Tiesheng Li , Sik K. Lui
发明人： Anup Bhalla , Daniel Ng , Tiesheng Li , Sik K. Lui
IPC分类号： H01L21/336
CPC分类号： H01L29/66712 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/41775 , H01L29/42368 , H01L29/42372 , H01L29/42376 , H01L29/66719 , H01L29/66727 , H01L29/7802 , H01L29/7811 , H01L29/7827
摘要： This invention discloses a new switching device supported on a semiconductor that includes a drain disposed on a first surface and a source region disposed near a second surface of said semiconductor opposite the first surface. The switching device further includes an insulated gate electrode disposed on top of the second surface for controlling a source to drain current. The switching device further includes a source electrode interposed into the insulated gate electrode for substantially preventing a coupling of an electrical field between the gate electrode and an epitaxial region underneath the insulated gate electrode. The source electrode further covers and extends over the insulated gate for covering an area on the second surface of the semiconductor to contact the source region. The semiconductor substrate further includes an epitaxial layer disposed above and having a different dopant concentration than the drain region. The insulated gate electrode further includes an insulation layer for insulating the gate electrode from the source electrode wherein the insulation layer having a thickness depending on a Vgsmax rating of the vertical power device.
摘要翻译：本发明公开了一种支撑在半导体上的新开关装置，其包括设置在第一表面上的漏极和设置在与第一表面相对的所述半导体的第二表面附近的源极区域。开关装置还包括设置在第二表面顶部的用于控制源极到漏极电流的绝缘栅电极。开关装置还包括插入到绝缘栅电极中的源电极，用于基本上防止栅电极和绝缘栅电极下方的外延区之间的电场的耦合。源电极进一步覆盖并延伸在绝缘栅上，以覆盖半导体的第二表面上的区域以接触源区。半导体衬底还包括设置在漏极区以上且具有与漏极区不同的掺杂浓度的外延层。绝缘栅电极还包括用于使栅电极与源电极绝缘的绝缘层，其中绝缘层的厚度取决于垂直功率器件的Vgsmax等级。

18. 发明申请

US20110207276A1 POWER MOS DEVICE FABRICATION 有权
标题翻译：电源MOS器件制造
公开(公告)号：US20110207276A1
公开(公告)日：2011-08-25
申请号：US13043721
申请日：2011-03-09
申请人： Anup Bhalla , Sik K. Lui , Tiesheng Li
发明人： Anup Bhalla , Sik K. Lui , Tiesheng Li
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/4236 , H01L29/456 , H01L29/47 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811
摘要： Fabricating a semiconductor device includes forming a hard mask on the substrate having a top substrate surface; forming a gate trench in the substrate, through the hard mask; depositing gate material in the gate trench; removing the hard mask to leave a gate structure; implanting a body region; implanting a source region; forming a source body contact trench having a trench wall and a trench bottom; and disposing an anti-punch through implant along at least a section of the trench wall but not along the trench bottom.
摘要翻译：制造半导体器件包括在具有顶部衬底表面的衬底上形成硬掩模; 通过硬掩模在衬底中形成栅极沟槽; 在栅极沟槽中沉积栅极材料; 去除硬掩模离开门结构; 植入人体区域; 植入源区; 形成具有沟槽壁和沟槽底部的源体接触沟槽; 以及沿着所述沟槽壁的至少一部分而不是沿着所述沟槽底部布置抗穿孔植入物。

19. 发明申请

US20110097885A1 Mosfet using gate work function engineering for switching applications 有权
标题翻译： Mosfet使用门功能工程开关应用
公开(公告)号：US20110097885A1
公开(公告)日：2011-04-28
申请号：US12928987
申请日：2010-12-23
申请人： Anup Bhalla , Sik K. Lui
发明人： Anup Bhalla , Sik K. Lui
IPC分类号： H01L21/28
CPC分类号： H01L29/7813 , H01L29/4916 , H01L29/4983 , H01L29/66734 , H01L29/7811
摘要： This invention discloses a new MOSFET device. The MOSFET device has an improved operation characteristic achieved by manufacturing a MOSFET with a higher gate work function by implementing a P-doped gate in an N-MOSFET device. The P-type gate increases the threshold voltage and shifts the C-Vds characteristics. The reduced Cgd thus achieves the purpose of suppressing the shoot through and resolve the difficulties discussed above. Unlike the conventional techniques, the reduction of the capacitance Cgd is achieved without requiring complicated fabrication processes and control of the recess electrode.
摘要翻译：本发明公开了一种新的MOSFET器件。通过在N-MOSFET器件中实现P掺杂栅极，MOSFET器件具有通过制造具有较高栅极功能功能的MOSFET获得的改进的操作特性。 P型栅极增加阈值电压并移位C-Vds特性。因此，减少的Cgd实现了抑制拍摄的目的，并解决了上述困难。与常规技术不同，实现了电容Cgd的减小，而不需要复杂的制造工艺和凹陷电极的控制。

20. 发明授权

US07863675B2 MOSFET using gate work function engineering for switching applications 有权
标题翻译： MOSFET采用门极功能工程用于开关应用
公开(公告)号：US07863675B2
公开(公告)日：2011-01-04
申请号：US11999167
申请日：2008-03-22
申请人： Anup Bhalla , Sik K. Lui
发明人： Anup Bhalla , Sik K. Lui
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/4916 , H01L29/4983 , H01L29/66734 , H01L29/7811
摘要： This invention discloses a new MOSFET device. The MOSFET device has an improved operation characteristic achieved by manufacturing a MOSFET with a higher gate work function by implementing a P-doped gate in an N-MOSFET device. The P-type gate increases the threshold voltage and shifts the C-Vds characteristics. The reduced Cgd thus achieves the purpose of suppressing the shoot through and resolve the difficulties discussed above. Unlike the conventional techniques, the reduction of the capacitance Cgd is achieved without requiring complicated fabrication processes and control of the recess electrode.
摘要翻译：本发明公开了一种新的MOSFET器件。通过在N-MOSFET器件中实现P掺杂栅极，MOSFET器件具有通过制造具有较高栅极功能功能的MOSFET获得的改进的操作特性。 P型栅极增加阈值电压并移位C-Vds特性。因此，减少的Cgd实现了抑制拍摄的目的，并解决了上述困难。与常规技术不同，实现了电容Cgd的减小，而不需要复杂的制造工艺和凹陷电极的控制。

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