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11. 发明申请

US20130219004A1 COMMUNICATION USING INTEGRATED CIRCUIT INTERCONNECT CIRCUITRY 有权
标题翻译：使用集成电路互连电路的通信
公开(公告)号：US20130219004A1
公开(公告)日：2013-08-22
申请号：US13825190
申请日：2011-10-11
申请人： Timothy Charles Mace , Andrew Christopher Rose
发明人： Timothy Charles Mace , Andrew Christopher Rose
IPC分类号： H04L29/08
CPC分类号： H04L67/10 , G06F15/7825 , G06F15/7842 , H04L12/40084 , H04L12/46 , H04L45/00
摘要： An integrated circuit comprising multiple master units (4, 6) and multiple slave units (10, 12) connected via interconnect circuitry (8) utilises token based node-to-node communication flow management within the interconnect circuitry (8) with a network node requesting a token and receiving a token signal before it asserts its communication signals onto a physical communication link shared between multiple virtual networks.
摘要翻译：包括通过互连电路（8）连接的多个主单元（4,6）和多个从单元（10,12）的集成电路利用网络节点在互连电路（8）内的基于令牌的节点到节点通信流管理在将其通信信号置于多个虚拟网络之间共享的物理通信链路之前，请求令牌并接收令牌信号。

12. 发明申请

US20110191543A1 Area and power efficient data coherency maintenance 有权
标题翻译：区域和功率有效的数据一致性维护
公开(公告)号：US20110191543A1
公开(公告)日：2011-08-04
申请号：US12656538
申请日：2010-02-02
申请人： Simon John Craske , Antony John Penton , Loic Pierron , Andrew Christopher Rose
发明人： Simon John Craske , Antony John Penton , Loic Pierron , Andrew Christopher Rose
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0831 , G06F12/0804 , G06F2212/1024 , Y02D10/13
摘要： An apparatus for storing data that is being processed is disclosed. The apparatus comprises: a cache associated with a processor and for storing a local copy of data items stored in a memory for use by the processor, monitoring circuitry associated with the cache for monitoring write transaction requests to the memory initiated by a further device, the further device being configured not to store data in the cache. The monitoring circuitry is responsive to detecting a write transaction request to write a data item, a local copy of which is stored in the cache, to block a write acknowledge signal transmitted from the memory to the further device indicating the write has completed and to invalidate the stored local copy in the cache and on completion of the invalidation to send the write acknowledge signal to the further device.
摘要翻译：公开了一种用于存储正在处理的数据的装置。该装置包括：与处理器相关联的用于存储在存储器中用于由处理器使用的数据项的本地副本的高速缓存，用于监控与高速缓存相关联的监视电路，用于监视由另一设备发起的存储器的写事务请求，进一步的设备被配置为不将数据存储在高速缓存中。监视电路响应于检测到写入事务请求来写入其本地副本存储在高速缓存中的数据项，以阻止从存储器发送到指示写入已完成的另一设备的写入确认信号，并使其无效存储的本地副本在缓存中并完成无效，以将写入确认信号发送到另一个设备。

13. 发明申请

US20110179255A1 Data processing reset operations 审中-公开
标题翻译：数据处理复位操作
公开(公告)号：US20110179255A1
公开(公告)日：2011-07-21
申请号：US12656246
申请日：2010-01-21
申请人： Chiloda Ashan Senerath Pathirane , Antony John Penton , Andrew Christopher Rose
发明人： Chiloda Ashan Senerath Pathirane , Antony John Penton , Andrew Christopher Rose
IPC分类号： G06F9/38 , G06F9/30 , G06F12/08
CPC分类号： G06F11/0793 , G06F1/24
摘要： A processor 4 is provided with reset circuitry 48 which generates a reset signal to reset a plurality of state parameters. Partial reset circuitry 50 is additionally provided to reset a proper subset of this plurality of state parameters. The reset circuitry triggers a redirection of program flow. The partial reset circuitry permits a continuation of program flow. The partial reset circuitry may be used to place processors into a known state with a low latency before switching from a split mode of operation into a locked mode of operation.
摘要翻译：处理器4设置有复位电路48，其产生复位信号以复位多个状态参数。另外提供部分复位电路50以复位该多个状态参数的正确子集。复位电路触发程序流的重定向。部分复位电路允许继续程序流程。部分复位电路可以用于在从分离操作模式切换到锁定操作模式之前将处理器置于具有低延迟的已知状态。

14. 发明授权

US07802080B2 Null exception handling 有权
标题翻译：空异常处理
公开(公告)号：US07802080B2
公开(公告)日：2010-09-21
申请号：US10807498
申请日：2004-03-24
申请人： David John Butcher , Stephen John Hill , Hedley James Francis , Vladimir Vasekin , Andrew Christopher Rose
发明人： David John Butcher , Stephen John Hill , Hedley James Francis , Vladimir Vasekin , Andrew Christopher Rose
IPC分类号： G06F9/40 , G06F9/44 , G06F9/445
CPC分类号： G06F9/3861 , G06F9/30174 , G06F9/355
摘要： A processor 6 is provided with an instruction decoder 18 which is responsive to memory access instructions to determine whether the base register value being used matches a null value and if such a match occurs then branches to a null value exception handler.
摘要翻译：处理器6设置有指令解码器18，该指令解码器18响应于存储器访问指令来确定正在使用的基本寄存器值是否与空值匹配，并且如果发生这样的匹配，则分支到空值异常处理程序。

15. 发明授权

US07747839B2 Data processing apparatus and method for handling instructions to be executed by processing circuitry 有权
标题翻译：用于处理由处理电路执行的指令的数据处理装置和方法
公开(公告)号：US07747839B2
公开(公告)日：2010-06-29
申请号：US12010305
申请日：2008-01-23
申请人： Peter Richard Greenhalgh , Andrew Christopher Rose
发明人： Peter Richard Greenhalgh , Andrew Christopher Rose
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/30145 , G06F9/30149 , G06F9/30189 , G06F9/3816 , G06F9/382 , G06F9/3861
摘要： A data processing apparatus and method are provided for handling instructions to be executed by processing circuitry. The processing circuitry has a plurality of processor states, each processor state having a different instruction set associated therewith. Pre-decoding circuitry receives the instructions fetched from the memory and performs a pre-decoding operation to generate corresponding pre-decoded instructions, with those pre-decoded instructions then being stored in a cache for access by the processing circuitry. The pre-decoding circuitry performs the pre-decoding operation assuming a speculative processor state, and the cache is arranged to store an indication of the speculative processor state in association with the pre-decoded instructions. The processing circuitry is then arranged only to execute an instruction in the sequence using the corresponding pre-decoded instruction from the cache if a current processor state of the processing circuitry matches the indication of the speculative processor state stored in the cache for that instruction. This provides a simple and effective mechanism for detecting instructions that have been corrupted by the pre-decoding operation due to an incorrect assumption of processor state.
摘要翻译：提供了一种用于处理由处理电路执行的指令的数据处理装置和方法。处理电路具有多个处理器状态，每个处理器状态具有与其相关联的不同指令集。预解码电路接收从存储器取出的指令，并执行预解码操作以产生相应的预解码指令，然后将那些预先解码的指令存储在高速缓存中以供处理电路访问。预解码电路在假设处理器状态下执行预解码操作，并且高速缓存被配置为存储与预解码指令相关联的推测性处理器状态的指示。如果处理电路的当前处理器状态与存储在该指令的高速缓存中的推测性处理器状态的指示相匹配，则处理电路然后被布置为仅使用来自高速缓存的相应的预解码指令来执行序列中的指令。这提供了一种用于检测由于处理器状态的不正确假设而被预解码操作损坏的指令的简单而有效的机制。

16. 发明授权

US07509502B2 Data processing apparatus and method for merging secure and non-secure data into an output data stream 有权
标题翻译：用于将安全和非安全数据合并到输出数据流中的数据处理装置和方法
公开(公告)号：US07509502B2
公开(公告)日：2009-03-24
申请号：US10931210
申请日：2004-09-01
申请人： Hedley James Francis , Ashley Miles Stevens , Andrew Christopher Rose
发明人： Hedley James Francis , Ashley Miles Stevens , Andrew Christopher Rose
IPC分类号： G06F12/14 , G06F13/14
CPC分类号： G06F21/72 , G06F21/10 , G06F21/84 , G06F2221/0797 , G06F2221/2105
摘要： The present invention provides a data processing apparatus and method for merging secure and non-secure data. The apparatus comprises at least one processor operable to execute a non-secure process to produce non-secure data to be included in an output data stream, and to execute a secure process to produce secure data to be included in the output data stream. A non-secure buffer is provided for receiving the non-secure data produced by the non-secure process, and in addition a secure buffer is provided for receiving the secure data produced by the secure process, the secure buffer not being accessible by the non-secure process. An output controller is then arranged to read the non-secure data from the non-secure buffer and the secure data from the secure buffer, and to merge the non-secure data and the secure data in order to produce a combined data stream, the output data stream then being derivable from the combined data stream. It has been found that such an approach assists in improving the security of the secure data, and in reducing memory bandwidth requirements and the processing requirements of the processor.
摘要翻译：本发明提供一种用于合并安全和非安全数据的数据处理装置和方法。该装置包括至少一个处理器，可操作以执行非安全过程以产生要包括在输出数据流中的非安全数据，以及执行安全处理以产生要包括在输出数据流中的安全数据。提供了一种非安全缓冲器，用于接收由非安全过程产生的非安全数据，另外还提供了一个安全缓冲器，用于接收由安全过程生成的安全数据，安全缓冲区不能被非安全性访问，安全程序。然后，输出控制器被安排为从非安全缓冲器读取非安全数据和来自安全缓冲器的安全数据，并且合并非安全数据和安全数据以产生组合数据流，输出数据流然后可从组合数据流导出。已经发现，这种方法有助于提高安全数据的安全性，并且在减少存储器带宽要求和处理器的处理要求方面有所帮助。

17. 发明授权

US08347067B2 Instruction pre-decoding of multiple instruction sets 有权
公开(公告)号：US08347067B2
公开(公告)日：2013-01-01
申请号：US12010312
申请日：2008-01-23
申请人： Peter Richard Greenhalgh , Andrew Christopher Rose , Simon John Craske
发明人： Peter Richard Greenhalgh , Andrew Christopher Rose , Simon John Craske
IPC分类号： G06F9/30
CPC分类号： G06F9/30174 , G06F9/30145 , G06F9/30167 , G06F9/3802 , G06F9/3814 , G06F9/382 , G06F9/3853 , G06F9/3865
摘要： A data processing apparatus is provided with pre-decoding circuitry 10 serving to generate pre-decoded instructions which are stored within an instruction cache 20. The pre-decoded instructions from the instruction cache 20 are read by decoding circuitry 45, 50, 46 and used to form control signals for controlling processing operations corresponding to the pre-decoded instructions. The program instructions originally fetched can belong to respective ones of a plurality of instruction sets. Instructions from one instruction set are pre-decoded by the pre-decoding circuitry 10 into pre-decoded instructions having a shared format to represent shared functionality with corresponding instructions taken from another of the instruction sets. In this way, a shared portion of the decoding circuitry can generate control signals with respect to the shared functionality of instructions from both of these different instruction sets.

18. 发明授权

US08219379B2 System, method and computer program product for testing software 有权
标题翻译：用于测试软件的系统，方法和计算机程序产品
公开(公告)号：US08219379B2
公开(公告)日：2012-07-10
申请号：US10998178
申请日：2004-11-29
申请人： Andrew Christopher Rose , Andrew James Bolt , Donald Robert Sinclair
发明人： Andrew Christopher Rose , Andrew James Bolt , Donald Robert Sinclair
IPC分类号： G06F9/45 , G06F13/00 , G06F9/46 , G06F9/455
CPC分类号： G06F11/3672
摘要： Software is tested for execution on data processing apparatus with plural processors that share access to a memory. The memory has a memory ordering type specifying an ordering freedom which allows memory access requests to be processed out of order from an original program order. A simulator for each processor executes a sequence of instructions in program order. An access buffer associated with one of the processor simulators receives and stores access requests issued by that simulator when executing access instructions within the sequences. A controller selects and applies an eviction policy to determine an order in which access requests are output from the access buffer to the memory so that the ordering freedom is exercised in a manner compliant with the memory ordering type but to a degree exceeding that expected within the data processing apparatus.
摘要翻译：在具有共享对存储器的访问的多个处理器的数据处理装置上测试软件的执行。存储器具有指定排序自由度的存储器排序类型，其允许从原始程序顺序处理不规则的存储器访问请求。每个处理器的模拟器以程序顺序执行一系列指令。与处理器模拟器之一相关联的访问缓冲器在执行序列内的访问指令时接收并存储由该模拟器发出的访问请求。控制器选择并应用驱逐策略来确定访问请求从访问缓冲器输出到存储器的顺序，使得以符合存储器排序类型的方式行使排序自由度，但是超过了在数据处理装置。

19. 发明授权

US07647480B2 Handling of conditional instructions in a data processing apparatus 有权
标题翻译：在数据处理设备中处理条件指令
公开(公告)号：US07647480B2
公开(公告)日：2010-01-12
申请号：US11632698
申请日：2004-07-27
申请人： Simon Andrew Ford , Andrew Christopher Rose
发明人： Simon Andrew Ford , Andrew Christopher Rose
IPC分类号： G06F9/38
CPC分类号： G06F9/30072 , G06F9/3001 , G06F9/30163
摘要： A data processing apparatus and method of handling conditional instructions in such a data processing apparatus are provided. The data processing apparatus has a pipelined processing unit for executing instructions including at least one conditional instruction from a set of conditional instructions, and a register file having a plurality of registers operable to store data values for access by the pipelined processing unit when executing the instructions. A register specified by an instruction may be either a source register holding a source data value for that instruction or a destination register into which is stored a result data value generated by execution of that instruction. The register file has a predetermined number of read ports via which data values can be read from registers of the register file. The pipelined processing unit is operable when executing the at least one conditional instruction to produce a result data value which, dependent on the existence of the condition specified by that conditional instruction, represents either the result of the computation specified by that conditional instruction or a current data value stored in the destination register for that conditional instruction. Further, each conditional instruction in the set is constrained to specify a register that is both a source register and a destination register for that conditional instruction, thereby reducing the minimum number of read ports required to support execution of that conditional instruction by the pipelined processing unit.
摘要翻译：提供了一种在这种数据处理装置中处理条件指令的数据处理装置和方法。数据处理装置具有流水线处理单元，用于执行包括来自一组条件指令的至少一个条件指令的指令，以及具有多个寄存器的寄存器文件，该多个寄存器可操作以在执行指令时存储由流水线处理单元进行访问的数据值。由指令指定的寄存器可以是保存该指令的源数据值的源寄存器或存储通过执行该指令而生成的结果数据值的目标寄存器。寄存器文件具有预定数量的读取端口，经由该读取端口可以从寄存器文件的寄存器读取数据值。流水线处理单元在执行至少一个条件指令以产生结果数据值时可操作，该结果数据值取决于由该条件指令指定的条件的存在表示由该条件指令指定的计算结果或当前值存储在该条件指令的目标寄存器中的数据值。此外，集合中的每个条件指令被限制为指定用于该条件指令的源寄存器和目的地寄存器的寄存器，由此减少支持由流水线处理单元执行该条件指令所需的读端口的最小数量。

20. 发明申请

US20090187741A1 Data processing apparatus and method for handling instructions to be executed by processing circuitry 有权
公开(公告)号：US20090187741A1
公开(公告)日：2009-07-23
申请号：US12010305
申请日：2008-01-23
申请人： Peter Richard Greenhalgh , Andrew Christopher Rose
发明人： Peter Richard Greenhalgh , Andrew Christopher Rose
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/30145 , G06F9/30149 , G06F9/30189 , G06F9/3816 , G06F9/382 , G06F9/3861
摘要： A data processing apparatus and method are provided for handling instructions to be executed by processing circuitry. The processing circuitry has a plurality of processor states, each processor state having a different instruction set associated therewith. Pre-decoding circuitry receives the instructions fetched from the memory and performs a pre-decoding operation to generate corresponding pre-decoded instructions, with those pre-decoded instructions then being stored in a cache for access by the processing circuitry. The pre-decoding circuitry performs the pre-decoding operation assuming a speculative processor state, and the cache is arranged to store an indication of the speculative processor state in association with the pre-decoded instructions. The processing circuitry is then arranged only to execute an instruction in the sequence using the corresponding pre-decoded instruction from the cache if a current processor state of the processing circuitry matches the indication of the speculative processor state stored in the cache for that instruction. This provides a simple and effective mechanism for detecting instructions that have been corrupted by the pre-decoding operation due to an incorrect assumption of processor state.

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