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11. 发明申请

US20050156281A1 HIGH TOLERANCE TCR BALANCED HIGH CURRENT RESISTOR FOR RF CMOS AND RF SiGe BiCMOS APPLICATIONS AND CADENCED BASED HIERARCHICAL PARAMETERIZED CELL DESIGN KIT WITH TUNABLE TCR AND ESD RESISTOR BALLASTING FEATURE 失效
标题翻译：用于RF CMOS和RF SiGe BiCMOS应用的高耐压TCR平衡型高电流电阻器和基于CAD的分层式参数化电池设计套件，具有TUNABLE TCR和ESD电阻贴片特性
公开(公告)号：US20050156281A1
公开(公告)日：2005-07-21
申请号：US10707863
申请日：2004-01-19
申请人： Ebenezer Eshun , Steven Voldman
发明人： Ebenezer Eshun , Steven Voldman
IPC分类号： H01C7/06 , H01L21/02 , H01L21/20 , H01L23/62 , H01L27/02 , H01L27/08 , H01L29/00
CPC分类号： H01C7/06 , H01L27/0288 , H01L27/0802 , H01L28/24 , H01L2924/0002 , H01L2924/00
摘要： A resistor device structure and method of manufacture therefore, wherein the resistor device structure invention includes a plurality of alternating conductive film and insulative film layers, at least two of the conductive film layers being electrically connected in parallel to provide for high current flow through the resistor device at high frequencies with increased temperature and mechanical stability. The alternating conductive film and insulative film layers may be of a planar or non-planar geometric spatial orientation. The alternating conductive film and insulative film layers may include lateral and vertical portions designed to enable a uniform current density flow within the structure itself through a self-ballasting effect within the physical resistor. A computer aided design tool with graphical and schematic features is provided to enable generation of hierarchical parameterized cells for a resistor element with the ability to provide customization, personalization and tunability of TCR, TCR matching, and high current and ESD robustness.
摘要翻译：因此，电阻器件结构及其制造方法，其中电阻器件结构发明包括多个交替导电膜和绝缘膜层，至少两个导电膜层并联电连接以提供通过电阻器的高电流器件在高频下具有升高的温度和机械稳定性。交替导电膜和绝缘膜层可以是平面或非平面的几何空间取向。交替导电膜和绝缘膜层可以包括横向和垂直部分，其被设计成能够通过物理电阻器内的自镇流效应在结构本身内实现均匀的电流密度流动。提供了具有图形和原理图功能的计算机辅助设计工具，以便能够为电阻元件生成分层参数化单元，具有提供TCR，TCR匹配以及高电流和ESD鲁棒性的定制，个性化和可调性的能力。

12. 发明申请

US20050122204A1 APPARATUS AND METHOD FOR ELECTRONIC FUSE WITH IMPROVED ESD TOLERANCE 有权
公开(公告)号：US20050122204A1
公开(公告)日：2005-06-09
申请号：US10707283
申请日：2003-12-03
申请人： Steven Voldman
发明人： Steven Voldman
IPC分类号： H01H85/046 , H01H85/048 , H01L23/525 , H01H85/04
CPC分类号： H01H85/046 , H01H85/048 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Tolerance to ESD is increased in an electronic fuse by providing at least one non-conductive region adjacent to a conductive region on the surface of an insulator. Such an arrangement reduces the thermal stresses imposed on the insulator in high current applications. Where multiple conductive and adjacent non-conductive regions are disposed on an insulator, the fuse can fail in discrete steps, thus providing a well defined and easily detected transisition to a blown state, as well as providing a stepwise increase in resistance between prescribed resistance values.

13. 发明申请

US20070029646A1 INTER-CHIP ESD PROTECTION STRUCTURE FOR HIGH SPEED AND HIGH FREQUENCY DEVICES 有权
标题翻译：用于高速和高频器件的片间ESD保护结构
公开(公告)号：US20070029646A1
公开(公告)日：2007-02-08
申请号：US11161414
申请日：2005-08-02
申请人： Steven Voldman
发明人： Steven Voldman
IPC分类号： H01L39/00
CPC分类号： H01L23/60 , H01L25/0657 , H01L2224/05001 , H01L2224/05009 , H01L2224/0508 , H01L2224/051 , H01L2224/05568 , H01L2224/05571 , H01L2224/056 , H01L2224/16 , H01L2225/06513 , H01L2225/06531 , H01L2924/12044 , H01L2924/3011 , H01L2924/00014
摘要： The present invention relates to inter-chip electrostatic discharge (ESD) protection structures for high speed, and high frequency devices that contain one or more direct, inter-chip signal transmission paths. Specifically, the present invention relates to a structure that contains: (1) a first chip including a first circuit, (2) a second chip including a second circuit, (3) an intermediate insulator layer located between the first and second chips, wherein the first and second circuits form a signal transmission path for transmitting signals through the intermediate insulator layer. An electrostatic discharge (ESD) protection path is provided in the structure between the first and the second chip through the intermediate insulator layer, to protect the signal transmission path from ESD damages.
摘要翻译：本发明涉及用于高速的片上静电放电（ESD）保护结构以及包含一个或多个直接的芯片间信号传输路径的高频器件。具体而言，本发明涉及一种结构，其包括：（1）包括第一电路的第一芯片，（2）包括第二电路的第二芯片，（3）位于第一和第二芯片之间的中间绝缘体层，其中第一和第二电路形成用于通过中间绝缘体层传输信号的信号传输路径。通过中间绝缘层在第一和第二芯片之间的结构中提供静电放电（ESD）保护路径，以保护信号传输路径免受ESD损害。

14. 发明申请

US20070013072A1 METHOD AND STRUCTURE FOR CHARGE DISSIPATION DURING FABRICATION OF INTEGRATED CIRCUITS AND ISOLATION THEREOF 有权
标题翻译：集成电路制造过程中充电放电的方法与结构及其分离
公开(公告)号：US20070013072A1
公开(公告)日：2007-01-18
申请号：US11160468
申请日：2005-06-24
申请人： John Ellis-Monaghan , Jeffrey Gambino , Timothy Sullivan , Steven Voldman
发明人： John Ellis-Monaghan , Jeffrey Gambino , Timothy Sullivan , Steven Voldman
IPC分类号： H01L23/52
CPC分类号： H01L27/0248 , Y10S438/926
摘要： A method, structure and design method for dissipating charge during fabrication of an integrated circuit. The structure includes: a substrate contact in a substrate; one or more wiring levels over the substrate; one or more electrically conductive charge dissipation structures extending from a top surface of an uppermost wiring level of the one or more wiring levels through each lower wiring level of the one or more wiring levels to and in electrical contact with the substrate contact; and circuit structures in the substrate and in the one or more wiring layers, the charge dissipation structures not electrically contacting any the circuit structures in any of the one or more wiring levels, the one or more charge dissipation structures dispersed between the circuit structures.
摘要翻译：一种用于在集成电路制造期间耗散电荷的方法，结构和设计方法。该结构包括：衬底中的衬底接触; 衬底上的一个或多个布线层; 一个或多个导电电荷耗散结构，其从所述一个或多个布线层的最上层布线层的顶表面延伸通过所述一个或多个布线层的每个下布线层与所述基板接触电接触; 以及在基板中和在一个或多个布线层中的电路结构，电荷耗散结构在电路结构之间分散的一个或多个电荷耗散结构不会电接触任何一个或多个布线层中的任何一个电路结构。

15. 发明申请

US20070004160A1 TUNABLE SEMICONDUCTOR DIODES 失效
标题翻译：可控半导体二极管
公开(公告)号：US20070004160A1
公开(公告)日：2007-01-04
申请号：US11469582
申请日：2006-09-01
申请人： Steven Voldman
发明人： Steven Voldman
IPC分类号： H01L21/331
CPC分类号： H01L29/66136 , H01L27/0255 , H01L29/8611 , H01L29/8618 , H01L2924/0002 , H01L2924/00
摘要： A diode structure fabrication method. In a P− substrate, an N+ layer is implanted. The N+ layer has an opening whose size affects the breakdown voltage of the diode structure. Upon the N+ layer, an N− layer is formed. Then, a P+ region is formed to serve as an anode of the diode structure. An N+ region can be formed on the surface of the substrate to serve as a cathode of the diode structure. By changing the size of the opening in the N+ layer during fabrication, the breakdown voltage of the diode structure can be changed (tuned) to a desired value.
摘要翻译：二极管结构制造方法。在P-衬底中，植入N +层。 N +层的开口尺寸影响二极管结构的击穿电压。在N +层上形成N-层。然后，形成P +区域作为二极管结构的阳极。可以在衬底的表面上形成N +区以用作二极管结构的阴极。通过在制造期间改变N +层中的开口的尺寸，可以将二极管结构的击穿电压改变（调谐）至期望的值。

16. 发明申请

US20060048080A1 METHODOLOGY OF QUANTIFICATION OF TRANSMISSION PROBABILITY FOR MINORITY CARRIER COLLECTION IN A SEMICONDUCTOR CHIP 失效
标题翻译：半导体芯片中少数载体收集传输概率的定量方法
公开(公告)号：US20060048080A1
公开(公告)日：2006-03-02
申请号：US10711143
申请日：2004-08-27
申请人： Anne Watson , Steven Voldman
发明人： Anne Watson , Steven Voldman
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method for computer aided design of semiconductor chips which minimizes sensitivity to latchup is provided. The method evaluates electron transmission, reflection and absorption at geometric shapes that represent components of the semiconductor.
摘要翻译：提供一种半导体芯片的计算机辅助设计方法，其最小化对闭锁的灵敏度。该方法评估了表示半导体元件的几何形状的电子透射，反射和吸收。

17. 发明申请

US20050218921A1 METHOD AND APPLICATION OF PICA (PICOSECOND IMAGING CIRCUIT ANALYSIS) FOR HIGH CURRENT PULSED PHENOMENA 失效
标题翻译： PICA（PICOSECOND成像电路分析）用于高电流脉冲激光源的方法与应用
公开(公告)号：US20050218921A1
公开(公告)日：2005-10-06
申请号：US10814962
申请日：2004-03-31
申请人： Naoko Sanda , Steven Voldman , Alan Weger
发明人： Naoko Sanda , Steven Voldman , Alan Weger
IPC分类号： G01R31/00 , G01R31/28 , G01R31/308 , G01R31/311 , G06F17/50 , H01L21/66 , G01R31/26
CPC分类号： G01R31/308
摘要： A method, system and apparatus are provided for operating a Picosecond Imaging Circuit Analysis (PICA)/high current source system include applying pulses from a high current pulse source to a Device Under Test (DUT). A photosensor detects photon emissions from the DUT. Signals from the photosensor are used to map photon emissions from the DUT. Data processing means relate the photon emissions to specific features of the DUT.
摘要翻译：提供了一种用于操作Picosecond成像电路分析（PICA）/高电流源系统的方法，系统和装置，包括将来自高电流脉冲源的脉冲施加到被测设备（DUT）。光电传感器检测来自DUT的光子发射。来自光电传感器的信号用于映射DUT的光子发射。数据处理手段将光子发射与DUT的特定特征相关联。

18. 发明申请

US20050161743A1 ELECTROSTATIC DISCHARGE INPUT AND POWER CLAMP CIRCUIT FOR HIGH CUTOFF FREQUENCY TECHNOLOGY RADIO FREQUENCY (RF) APPLICATIONS 失效
标题翻译：用于高切割频率技术的静电放电输入和电源钳位电路无线电频率（RF）应用
公开(公告)号：US20050161743A1
公开(公告)日：2005-07-28
申请号：US10707954
申请日：2004-01-28
申请人： Steven Voldman
发明人： Steven Voldman
IPC分类号： H01L27/02 , H01L29/06 , H01L29/737 , H01L21/331 , H01L23/62
CPC分类号： H01L27/0259 , H01L29/0657 , H01L29/7378 , H01L2924/0002 , H01L2924/00
摘要： A SiGe ESD (electrostatic discharge) power clamp circuit having a forward biased trigger device fabricated in a given technology and a clamp transistor preferably comprising a high frequency cutoff SiGe npn transistor, wherein the trigger device has a turn-on voltage which is below the Johnson Limit breakdown voltage of the highest frequency device fabricated in the given technology.
摘要翻译：具有以给定技术制造的正向偏置触发器件和优选地包括高频截止SiGe npn晶体管的钳位晶体管的SiGe ESD（静电放电）功率钳位电路，其中所述触发器件具有低于Johnson的导通电压限制在给定技术中制造的最高频率器件的击穿电压。

19. 发明申请

US20050121741A1 Apparatus and method for electronic fuse with improved ESD tolerance 有权
标题翻译：具有改善ESD耐受性的电子熔断器的装置和方法
公开(公告)号：US20050121741A1
公开(公告)日：2005-06-09
申请号：US11004846
申请日：2004-12-07
申请人： Steven Voldman
发明人： Steven Voldman
IPC分类号： H01L21/44 , H01L21/82 , H01L23/525 , H01L27/02 , H01L29/00
CPC分类号： H01L23/5256 , H01L27/0248 , H01L2924/0002 , Y10T29/49107 , Y10T29/49117 , Y10T29/49124 , Y10T29/49128 , Y10T29/49155 , H01L2924/00
摘要： Tolerance to ESD is increased in an electronic fuse by providing at least one non-conductive region adjacent to a conductive region on the surface of an insulator. Such an arrangement reduces the thermal stresses imposed on the insulator in high current applications. Where multiple conductive and adjacent non-conductive regions are disposed on an insulator, the fuse can fail in discrete steps, thus providing a well defined and easily detected transisition to a blown state, as well as providing a stepwise increase in resistance between prescribed resistance values.
摘要翻译：通过在绝缘体的表面上提供与导电区域相邻的至少一个非导电区域，在电子熔断器中增加对ESD的耐受性。这种布置降低了在大电流应用中施加在绝缘体上的热应力。在多个导电和相邻的非导电区域设置在绝缘体上的情况下，保险丝可以在离散的步骤中失效，从而提供良好限定且易于检测到的吹扫状态的接收，以及提供规定电阻值之间的电阻的逐步增加。

20. 发明授权

US07705426B2 Integration of a SiGe- or SiGeC-based HBT with a SiGe- or SiGeC-strapped semiconductor device 有权
标题翻译：基于SiGe或SiGeC的HBT与SiGe或SiGeC带状半导体器件的集成
公开(公告)号：US07705426B2
公开(公告)日：2010-04-27
申请号：US11558480
申请日：2006-11-10
申请人： Steven Voldman
发明人： Steven Voldman
IPC分类号： H01L29/10 , H01L29/737
CPC分类号： H01L27/0635 , H01L21/8249 , H01L27/10894 , H01L27/11 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides an integrated semiconductor device that includes a semiconductor substrate, a first device containing a heterojunction bipolar transistor (HBT) located in a first region of the semiconductor substrate, wherein the HBT includes a base region containing a first portion of a SiGe or SiGeC layer, and a second device located in a second region of the semiconductor substrate, wherein the second device includes an interconnect containing a second portion of the SiGe or SiGeC layer. In a specific embodiment of the present invention, the second device is a memory device including a trench capacitor and a field effect transistor (FET) that are electrically connected together by the second portion of the SiGe or SiGeC layer. Alternatively, the second device is a trench-biased PNPN silicon controlled rectifier (SCR). The present invention also provides a novel reversibly programmable device or a novel memory device formed by a novel trench-biased SCR device.
摘要翻译：本发明提供一种集成半导体器件，其包括半导体衬底，含有位于半导体衬底的第一区域中的异质结双极晶体管（HBT）的第一器件，其中HBT包括含有SiGe的第一部分的基极区域或 SiGeC层和位于半导体衬底的第二区域中的第二器件，其中第二器件包括含有SiGe或SiGeC层的第二部分的互连。在本发明的具体实施例中，第二器件是包括通过SiGe或SiGeC层的第二部分电连接在一起的沟槽电容器和场效应晶体管（FET）的存储器件。或者，第二器件是沟槽偏置PNPN可硅可控整流器（SCR）。本发明还提供了一种新颖的可逆编程装置或由新颖的沟槽偏置SCR装置形成的新型存储装置。

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