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11. 发明申请

US20110221510A1 SOI RADIO FREQUENCY SWITCH WITH ENHANCED SIGNAL FIDELITY AND ELECTRICAL ISOLATION 有权
标题翻译：具有增强信号强度和电隔离的SOI无线电频率开关
公开(公告)号：US20110221510A1
公开(公告)日：2011-09-15
申请号：US13116396
申请日：2011-05-26
申请人： Alan B. Botula , Alvin J. Joseph , Edward J. Nowak , Yun Shi , James A. Slinkman
发明人： Alan B. Botula , Alvin J. Joseph , Edward J. Nowak , Yun Shi , James A. Slinkman
IPC分类号： H03K3/01 , H01L21/336 , G06F17/50
CPC分类号： H01L27/1203 , H01L21/743 , H01L21/76224 , H01L21/76251 , H01L21/84
摘要： A doped contact region having an opposite conductivity type as a bottom semiconductor layer is provided underneath a buried insulator layer in a bottom semiconductor layer. At least one conductive via structure extends from an interconnect-level metal line through a middle-of-line (MOL) dielectric layer, a shallow trench isolation structure in a top semiconductor layer, and a buried insulator layer and to the doped contact region. The doped contact region is biased at a voltage that is at or close to a peak voltage in the RF switch that removes minority charge carriers within the induced charge layer. The minority charge carriers are drained through the doped contact region and the at least one conductive via structure. Rapid discharge of mobile electrical charges in the induce charge layer reduces harmonic generation and signal distortion in the RF switch. A design structure for the semiconductor structure is also provided.
摘要翻译：具有与底部半导体层相反的导电类型的掺杂接触区域设置在底部半导体层中的掩埋绝缘体层的下方。至少一个导电通孔结构从互连级金属线延伸穿过中间线（MOL）电介质层，顶部半导体层中的浅沟槽隔离结构，以及掩埋绝缘体层和掺杂接触区域。掺杂接触区域被偏置在处于或接近RF开关中的峰值电压的电压，该电压去除感应电荷层内的少数电荷载流子。少数电荷载体通过掺杂接触区域和至少一个导电通孔结构排出。诱导电荷层中的移动电荷的快速放电减少了RF开关中的谐波产生和信号失真。还提供了用于半导体结构的设计结构。

12. 发明申请

US20100156526A1 SOI RADIO FREQUENCY SWITCH WITH ENHANCED SIGNAL FIDELITY AND ELECTRICAL ISOLATION 有权
标题翻译：具有增强信号强度和电隔离的SOI无线电频率开关
公开(公告)号：US20100156526A1
公开(公告)日：2010-06-24
申请号：US12342527
申请日：2008-12-23
申请人： Alan B. Botula , Alvin J. Joseph , Edward J. Nowak , Yun Shi , James A. Slinkman
发明人： Alan B. Botula , Alvin J. Joseph , Edward J. Nowak , Yun Shi , James A. Slinkman
IPC分类号： H03H11/00 , H01L21/761 , H01L21/762 , H01L27/12
CPC分类号： H01L27/1203 , H01L21/743 , H01L21/76224 , H01L21/76251 , H01L21/84
摘要： A doped contact region having an opposite conductivity type as a bottom semiconductor layer is provided underneath a buried insulator layer in a bottom semiconductor layer. At least one conductive via structure extends from an interconnect-level metal line through a middle-of-line (MOL) dielectric layer, a shallow trench isolation structure in a top semiconductor layer, and a buried insulator layer and to the doped contact region. The doped contact region is biased at a voltage that is at or close to a peak voltage in the RF switch that removes minority charge carriers within the induced charge layer. The minority charge carriers are drained through the doped contact region and the at least one conductive via structure. Rapid discharge of mobile electrical charges in the induce charge layer reduces harmonic generation and signal distortion in the RF switch. A design structure for the semiconductor structure is also provided.
摘要翻译：具有与底部半导体层相反的导电类型的掺杂接触区域设置在底部半导体层中的掩埋绝缘体层的下方。至少一个导电通孔结构从互连级金属线延伸穿过中间线（MOL）电介质层，顶部半导体层中的浅沟槽隔离结构，以及掩埋绝缘体层和掺杂接触区域。掺杂接触区域被偏置在处于或接近RF开关中的峰值电压处的电压，其移除感应电荷层内的少数电荷载流子。少数电荷载体通过掺杂接触区域和至少一个导电通孔结构排出。诱导电荷层中的移动电荷的快速放电减少了RF开关中的谐波产生和信号失真。还提供了用于半导体结构的设计结构。

13. 发明申请

US20090250772A1 FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURE 有权
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US20090250772A1
公开(公告)日：2009-10-08
申请号：US12099175
申请日：2008-04-08
申请人： Alan B. Botula , Alvin J. Joseph , Stephen E. Luce , John J. Pekarik , Yun Shi
发明人： Alan B. Botula , Alvin J. Joseph , Stephen E. Luce , John J. Pekarik , Yun Shi
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7834 , H01L29/0847 , H01L29/41783 , H01L29/423 , H01L29/66575
摘要： A semiconductor structure and method of manufacture and, more particularly, a field effect transistor that has a body contact and method of manufacturing the same is provided. The structure includes a device having a raised source region of a first conductivity type and an active region below the raised source region extending to a body of the device. The active region has a second conductivity type different than the first conductivity type. A contact region is in electric contact with the active region. The method includes forming a raised source region over an active region of a device and forming a contact region of a same conductivity type as the active region, wherein the active region forms a contact body between the contact region and a body of the device.
摘要翻译：提供一种半导体结构和制造方法，更具体地说，具有身体接触的场效应晶体管及其制造方法。该结构包括具有第一导电类型的凸起源极区域和延伸到器件主体的凸起源极区域下方的有源区域的器件。有源区具有不同于第一导电类型的第二导电类型。接触区域与有源区域电接触。该方法包括在器件的有源区上形成凸起的源极区域，并形成与有源区域相同的导电类型的接触区域，其中有源区域在接触区域和器件的主体之间形成接触体。

14. 发明授权

US08916467B2 SOI radio frequency switch with enhanced signal fidelity and electrical isolation 有权
标题翻译：具有增强的信号保真度和电隔离的SOI射频开关
公开(公告)号：US08916467B2
公开(公告)日：2014-12-23
申请号：US13116396
申请日：2011-05-26
申请人： Alan B. Botula , Alvin J. Joseph , Edward J. Nowak , Yun Shi , James A. Slinkman
发明人： Alan B. Botula , Alvin J. Joseph , Edward J. Nowak , Yun Shi , James A. Slinkman
IPC分类号： H03K3/01 , H01L21/336 , G06F17/50 , H01L21/762 , H01L27/12 , H01L21/84
CPC分类号： H01L27/1203 , H01L21/743 , H01L21/76224 , H01L21/76251 , H01L21/84
摘要： A doped contact region having an opposite conductivity type as a bottom semiconductor layer is provided underneath a buried insulator layer in a bottom semiconductor layer. At least one conductive via structure extends from an interconnect-level metal line through a middle-of-line (MOL) dielectric layer, a shallow trench isolation structure in a top semiconductor layer, and a buried insulator layer and to the doped contact region. The doped contact region is biased at a voltage that is at or close to a peak voltage in the RF switch that removes minority charge carriers within the induced charge layer. The minority charge carriers are drained through the doped contact region and the at least one conductive via structure. Rapid discharge of mobile electrical charges in the induce charge layer reduces harmonic generation and signal distortion in the RF switch. A design structure for the semiconductor structure is also provided.
摘要翻译：具有与底部半导体层相反的导电类型的掺杂接触区域设置在底部半导体层中的掩埋绝缘体层的下方。至少一个导电通孔结构从互连级金属线延伸穿过中间线（MOL）电介质层，顶部半导体层中的浅沟槽隔离结构，以及掩埋绝缘体层和掺杂接触区域。掺杂接触区域被偏置在处于或接近RF开关中的峰值电压的电压，该电压去除感应电荷层内的少数电荷载流子。少数电荷载体通过掺杂接触区域和至少一个导电通孔结构排出。诱导电荷层中的移动电荷的快速放电减少了RF开关中的谐波产生和信号失真。还提供了用于半导体结构的设计结构。

15. 发明授权

US08133774B2 SOI radio frequency switch with enhanced electrical isolation 有权
标题翻译： SOI射频开关具有增强的电气隔离
公开(公告)号：US08133774B2
公开(公告)日：2012-03-13
申请号：US12411494
申请日：2009-03-26
申请人： Alan B. Botula , Alvin J. Joseph , Edward J. Nowak , Yun Shi , James A. Slinkman
发明人： Alan B. Botula , Alvin J. Joseph , Edward J. Nowak , Yun Shi , James A. Slinkman
IPC分类号： H01L21/00
CPC分类号： H01L21/84 , H01L21/76264 , H01L27/1203
摘要： At least one conductive via structure is formed from an interconnect-level metal line through a middle-of-line (MOL) dielectric layer, a shallow trench isolation structure in a top semiconductor layer, and a buried insulator layer to a bottom semiconductor layer. The shallow trench isolation structure laterally abuts at least two field effect transistors that function as a radio frequency (RF) switch. The at least one conductive via structure and the at interconnect-level metal line may provide a low resistance electrical path from the induced charge layer in a bottom semiconductor layer to electrical ground, discharging the electrical charge in the induced charge layer. The discharge of the charge in the induced charge layer thus reduces capacitive coupling between the semiconductor devices and the bottom semiconductor layer, and thus secondary coupling between components electrically disconnected by the RF switch is reduced.
摘要翻译：至少一个导电通孔结构由通过中间线（MOL）电介质层的互连级金属线，顶部半导体层中的浅沟槽隔离结构和到半导体层的掩埋绝缘体层形成。浅沟槽隔离结构横向邻接用作射频（RF）开关的至少两个场效应晶体管。所述至少一个导电通孔结构和所述互连级金属线可以提供从底部半导体层中的感应电荷层到电接地的低电阻电路径，从而对感应电荷层中的电荷进行放电。感应电荷层中的电荷的放电因此减小了半导体器件与底部半导体层之间的电容耦合，因此降低了由RF开关电断开的部件之间的二次耦合。

16. 发明授权

US07999320B2 SOI radio frequency switch with enhanced signal fidelity and electrical isolation 有权
标题翻译：具有增强的信号保真度和电隔离的SOI射频开关
公开(公告)号：US07999320B2
公开(公告)日：2011-08-16
申请号：US12342527
申请日：2008-12-23
申请人： Alan B. Botula , Alvin J. Joseph , Edward J. Nowak , Yun Shi , James A. Slinkman
发明人： Alan B. Botula , Alvin J. Joseph , Edward J. Nowak , Yun Shi , James A. Slinkman
IPC分类号： H01L27/01 , H01L27/12
CPC分类号： H01L27/1203 , H01L21/743 , H01L21/76224 , H01L21/76251 , H01L21/84
摘要： A doped contact region having an opposite conductivity type as a bottom semiconductor layer is provided underneath a buried insulator layer in a bottom semiconductor layer. At least one conductive via structure extends from an interconnect-level metal line through a middle-of-line (MOL) dielectric layer, a shallow trench isolation structure in a top semiconductor layer, and a buried insulator layer and to the doped contact region. The doped contact region is biased at a voltage that is at or close to a peak voltage in the RF switch that removes minority charge carriers within the induced charge layer. The minority charge carriers are drained through the doped contact region and the at least one conductive via structure. Rapid discharge of mobile electrical charges in the induce charge layer reduces harmonic generation and signal distortion in the RF switch. A design structure for the semiconductor structure is also provided.
摘要翻译：具有与底部半导体层相反的导电类型的掺杂接触区域设置在底部半导体层中的掩埋绝缘体层的下方。至少一个导电通孔结构从互连级金属线延伸穿过中间线（MOL）电介质层，顶部半导体层中的浅沟槽隔离结构，以及掩埋绝缘体层和掺杂接触区域。掺杂接触区域被偏置在处于或接近RF开关中的峰值电压的电压，该电压去除感应电荷层内的少数电荷载流子。少数电荷载体通过掺杂接触区域和至少一个导电通孔结构排出。诱导电荷层中的移动电荷的快速放电减少了RF开关中的谐波产生和信号失真。还提供了用于半导体结构的设计结构。

17. 发明申请

US20120104496A1 SOI RADIO FREQUENCY SWITCH WITH ENHANCED ELECTRICAL ISOLATION 有权
标题翻译：具有增强电隔离的SOI无线电频率开关
公开(公告)号：US20120104496A1
公开(公告)日：2012-05-03
申请号：US13345871
申请日：2012-01-09
申请人： Alan B. Botula , Alvin J. Joseph , Edward J. Nowak , Yun Shi , James A. Slinkman
发明人： Alan B. Botula , Alvin J. Joseph , Edward J. Nowak , Yun Shi , James A. Slinkman
IPC分类号： H01L27/088 , G06F17/50
CPC分类号： H01L21/84 , H01L21/76264 , H01L27/1203
摘要： At least one conductive via structure is formed from an interconnect-level metal line through a middle-of-line (MOL) dielectric layer, a shallow trench isolation structure in a top semiconductor layer, and a buried insulator layer to a bottom semiconductor layer. The shallow trench isolation structure laterally abuts at least two field effect transistors that function as a radio frequency (RF) switch. The at least one conductive via structure and the at interconnect-level metal line may provide a low resistance electrical path from the induced charge layer in a bottom semiconductor layer to electrical ground, discharging the electrical charge in the induced charge layer. The discharge of the charge in the induced charge layer thus reduces capacitive coupling between the semiconductor devices and the bottom semiconductor layer, and thus secondary coupling between components electrically disconnected by the RF switch is reduced.
摘要翻译：至少一个导电通孔结构由通过中间线（MOL）电介质层的互连级金属线，顶部半导体层中的浅沟槽隔离结构和到半导体层的掩埋绝缘体层形成。浅沟槽隔离结构横向邻接用作射频（RF）开关的至少两个场效应晶体管。所述至少一个导电通孔结构和所述互连级金属线可以提供从底部半导体层中的感应电荷层到电接地的低电阻电路径，从而对感应电荷层中的电荷进行放电。感应电荷层中的电荷的放电因此减小了半导体器件与底部半导体层之间的电容耦合，因此降低了由RF开关电断开的部件之间的二次耦合。

18. 发明申请

US20100244934A1 SOI RADIO FREQUENCY SWITCH WITH ENHANCED ELECTRICAL ISOLATION 有权
标题翻译：具有增强电隔离的SOI无线电频率开关
公开(公告)号：US20100244934A1
公开(公告)日：2010-09-30
申请号：US12411494
申请日：2009-03-26
申请人： Alan B. Botula , Alvin J. Joseph , Edward J. Nowak , Yun Shi , James A. Slinkman
发明人： Alan B. Botula , Alvin J. Joseph , Edward J. Nowak , Yun Shi , James A. Slinkman
IPC分类号： G11C5/14 , H01L29/06 , G06F17/50 , H01L21/762 , H01L21/768
CPC分类号： H01L21/84 , H01L21/76264 , H01L27/1203
摘要： At least one conductive via structure is formed from an interconnect-level metal line through a middle-of-line (MOL) dielectric layer, a shallow trench isolation structure in a top semiconductor layer, and a buried insulator layer to a bottom semiconductor layer. The shallow trench isolation structure laterally abuts at least two field effect transistors that function as a radio frequency (RF) switch. The at least one conductive via structure and the at interconnect-level metal line may provide a low resistance electrical path from the induced charge layer in a bottom semiconductor layer to electrical ground, discharging the electrical charge in the induced charge layer. The discharge of the charge in the induced charge layer thus reduces capacitive coupling between the semiconductor devices and the bottom semiconductor layer, and thus secondary coupling between components electrically disconnected by the RF switch is reduced.
摘要翻译：至少一个导电通孔结构由通过中间线（MOL）电介质层的互连级金属线，顶部半导体层中的浅沟槽隔离结构和到半导体层的掩埋绝缘体层形成。浅沟槽隔离结构横向邻接用作射频（RF）开关的至少两个场效应晶体管。所述至少一个导电通孔结构和所述互连级金属线可以提供从底部半导体层中的感应电荷层到电接地的低电阻电路径，从而对感应电荷层中的电荷进行放电。感应电荷层中的电荷的放电因此减小了半导体器件与底部半导体层之间的电容耦合，因此降低了由RF开关电断开的部件之间的二次耦合。

19. 发明申请

US20120168817A1 LATERAL EXTENDED DRAIN METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (LEDMOSFET) HAVING A HIGH DRAIN-TO-BODY BREAKDOWN VOLTAGE (Vb), A METHOD OF FORMING AN LEDMOSFET, AND A SILICON-CONTROLLED RECTIFIER (SCR) INCORPORATING A COMPLEMENTARY PAIR OF LEDMOSFETS 有权
标题翻译：具有高排水 - 体积断电电压（Vb），形成LEDMOSFET的方法，以及包含LEDMOSFETS的补充对的硅控制整流器（SCR）的侧向延伸漏极金属氧化物半导体场效应晶体管（LEDMOSFET）
公开(公告)号：US20120168817A1
公开(公告)日：2012-07-05
申请号：US13238414
申请日：2011-09-21
申请人： Michel J. Abou-Khalil , Alan B. Botula , Alvin J. Joseph , Theodore J. Letavic , James A. Slinkman
发明人： Michel J. Abou-Khalil , Alan B. Botula , Alvin J. Joseph , Theodore J. Letavic , James A. Slinkman
IPC分类号： H01L27/088 , H01L21/76 , H01L21/336 , H01L29/78
CPC分类号： H01L29/66681 , H01L29/402 , H01L29/407 , H01L29/4238 , H01L29/66704 , H01L29/66795 , H01L29/7436 , H01L29/7824 , H01L29/7825 , H01L29/785
摘要： Disclosed are embodiments of a lateral, extended drain, metal oxide semiconductor, field effect transistor (LEDMOSFET) having a high drain-to-body breakdown voltage. Discrete conductive field (CF) plates are adjacent to opposing sides of the drain drift region, each having an angled sidewall such that the area between the drain drift region and the CF plate has a continuously increasing width along the length of the drain drift region from the channel region to the drain region. The CF plates can comprise polysilicon or metal structures or dopant implant regions within the same semiconductor body as the drain drift region. The areas between the CF plates and the drain drift region can comprise tapered dielectric regions or, alternatively, tapered depletion regions within the same semiconductor body as the drain drift region. Also disclosed are embodiments of a method for forming an LEDMOSFET and embodiments of a silicon-controlled rectifier (SCR) incorporating such LEDMOSFETs.
摘要翻译：公开了具有高漏极对体击穿电压的横向延伸漏极，金属氧化物半导体，场效应晶体管（LEDMOSFET）的实施例。离散导电场（CF）板与漏极漂移区的相对侧相邻，每侧具有成角度的侧壁，使得漏极漂移区和CF板之间的区域沿着漏极漂移区的长度具有连续增加的宽度，沟道区到漏极区。 CF板可以包括与漏极漂移区相同的半导体主体内的多晶硅或金属结构或掺杂剂注入区。 CF板和漏极漂移区域之间的区域可以包括与漏极漂移区域相同的半导体本体内的锥形介质区域或者替代地，锥形耗尽区域。还公开了用于形成LEDMOSFET的方法的实施例和结合了这种LEDMOSFET的可控硅整流器（SCR）的实施例。

20. 发明申请

US20110127529A1 SILICON-ON-INSULATOR (SOI) STRUCTURE CONFIGURED FOR REDUCED HARMONICS AND METHOD OF FORMING THE STRUCTURE 有权
标题翻译：用于减少谐波的硅绝缘体（SOI）结构和形成结构的方法
公开(公告)号：US20110127529A1
公开(公告)日：2011-06-02
申请号：US12627343
申请日：2009-11-30
申请人： Alan B. Botula , John J. Ellis-Monaghan , Alvin J. Joseph , Max G. Levy , Richard A. Phelps , James A. Slinkman , Randy L. Wolf
发明人： Alan B. Botula , John J. Ellis-Monaghan , Alvin J. Joseph , Max G. Levy , Richard A. Phelps , James A. Slinkman , Randy L. Wolf
IPC分类号： H01L27/12 , H01L21/762
CPC分类号： H01L21/02488 , H01L21/2652 , H01L21/7624 , H01L21/84 , H01L27/1203 , H01L29/78603
摘要： Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity due to increased doping with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method for forming such a semiconductor structure.
摘要翻译：公开了在半导体衬底上具有绝缘体层并且器件层位于绝缘体层上的半导体结构。衬底掺杂有相对低剂量的具有给定导电类型的掺杂剂，使得其具有相对高的电阻率。此外，与绝缘体层紧密相邻的半导体衬底的一部分可掺杂略高的相同掺杂剂剂量，具有相同导电类型的不同掺杂剂或其组合。可选地，在该相同部分内形成微腔，以便平衡由于掺杂增加导致的电导率的增加，同时具有相应的电阻率增加。增加半导体衬底 - 绝缘体层界面处的掺杂剂浓度会提高任何结果的寄生电容器的阈值电压（Vt），从而降低谐波行为。本文还公开了用于形成这种半导体结构的方法的实施例。

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