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11. 发明授权

US08916481B2 Embedded wafer level package for 3D and package-on-package applications, and method of manufacture 有权
标题翻译：用于3D和封装封装应用的嵌入式晶圆级封装以及制造方法
公开(公告)号：US08916481B2
公开(公告)日：2014-12-23
申请号：US13312562
申请日：2011-12-06
申请人： Kah Wee Gan , Yaohuang Huang , Yonggang Jin
发明人： Kah Wee Gan , Yaohuang Huang , Yonggang Jin
IPC分类号： H01L21/31 , H01L23/538 , H01L23/00 , H01L23/498 , H01L25/00 , H01L21/48 , H01L25/10 , H05K1/18
CPC分类号： H01L24/97 , H01L21/486 , H01L23/49816 , H01L23/49827 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L24/96 , H01L25/105 , H01L25/50 , H01L2224/0401 , H01L2224/04105 , H01L2224/05569 , H01L2224/05572 , H01L2224/12105 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/97 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2924/00014 , H01L2924/01029 , H01L2924/10253 , H01L2924/12042 , H01L2924/15192 , H01L2924/15311 , H01L2924/15321 , H01L2924/181 , H05K1/186 , H01L2224/03 , H01L2924/014 , H01L2224/81 , H01L2924/00 , H01L2224/05552
摘要： A process for manufacturing a 3D or PoP semiconductor package includes forming a redistribution layer on a reconstituted wafer, then laser drilling a plurality of apertures in the reconstituted wafer, extending from an outer surface of the reconstituted wafer to intersect electrical traces in the first redistribution layer. A solder ball is then positioned adjacent to an opening of each of the apertures. The solder balls are melted and allowed to fill the apertures, making contact with the respective electrical traces and forming a plurality of solder columns. The outer surface of the reconstituted wafer is then planarized, and a second redistribution layer is formed on the planarized surface. The solder columns serve as through-vias, electrically coupling the first and second redistribution layers on opposite sides of the reconstituted wafer.
摘要翻译：一种用于制造3D或PoP半导体封装的工艺包括在再构成的晶片上形成再分配层，然后激光钻出重建的晶片中的多个孔，从再构成的晶片的外表面延伸，以与第一再分配层。然后将焊球定位成与每个孔的开口相邻。焊球熔化并允许填充孔，与相应的电迹线接触并形成多个焊料柱。然后将重构的晶片的外表面平坦化，并且在平坦化表面上形成第二再分布层。焊料柱用作通孔，将重新构成的晶片的相对侧上的第一和第二再分配层电耦合。

12. 发明授权

US08728831B2 Reconstituted wafer warpage adjustment 有权
标题翻译：晶圆翘曲调整
公开(公告)号：US08728831B2
公开(公告)日：2014-05-20
申请号：US12982707
申请日：2010-12-30
申请人： Kah Wee Gan , Yonggang Jin
发明人： Kah Wee Gan , Yonggang Jin
IPC分类号： H01L21/00
CPC分类号： H01L21/67288
摘要： A system and method for reducing warpage of a semiconductor wafer. The system includes a device for securing the semiconductor wafer in a heating area. The device includes a holding mechanism for securing an edge of the semiconductor wafer. The device further includes a pressure reducing device that reduces the pressure underneath the semiconductor device, which further secures the semiconductor device in the heating area. The heating area includes a plurality of heating and cooling zones in which the semiconductor wafer is subjected to various temperatures.
摘要翻译：一种减少半导体晶片翘曲的系统和方法。该系统包括用于将半导体晶片固定在加热区域中的装置。该装置包括用于固定半导体晶片的边缘的保持机构。该装置还包括减压装置，其降低半导体器件下方的压力，这进一步将半导体器件固定在加热区域中。加热区域包括多个加热和冷却区域，其中半导体晶片经受各种温度。

13. 发明申请

US20120282767A1 METHOD FOR PRODUCING A TWO-SIDED FAN-OUT WAFER LEVEL PACKAGE WITH ELECTRICALLY CONDUCTIVE INTERCONNECTS, AND A CORRESPONDING SEMICONDUCTOR PACKAGE 审中-公开
标题翻译：用于制造具有导电互连的两面散热片式电容器封装的方法和相应的半导体封装
公开(公告)号：US20120282767A1
公开(公告)日：2012-11-08
申请号：US13173991
申请日：2011-06-30
申请人： Yonggang Jin , Yun Liu , Puay Gek Chua , Anandan Ramasamy , Yaohuang Huang , Kah Wee Gan
发明人： Yonggang Jin , Yun Liu , Puay Gek Chua , Anandan Ramasamy , Yaohuang Huang , Kah Wee Gan
IPC分类号： H01L21/60
CPC分类号： H01L21/568 , H01L23/3128 , H01L24/19 , H01L24/96 , H01L24/97 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/131 , H01L2224/16145 , H01L2224/16225 , H01L2924/01006 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01061 , H01L2924/01075 , H01L2924/014 , H01L2924/12042 , H01L2924/1461 , H01L2924/181 , H01L2924/00
摘要： A semiconductor packaging process includes drilling apertures in a reconstituted wafer, then filling the apertures with conductive paste by wiping a quantity of the paste across a back surface of the wafer so that paste is forced into the apertures. The paste is cured to form conductive posts. The wafer is thinned, and redistribution layers are formed on front and back surfaces of the wafer, with the posts acting as interconnections between the redistribution layers. In an alternative process, blind apertures are drilled. A dry film resist is applied to the front surface of the wafer, and patterned to expose the apertures. Conductive paste is applied from the front. To prevent paste from trapping air pockets in the apertures, the wiping process is performed under vacuum. After curing the paste, the wafer is thinned to expose the cured paste in the apertures, and redistribution layers are formed.
摘要翻译：半导体封装工艺包括在重构的晶片中的钻孔，然后通过在晶片的背面上擦拭一定量的糊料，将导电浆料填充到孔中，使得膏被迫进入孔中。该膏被固化以形成导电柱。晶片变薄，并且再分布层形成在晶片的前表面和后表面上，其中柱用作再分布层之间的互连。在另一种方法中，钻出盲孔。将干膜抗蚀剂施加到晶片的前表面，并图案化以露出孔。导电胶从前面涂敷。为了防止糊料在孔中捕获气穴，擦拭过程在真空下进行。固化糊剂后，将晶片变薄以露出孔中的固化糊料，形成再分布层。

14. 发明授权

US08766422B2 Through hole via filling using electroless plating 有权
标题翻译：通孔采用化学镀填充
公开(公告)号：US08766422B2
公开(公告)日：2014-07-01
申请号：US13098083
申请日：2011-04-29
申请人： Kah Wee Gan , Yonggang Jin , Yun Liu , Yaohuang Huang
发明人： Kah Wee Gan , Yonggang Jin , Yun Liu , Yaohuang Huang
IPC分类号： H01L23/02 , H01L23/04
CPC分类号： H01L24/19 , H01L21/486 , H01L21/561 , H01L21/568 , H01L21/76868 , H01L21/76873 , H01L23/49827 , H01L23/5389 , H01L24/20 , H01L24/24 , H01L24/82 , H01L24/96 , H01L25/105 , H01L25/16 , H01L25/50 , H01L2224/04105 , H01L2224/12105 , H01L2225/1035 , H01L2225/1052 , H01L2225/1058 , H01L2225/107 , H01L2924/00013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01073 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15747 , H01L2924/181 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00
摘要： An embedded wafer level ball grid array (eWLB) is formed by embedding a semiconductor die in a molding compound. A trench is formed in the molding compound with a laser drill. A first layer of copper is deposited on the sidewall of the trench by physical vapor deposition. A second layer of copper is then formed on the first layer of copper by an electroless process. A third layer of copper is then formed on the second layer by electroplating.
摘要翻译：嵌入式晶片级球栅阵列（eWLB）通过将半导体管芯嵌入到模塑料中而形成。在激光钻头的模塑料中形成沟槽。第一层铜通过物理气相沉积沉积在沟槽的侧壁上。然后通过无电解方法在第一层铜上形成第二层铜层。然后通过电镀在第二层上形成第三层铜层。

15. 发明申请

US20120168944A1 THROUGH HOLE VIA FILLING USING ELECTROLESS PLATING 有权
公开(公告)号：US20120168944A1
公开(公告)日：2012-07-05
申请号：US13098083
申请日：2011-04-29
申请人： Kah Wee Gan , Yonggang Jin , Yun Liu , Yaohuang Huang
发明人： Kah Wee Gan , Yonggang Jin , Yun Liu , Yaohuang Huang
IPC分类号： H01L23/498 , H01L21/50 , H01L21/768
CPC分类号： H01L24/19 , H01L21/486 , H01L21/561 , H01L21/568 , H01L21/76868 , H01L21/76873 , H01L23/49827 , H01L23/5389 , H01L24/20 , H01L24/24 , H01L24/82 , H01L24/96 , H01L25/105 , H01L25/16 , H01L25/50 , H01L2224/04105 , H01L2224/12105 , H01L2225/1035 , H01L2225/1052 , H01L2225/1058 , H01L2225/107 , H01L2924/00013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01073 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15747 , H01L2924/181 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00
摘要： An embedded wafer level ball grid array (eWLB) is formed by embedding a semiconductor die in a molding compound. A trench is formed in the molding compound with a laser drill. A first layer of copper is deposited on the sidewall of the trench by physical vapor deposition. A second layer of copper is then formed on the first layer of copper by an electroless process. A third layer of copper is then formed on the second layer by electroplating.

16. 发明申请

US20120168942A1 THROUGH HOLE VIA FILLING USING ELECTROLESS PLATING 有权
标题翻译：通过使用电镀镀层填充的通孔
公开(公告)号：US20120168942A1
公开(公告)日：2012-07-05
申请号：US12982697
申请日：2010-12-30
申请人： Kah Wee Gan , Yonggang Jin , Yun Liu , Yaohuang Huang
发明人： Kah Wee Gan , Yonggang Jin , Yun Liu , Yaohuang Huang
IPC分类号： H01L23/498 , H05K3/00 , H05K3/34 , H05K3/42
CPC分类号： H01L25/105 , H01L21/486 , H01L21/568 , H01L23/49827 , H01L23/5389 , H01L24/19 , H01L24/96 , H01L2224/04105 , H01L2224/12105 , H01L2225/1035 , H01L2225/1058 , H01L2924/14 , H01L2924/15747 , H01L2924/181 , Y10T29/413 , Y10T29/49144 , Y10T29/49165 , H01L2924/00
摘要： An embedded wafer level ball grid array (eWLB) is formed by embedding a semiconductor die in a molding compound. A trench is formed in the molding compound with a laser drill. A first layer of copper is deposited on the sidewall of the trench by physical vapor deposition. A second layer of copper is then formed on the first layer of copper by an electroless process. A third layer of copper is then formed on the second layer by electroplating.
摘要翻译：嵌入式晶片级球栅阵列（eWLB）通过将半导体管芯嵌入到模塑料中而形成。在激光钻头的模塑料中形成沟槽。第一层铜通过物理气相沉积沉积在沟槽的侧壁上。然后通过无电解方法在第一层铜上形成第二层铜层。然后通过电镀在第二层上形成第三层铜层。

17. 发明申请

US20120168938A1 PLASMA TREATMENT ON SEMICONDUCTOR WAFERS 有权
标题翻译：半导体波长处理等离子体处理
公开(公告)号：US20120168938A1
公开(公告)日：2012-07-05
申请号：US13327563
申请日：2011-12-15
申请人： Kah Wee Gan , Yonggang Jin , Anandan Ramasamy , Yun Liu
发明人： Kah Wee Gan , Yonggang Jin , Anandan Ramasamy , Yun Liu
IPC分类号： H01L23/488 , H01L21/78
CPC分类号： H01L21/3105 , H01L21/31116 , H01L21/561 , H01L21/568 , H01L23/3128 , H01L24/19 , H01L24/96 , H01L2224/12105 , H01L2924/14 , H01L2924/181 , H01L2924/00
摘要： A semiconductor wafer has integrated circuits formed thereon and a top passivation layer applied. The passivation layer is patterned and selectively etched to expose contact pads on each semiconductor die. The wafer is exposed to ionized gas causing the upper surface of passivation layer to roughen and to slightly roughen the upper surface of the contact pads. The wafer is cut to form a plurality of semiconductor dies each with a roughened passivation layer. The plurality of semiconductor dies are placed on an adhesive layer and a reconstituted wafer formed. Redistribution layers are formed to complete the semiconductor package having electrical contacts for establishing electrical connections external to the semiconductor package, after which the wafer is singulated to separate the dice.
摘要翻译：半导体晶片具有形成在其上的集成电路和施加的顶部钝化层。钝化层被图案化并选择性地蚀刻以暴露每个半导体管芯上的接触焊盘。将晶片暴露于电离气体中，导致钝化层的上表面变粗糙，并使接触垫的上表面略微变糙。切割晶片以形成多个具有粗糙化钝化层的半导体管芯。多个半导体管芯被放置在粘合剂层上并形成重构的晶片。形成再分布层，以完成具有用于建立半导体封装外部的电连接的电触头的半导体封装，然后将晶片单分割以分离晶片。

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