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11. 发明授权

US07737469B2 Semiconductor device having superjunction structure formed of p-type and n-type pillar regions 失效
标题翻译：具有由p型和n型柱状区域形成的超结构结构的半导体装置
公开(公告)号：US07737469B2
公开(公告)日：2010-06-15
申请号：US11748869
申请日：2007-05-15
申请人： Wataru Saito , Syotaro Ono , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta , Wataru Sekine
发明人： Wataru Saito , Syotaro Ono , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta , Wataru Sekine
IPC分类号： H01L29/74
CPC分类号： H01L29/872 , H01L29/0619 , H01L29/0623 , H01L29/0634 , H01L29/0696 , H01L29/0878 , H01L29/402 , H01L29/404 , H01L29/41741 , H01L29/7395 , H01L29/7397 , H01L29/7722 , H01L29/7806 , H01L29/7811 , H01L29/8611
摘要： A semiconductor device includes: a semiconductor layer of a first conductivity type; a first semiconductor pillar region of the first conductivity type provided on a major surface of the semiconductor layer; a second semiconductor pillar region of a second conductivity type provided adjacent to the first semiconductor pillar region on the major surface of the semiconductor layer, the second semiconductor pillar region forming a periodic arrangement structure substantially parallel to the major surface of the semiconductor layer together with the first semiconductor pillar region; a first main electrode; a first semiconductor region of the second conductivity type; a second semiconductor region of the first conductivity type; a second main electrode; a control electrode; and a high-resistance semiconductor layer provided on the semiconductor layer in an edge termination section surrounding the first semiconductor pillar region and the second semiconductor pillar region. The high-resistance semiconductor layer has a lower dopant concentration than the first semiconductor pillar region. A boundary region is provided between a device central region and the edge termination section. The first semiconductor pillar region and the second semiconductor pillar region adjacent to the high-resistance semiconductor layer in the boundary region have a depth decreasing stepwise toward the edge termination section.
摘要翻译：半导体器件包括：第一导电类型的半导体层; 设置在半导体层的主表面上的第一导电类型的第一半导体柱区域; 第二导电类型的第二半导体柱区域，与半导体层的主表面上的第一半导体柱区域相邻设置，第二半导体柱区域形成基本上平行于半导体层的主表面的周期性排列结构以及第一半导体柱区域; 第一主电极; 第二导电类型的第一半导体区域; 第一导电类型的第二半导体区域; 第二主电极; 控制电极; 以及设置在包围第一半导体柱区域和第二半导体柱区域的边缘终端部分的半导体层上的高电阻半导体层。高电阻半导体层的掺杂浓度低于第一半导体柱区域。边界区域设置在设备中心区域和边缘终端部分之间。边界区域中与高电阻半导体层相邻的第一半导体柱区域和第二半导体柱区域具有沿着边缘终止部分逐步减小的深度。

12. 发明申请

US20080290403A1 SEMICONDUCTOR APPARATUS 失效
公开(公告)号：US20080290403A1
公开(公告)日：2008-11-27
申请号：US12123072
申请日：2008-05-19
申请人： Syotaro ONO , Wataru Saito , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta , Wataru Sekine
发明人： Syotaro ONO , Wataru Saito , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta , Wataru Sekine
IPC分类号： H01L29/78
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0638 , H01L29/0878 , H01L29/7395 , H01L29/861 , H01L29/868 , H01L29/872
摘要： A semiconductor apparatus includes a first semiconductor layer, a second semiconductor layer provided on a major surface of the first semiconductor layer, a third semiconductor layer provided on the major surface and being adjacent to the second semiconductor layer, a termination semiconductor layer provided on the major surface of the first semiconductor layer in a termination region outside the device region, a channel stop layer, and a channel stop electrode. The channel stop layer is provided in contact with the termination semiconductor layer on the major surface of the first semiconductor layer in an outermost peripheral portion outside the termination semiconductor layer and has a higher impurity concentration than the termination semiconductor layer. The channel stop electrode is provided on at least part of a surface of the channel stop layer and projects toward the termination semiconductor layer beyond at least a superficial portion of the channel stop layer.
摘要翻译：半导体装置包括第一半导体层，设置在第一半导体层的主表面上的第二半导体层，设置在主表面上并与第二半导体层相邻的第三半导体层，设置在主体上的端接半导体层在器件区域外的终端区域中的第一半导体层的表面，沟道阻挡层和沟道停止电极。沟道阻挡层设置成与终端半导体层外部的最外周部分中的第一半导体层的主表面上的端接半导体层接触，并且具有比端接半导体层更高的杂质浓度。通道阻挡电极设置在通道阻挡层的表面的至少一部分上，并且朝向端子半导体层突出超过通道阻挡层的至少表面部分。

13. 发明授权

US08013360B2 Semiconductor device having a junction of P type pillar region and N type pillar region 有权
标题翻译：具有P型支柱区域和N型支柱区域的结的半导体器件
公开(公告)号：US08013360B2
公开(公告)日：2011-09-06
申请号：US12764763
申请日：2010-04-21
申请人： Wataru Saito , Syotaro Ono , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta , Wataru Sekine
发明人： Wataru Saito , Syotaro Ono , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta , Wataru Sekine
IPC分类号： H01L29/66
CPC分类号： H01L29/872 , H01L29/0619 , H01L29/0623 , H01L29/0634 , H01L29/0696 , H01L29/0878 , H01L29/402 , H01L29/404 , H01L29/41741 , H01L29/7395 , H01L29/7397 , H01L29/7722 , H01L29/7806 , H01L29/7811 , H01L29/8611
摘要： A semiconductor device includes: a semiconductor layer of a first conductivity type; a first semiconductor pillar region of the first conductivity type provided on a major surface of the semiconductor layer; a second semiconductor pillar region of a second conductivity type provided adjacent to the first semiconductor pillar region on the major surface of the semiconductor layer, the second semiconductor pillar region forming a periodic arrangement structure substantially parallel to the major surface of the semiconductor layer together with the first semiconductor pillar region; a first main electrode; a first semiconductor region of the second conductivity type; a second semiconductor region of the first conductivity type; a second main electrode; a control electrode; and a high-resistance semiconductor layer provided on the semiconductor layer in an edge termination section surrounding the first semiconductor pillar region and the second semiconductor pillar region. The high-resistance semiconductor layer has a lower dopant concentration than the first semiconductor pillar region. A boundary region is provided between a device central region and the edge termination section. The first semiconductor pillar region and the second semiconductor pillar region adjacent to the high-resistance semiconductor layer in the boundary region have a depth decreasing stepwise toward the edge termination section.
摘要翻译：半导体器件包括：第一导电类型的半导体层; 设置在半导体层的主表面上的第一导电类型的第一半导体柱区域; 第二导电类型的第二半导体柱区域，与半导体层的主表面上的第一半导体柱区域相邻设置，第二半导体柱区域形成基本上平行于半导体层的主表面的周期性排列结构以及第一半导体柱区域; 第一主电极; 第二导电类型的第一半导体区域; 第一导电类型的第二半导体区域; 第二主电极; 控制电极; 以及设置在包围第一半导体柱区域和第二半导体柱区域的边缘终端部分的半导体层上的高电阻半导体层。高电阻半导体层的掺杂浓度低于第一半导体柱区域。边界区域设置在设备中心区域和边缘终端部分之间。边界区域中与高电阻半导体层相邻的第一半导体柱区域和第二半导体柱区域具有沿着边缘终止部分逐步减小的深度。

14. 发明申请

US20100200936A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100200936A1
公开(公告)日：2010-08-12
申请号：US12764763
申请日：2010-04-21
申请人： Wataru SAITO , Syotaro Ono , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta , Wataru Sekine
发明人： Wataru SAITO , Syotaro Ono , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta , Wataru Sekine
IPC分类号： H01L29/78
CPC分类号： H01L29/872 , H01L29/0619 , H01L29/0623 , H01L29/0634 , H01L29/0696 , H01L29/0878 , H01L29/402 , H01L29/404 , H01L29/41741 , H01L29/7395 , H01L29/7397 , H01L29/7722 , H01L29/7806 , H01L29/7811 , H01L29/8611
摘要： A semiconductor device includes: a semiconductor layer of a first conductivity type; a first semiconductor pillar region of the first conductivity type provided on a major surface of the semiconductor layer; a second semiconductor pillar region of a second conductivity type provided adjacent to the first semiconductor pillar region on the major surface of the semiconductor layer, the second semiconductor pillar region forming a periodic arrangement structure substantially parallel to the major surface of the semiconductor layer together with the first semiconductor pillar region; a first main electrode; a first semiconductor region of the second conductivity type; a second semiconductor region of the first conductivity type; a second main electrode; a control electrode; and a high-resistance semiconductor layer provided on the semiconductor layer in an edge termination section surrounding the first semiconductor pillar region and the second semiconductor pillar region. The high-resistance semiconductor layer has a lower dopant concentration than the first semiconductor pillar region. A boundary region is provided between a device central region and the edge termination section. The first semiconductor pillar region and the second semiconductor pillar region adjacent to the high-resistance semiconductor layer in the boundary region have a depth decreasing stepwise toward the edge termination section.
摘要翻译：半导体器件包括：第一导电类型的半导体层; 设置在半导体层的主表面上的第一导电类型的第一半导体柱区域; 第二导电类型的第二半导体柱区域，与半导体层的主表面上的第一半导体柱区域相邻设置，第二半导体柱区域形成基本上平行于半导体层的主表面的周期性排列结构以及第一半导体柱区域; 第一主电极; 第二导电类型的第一半导体区域; 第一导电类型的第二半导体区域; 第二主电极; 控制电极; 以及设置在包围第一半导体柱区域和第二半导体柱区域的边缘终端部分的半导体层上的高电阻半导体层。高电阻半导体层的掺杂浓度低于第一半导体柱区域。边界区域设置在设备中心区域和边缘终端部分之间。边界区域中与高电阻半导体层相邻的第一半导体柱区域和第二半导体柱区域具有沿着边缘终止部分逐步减小的深度。

15. 发明申请

US20090101974A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090101974A1
公开(公告)日：2009-04-23
申请号：US12252872
申请日：2008-10-16
申请人： Wataru SAITO , Syotaro Ono , Masaru Izumisawa , Yasuto Sumi , Hiroshi Ohta , Wataru Sekine , Nana Hatano
发明人： Wataru SAITO , Syotaro Ono , Masaru Izumisawa , Yasuto Sumi , Hiroshi Ohta , Wataru Sekine , Nana Hatano
IPC分类号： H01L29/78
CPC分类号： H01L29/0634 , H01L29/0615 , H01L29/0638 , H01L29/0696 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/7811
摘要： A semiconductor device includes an n+ type semiconductor substrate 1 and a super junction region that has, on the top of the substrate 1, an n and p type pillar regions 2 and 3 provided alternately. The device also includes, in the top surface of the super junction region, a p type base region 4 and an n type source layer 5. The device also includes a gate electrode 7 on the region 4 and layer 5 via a gate-insulating film 6, a drain electrode 9 on the bottom of the substrate 1, and a source electrode 8 on the top of the substrate 1. In the top surface of the super junction region in the terminal region, a RESURF region 10 is formed. The RESURF region has a comb-like planar shape with repeatedly-formed teeth having tips facing the end portion of the terminal region.
摘要翻译：半导体器件包括n +型半导体衬底1和超结区，其在衬底1的顶部上交替设置n和p型柱状区域2,3。该器件还在超结区域的顶表面中包括ap型基极区域4和n型源极层5.该器件还包括位于区域4上的栅电极7和通过栅极绝缘膜6的层5 ，基板1底部的漏电极9以及基板1顶部的源极8.在端子区域的超结区域的上表面形成有RESURF区域10。 RESURF区域具有梳状平面形状，具有重复形成的齿，其尖端面向终端区域的端部。

16. 发明授权

US08610210B2 Power semiconductor device and method for manufacturing same 失效
标题翻译：功率半导体器件及其制造方法
公开(公告)号：US08610210B2
公开(公告)日：2013-12-17
申请号：US12840201
申请日：2010-07-20
申请人： Hiroshi Ohta , Yasuto Sumi , Kiyoshi Kimura , Wataru Sekine , Wataru Saito , Syotaro Ono , Munehisa Yabuzaki , Nana Hatano , Miho Watanabe
发明人： Hiroshi Ohta , Yasuto Sumi , Kiyoshi Kimura , Wataru Sekine , Wataru Saito , Syotaro Ono , Munehisa Yabuzaki , Nana Hatano , Miho Watanabe
IPC分类号： H01L29/66
CPC分类号： H01L29/66712 , H01L29/0619 , H01L29/0634 , H01L29/0638 , H01L29/0696 , H01L29/1095 , H01L29/402 , H01L29/7811
摘要： According to one embodiment, a power semiconductor device includes a first semiconductor layer, and first, second and third semiconductor regions. The first semiconductor layer has a first conductivity type. The first semiconductor regions have a second conductivity type, and are formed with periodicity in a lateral direction in a second semiconductor layer of the first conductivity type. The second semiconductor layer is provided on a major surface of the first semiconductor layer in a device portion with a main current path formed in a vertical direction generally perpendicular to the major surface and in a terminal portion provided around the device portion. The second semiconductor region has the first conductivity type and is a portion of the second semiconductor layer sandwiched between adjacent ones of the first semiconductor regions. The third semiconductor regions have the second conductivity type and are provided below the first semiconductor regions in the terminal portion.
摘要翻译：根据一个实施例，功率半导体器件包括第一半导体层以及第一，第二和第三半导体区域。第一半导体层具有第一导电类型。第一半导体区域具有第二导电类型，并且在第一导电类型的第二半导体层中在横向方向上形成周期性。第二半导体层设置在器件部分的第一半导体层的主表面上，其主电流通道形成在大体上垂直于主表面的垂直方向上，以及设置在器件部分周围的端子部分中。第二半导体区域具有第一导电类型，并且是夹在相邻的第一半导体区域中的第二半导体层的一部分。第三半导体区域具有第二导电类型并且设置在端子部分中的第一半导体区域的下方。

17. 发明申请

US20070272979A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20070272979A1
公开(公告)日：2007-11-29
申请号：US11748869
申请日：2007-05-15
申请人： Wataru SAITO , Syotaro Ono , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta , Wataru Sekine
发明人： Wataru SAITO , Syotaro Ono , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta , Wataru Sekine
IPC分类号： H01L29/76
CPC分类号： H01L29/872 , H01L29/0619 , H01L29/0623 , H01L29/0634 , H01L29/0696 , H01L29/0878 , H01L29/402 , H01L29/404 , H01L29/41741 , H01L29/7395 , H01L29/7397 , H01L29/7722 , H01L29/7806 , H01L29/7811 , H01L29/8611
摘要： A semiconductor device includes: a semiconductor layer of a first conductivity type; a first semiconductor pillar region of the first conductivity type provided on a major surface of the semiconductor layer; a second semiconductor pillar region of a second conductivity type provided adjacent to the first semiconductor pillar region on the major surface of the semiconductor layer, the second semiconductor pillar region forming a periodic arrangement structure substantially parallel to the major surface of the semiconductor layer together with the first semiconductor pillar region; a first main electrode; a first semiconductor region of the second conductivity type; a second semiconductor region of the first conductivity type; a second main electrode; a control electrode; and a high-resistance semiconductor layer provided on the semiconductor layer in an edge termination section surrounding the first semiconductor pillar region and the second semiconductor pillar region. The high-resistance semiconductor layer has a lower dopant concentration than the first semiconductor pillar region. A boundary region is provided between a device central region and the edge termination section. The first semiconductor pillar region and the second semiconductor pillar region adjacent to the high-resistance semiconductor layer in the boundary region have a depth decreasing stepwise toward the edge termination section.
摘要翻译：半导体器件包括：第一导电类型的半导体层; 设置在半导体层的主表面上的第一导电类型的第一半导体柱区域; 第二导电类型的第二半导体柱区域，与半导体层的主表面上的第一半导体柱区域相邻设置，第二半导体柱区域形成基本上平行于半导体层的主表面的周期性排列结构以及第一半导体柱区域; 第一主电极; 第二导电类型的第一半导体区域; 第一导电类型的第二半导体区域; 第二主电极; 控制电极; 以及设置在包围第一半导体柱区域和第二半导体柱区域的边缘终端部分的半导体层上的高电阻半导体层。高电阻半导体层的掺杂浓度低于第一半导体柱区域。边界区域设置在设备中心区域和边缘终端部分之间。边界区域中与高电阻半导体层相邻的第一半导体柱区域和第二半导体柱区域具有沿着边缘终止部分逐步减小的深度。

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