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11. 发明申请

WO2009079244A1 SYSTEM AND METHOD FOR ROUTING CONNECTIONS 审中-公开
标题翻译：用于路由连接的系统和方法
公开(公告)号：WO2009079244A1
公开(公告)日：2009-06-25
申请号：PCT/US2008/085782
申请日：2008-12-08
申请人： DSM SOLUTIONS, INC. , ZARKESH-HA, Payman , HAMLIN, Christopher, L. , KAPOOR, Ashok, K. , KOFORD, James, S. , VORA, Madhukar, B.
发明人： ZARKESH-HA, Payman , HAMLIN, Christopher, L. , KAPOOR, Ashok, K. , KOFORD, James, S. , VORA, Madhukar, B.
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method for modeling a circuit includes receiving a netlist that defines a plurality of connections between a plurality of circuit elements and identifying a subset of the connections. The method also includes routing the identified connections with a first group of wires having a first wire width and routing at least a portion of the remaining connections with a second wire width. The second wire width is smaller than the first wire width. The method further includes replacing the first group of wires with a third group of wires having the second wire width.
摘要翻译：一种用于对电路进行建模的方法包括：接收网表，其定义多个电路元件之间的多个连接并识别连接的子集。该方法还包括使用具有第一线宽度的第一组线路路由所识别的连接，并且以第二线宽度路由至少一部分剩余的连接。第二线宽小于第一线宽度。该方法还包括用具有第二线宽度的第三组线代替第一组线。

12. 发明申请

WO2008057814A3 DEVICE WITH PATTERNED SEMICONDUCTOR ELECTRODE STRUCTURE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：具有图形半导体电极结构的器件及其制造方法
公开(公告)号：WO2008057814A3
公开(公告)日：2008-07-10
申请号：PCT/US2007082775
申请日：2007-10-29
申请人： DSM SOLUTIONS INC , VORA MADHUKAR B
发明人： VORA MADHUKAR B
IPC分类号： H01L21/762 , H01L21/337 , H01L29/808
CPC分类号： H01L27/0623 , H01L21/02071 , H01L21/28525 , H01L21/32134 , H01L21/32137 , H01L21/76897 , H01L21/823807 , H01L21/823828 , H01L21/823842 , H01L21/823878 , H01L21/8249 , H01L27/0922 , H01L27/098 , H01L29/66901 , H01L29/78
摘要： A method of forming a semiconductor device can include forming a first layer of semiconductor material in contact with a first area of a substrate. The first area can be adjacent to at least one electrical isolation structure that extends into the substrate and has a top portion extending above a surface of the substrate. The method can also include etching, with a degree of anisotropy, the first layer to form at least a first structure in contact with the first area. Further, in a step separate from the etching step, retention of residual semiconductor material at a junction of the substrate and the at least one electrical isolation structure can be prevented.
摘要翻译：形成半导体器件的方法可以包括形成与衬底的第一区域接触的第一半导体材料层。第一区域可以与延伸到衬底中的至少一个电隔离结构相邻，并且具有在衬底的表面上方延伸的顶部部分。该方法还可以包括具有一定程度的各向异性的蚀刻，第一层以形成与第一区域接触的至少第一结构。此外，在与蚀刻步骤分离的步骤中，可以防止残留半导体材料在基板和至少一个电隔离结构的接合处的保留。

13. 发明申请

WO2008055089A3 SEMICONDUCTOR DEVICE, DESIGN METHOD AND STRUCTURE 审中-公开
公开(公告)号：WO2008055089A3
公开(公告)日：2008-05-08
申请号：PCT/US2007/082781
申请日：2007-10-29
申请人： DSM SOLUTIONS, INC. , VORA, Madhukar, B.
发明人： VORA, Madhukar, B.
IPC分类号： H01L27/11 , H01L21/8244
摘要： The present invention relates generally to semiconductor circuits, and more particularly to semiconductor circuits having interconnected field effect transistors, methods of designing such circuits, and data structures representing such circuits.

14. 发明申请

WO2008008764A3 OXIDE ISOLATED METAL SILICON-GATE JFET 审中-公开
标题翻译：氧化物隔离金属硅栅极
公开(公告)号：WO2008008764A3
公开(公告)日：2008-05-08
申请号：PCT/US2007073134
申请日：2007-07-10
申请人： DSM SOLUTIONS INC , KAPOOR ASHOK KUMAR , VORA MADHUKAR
发明人： KAPOOR ASHOK KUMAR , VORA MADHUKAR
IPC分类号： H01L29/80 , H01L21/337
CPC分类号： H01L29/808 , H01L29/66901
摘要： A JFET structure with self-aligned metal source, drain and gate contacts with very low resistivity and very small feature sizes. Small source, drain and gate openings are etched in a thin dielectric layer which has a thickness set according to the desired source, gate and drain opening sizes, said dielectric layer having a nitride top layer. Metal is deposited on top of said dielectric layer to fill said openings and the metal is polished back to the top of the dielectric layer to achieve thin source, drain and gate contacts. Some embodiments include an anti-leakage poly-silicon layer lining the contact holes and all embodiments where spiking may occur include a barrier metal layer.
摘要翻译：具有自对准金属源，漏极和栅极接触的JFET结构，具有非常低的电阻率和非常小的特征尺寸。小的源极，漏极和栅极开口被蚀刻在具有根据期望的源极，栅极和漏极开口尺寸设置的厚度的薄介电层中，所述介电层具有氮化物顶层。金属沉积在所述介电层的顶部以填充所述开口并且金属被抛光回到电介质层的顶部以实现薄的源极，漏极和栅极接触。一些实施例包括衬在接触孔上的防漏多晶硅层，并且可能发生尖峰的所有实施例包括阻挡金属层。

15. 发明申请

WO2007024774A3 APPARATUS AND METHODS FOR HIGH-DENSITY CHIP CONNECTIVITY 审中-公开
标题翻译：用于高密度芯片连接的装置和方法
公开(公告)号：WO2007024774A3
公开(公告)日：2007-11-01
申请号：PCT/US2006032592
申请日：2006-08-22
申请人： VORA MADHUKAR B
发明人： VORA MADHUKAR B
IPC分类号： H01L25/065 , H01L21/98
CPC分类号： H01L25/0657 , H01L25/50 , H01L2224/16 , H01L2225/06513 , H01L2225/06593 , H01L2924/01019 , H01L2924/01023 , H01L2924/01033 , H01L2924/01079 , H01L2924/10253 , H01L2924/00
摘要： Self-alignment structures, such as micro-balls (608) and V-grooves (606), may be formed on chips (605, 607) made by different processes. The self-alignment structures may be aligned to mask layers within an accuracy of one-half the smallest feature size inside a chip. For example, the alignment structures can align an array of pads (803, 807) having a pitch of 0.6 microns, compared to a pitch of 100 microns available with today's Ball Grid Array (BGA) technology. As a result, circuits in the mated chips (605, 607) can communicate via the pads (803, 807) with the same speed or clock frequency as if in a single chip. For example, clock rates between interconnected chips (605, 607) can be increased from 100 MHz to 4 GHz due to low capacitance of the interconnected pads (803, 807). Because high-density arrays of pads (803, 807) can interconnect chips, chips (605, 607) can be made smaller, thereby reducing cost of chips (605, 607) by order(s) of magnitude.
摘要翻译：诸如微球（608）和V形槽（606）的自对准结构可以形成在由不同工艺制成的芯片（605,607）上。自对准结构可以对准以在芯片内的最小特征尺寸的一半的精度内掩模层。例如，对准结构可以对齐具有0.6微米间距的焊盘（803,807）的阵列，而与当今的球栅阵列（BGA）技术可用的100微米的间距相比。结果，配合的芯片（605,607）中的电路可以以与在单个芯片中相同的速度或时钟频率经由焊盘（803,807）进行通信。例如，由于互连焊盘（803,807）的低电容，互连芯片（605,607）之间的时钟速率可以从100MHz增加到4GHz。因为高密度的焊盘阵列（803,807）可以互连芯片，所以可以使芯片（605,607）更小，从而将芯片（605,607）的成本降低数量级。

16. 发明申请

WO2009151769A3 SYSTEM AND METHOD FOR ROUTING CONNECTIONS WITH IMPROVED INTERCONNECT THICKNESS 审中-公开
标题翻译：具有改进的互连厚度的连接的系统和方法
公开(公告)号：WO2009151769A3
公开(公告)日：2010-04-22
申请号：PCT/US2009040460
申请日：2009-04-14
申请人： DSM SOLUTIONS INC , ZARKESH-HA PAYMAN , HAMLIN CHRISTOPHER L , KAPOOR ASHOK K , KOFORD JAMES S , VORA MADHUKAR B
发明人： ZARKESH-HA PAYMAN , HAMLIN CHRISTOPHER L , KAPOOR ASHOK K , KOFORD JAMES S , VORA MADHUKAR B
IPC分类号： H01L29/40 , H01L29/80
CPC分类号： H01L23/5283 , G06F17/5077 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A method for modeling a circuit includes generating a circuit model based on a netlist that defines a plurality of connections between a plurality of circuit elements. The circuit model includes a model of one or more of the circuit elements. The method further includes determining a wire width associated with at least a selected connection based, at least in part, on design rules associated with the netlist. Additionally, the method includes determining a wire thickness associated with the selected connection based, at least in part, on a signal delay associated with the wire thickness. Furthermore, the method also includes routing the selected connection in the circuit model using a wire having a width substantially equal to the wire width calculated for the connection and a thickness equal to the wire thickness calculated for the connection and storing the circuit model in an electronic storage media.
摘要翻译：一种用于对电路进行建模的方法包括基于限定多个电路元件之间的多个连接的网表生成电路模型。电路模型包括一个或多个电路元件的模型。该方法还包括至少部分地基于与网表相关联的设计规则来确定与至少所选连接相关联的线宽度。另外，该方法包括至少部分地基于与线材厚度相关联的信号延迟来确定与所选择的连接相关联的线材厚度。此外，该方法还包括使用具有基本上等于为连接计算出的线宽度的宽度的线和对于连接计算的线厚度等于电路模型中的所选择的连接来路由选择的连接，并将电路模型存储在电子储存媒介。

17. 发明申请

WO2009151769A2 SYSTEM AND METHOD FOR ROUTING CONNECTIONS WITH IMPROVED INTERCONNECT THICKNESS 审中-公开
标题翻译：具有改进的互连厚度的连接的系统和方法
公开(公告)号：WO2009151769A2
公开(公告)日：2009-12-17
申请号：PCT/US2009/040460
申请日：2009-04-14
申请人： DSM SOLUTIONS, INC. , ZARKESH-HA, Payman , HAMLIN, Christopher, L. , KAPOOR, Ashok, K. , KOFORD, James, S. , VORA, Madhukar, B.
发明人： ZARKESH-HA, Payman , HAMLIN, Christopher, L. , KAPOOR, Ashok, K. , KOFORD, James, S. , VORA, Madhukar, B.
CPC分类号： H01L23/5283 , G06F17/5077 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A method for modeling a circuit includes generating a circuit model based on a netlist that defines a plurality of connections between a plurality of circuit elements. The circuit model includes a model of one or more of the circuit elements. The method further includes determining a wire width associated with at least a selected connection based, at least in part, on design rules associated with the netlist. Additionally, the method includes determining a wire thickness associated with the selected connection based, at least in part, on a signal delay associated with the wire thickness. Furthermore, the method also includes routing the selected connection in the circuit model using a wire having a width substantially equal to the wire width calculated for the connection and a thickness equal to the wire thickness calculated for the connection and storing the circuit model in an electronic storage media.
摘要翻译：一种用于对电路进行建模的方法包括基于限定多个电路元件之间的多个连接的网表生成电路模型。电路模型包括一个或多个电路元件的模型。该方法还包括至少部分地基于与网表相关联的设计规则来确定与至少所选连接相关联的线宽度。另外，该方法包括至少部分地基于与线材厚度相关联的信号延迟来确定与所选择的连接相关联的线材厚度。此外，该方法还包括使用具有基本上等于为连接计算出的线宽度的宽度的线和对于连接计算的线厚度等于电路模型中的所选择的连接来路由选择的连接，并将电路模型存储在电子储存媒介。

18. 发明申请

WO2008134148A1 JUNCTION FIELD EFFECT TRANSISTORS IN GERMANIUM AND SILICON-GERMANIUM ALLOYS AND METHOD FOR MAKING AND USING 审中-公开
标题翻译：锗和锗 - 锗合金中的结型场效应晶体管及其制造和使用方法
公开(公告)号：WO2008134148A1
公开(公告)日：2008-11-06
申请号：PCT/US2008/057945
申请日：2008-03-21
申请人： DSM SOLUTIONS, INC. , KAPOOR, Ashok Kumar , VORA, Madhukar B. , ZHANG, Weimin , SONKUSALE, Sachin R. , LIU, Yujie
发明人： KAPOOR, Ashok Kumar , VORA, Madhukar B. , ZHANG, Weimin , SONKUSALE, Sachin R. , LIU, Yujie
IPC分类号： H01L29/16 , H01L29/161 , H01L29/808 , H01L21/337 , H01L29/10 , H01L29/08 , H01L21/225 , H01L29/165 , H01L29/45 , H01L29/06 , H01L21/762 , H01L21/761
CPC分类号： H01L29/66901 , H01L21/2257 , H01L21/761 , H01L21/76224 , H01L29/0653 , H01L29/0843 , H01L29/1066 , H01L29/1075 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/45 , H01L29/808 , H01L29/8086
摘要： Junction field effect transistors (JFET) formed in substrates containing germanium. JFETs having polycrystalline semiconductor surface contacts (562, 530, 560, 532) with self-aligned suicide (580) formed thereon and self-aligned source, drain and gate regions (520, 522,540) formed by thermal drive-in of impurities from surface contacts into the substrate, and implanted link regions (522, 526). Others have a polycrystalline semiconductor gate surface contact and metal back gate, source and drain contacts and a metal surface contact to the gate surface contact with implanted source and drains and a self -aligned gate region. JFETs having a polycrystalline semiconductor gate surface contact and metal back gate, source and drain contacts and a metal surface contact to the- gate surface contact with implanted source and drains and a self-aligned gate region and suicide formed on the top of the source, drain and back gate contacts and on top of the gate polycrystalline semiconductor gate contact to which the metal surface contacts make electrical contact.
摘要翻译：在包含锗的衬底中形成的结型场效应晶体管（JFET）。具有在其上形成有自对准硅化物（580）的多晶半导体表面接触（562,530,560,532）的JFET，以及通过来自表面的杂质的热传导形成的自对准源极，漏极和栅极区域（520,522,540）接触到衬底中，以及植入的链接区域（522,526）。其他具有多晶半导体栅极表面接触和金属后栅极，源极和漏极接触以及与栅极表面接触的金属表面接触与注入源和漏极以及自对准栅极区域。具有多晶半导体栅极表面接触和金属背栅极，源极和漏极接触以及与栅极表面的金属表面接触的JFET与植入源和漏极接触，并且形成在源的顶部上的自对准栅极区域和硅化物，漏极和后栅极触点，并且在栅极多晶半导体栅极触点的顶部与金属表面接触形成电接触。

19. 发明申请

WO2008057814A2 DEVICE WITH PATTERNED SEMICONDUCTOR ELECTRODE STRUCTURE AND METHOD OF MANUFACTURE 审中-公开
标题翻译：具有图形半导体电极结构的器件及其制造方法
公开(公告)号：WO2008057814A2
公开(公告)日：2008-05-15
申请号：PCT/US2007/082775
申请日：2007-10-29
申请人： DSM SOLUTIONS, INC. , VORA, Madhukar, B.
发明人： VORA, Madhukar, B.
CPC分类号： H01L27/0623 , H01L21/02071 , H01L21/28525 , H01L21/32134 , H01L21/32137 , H01L21/76897 , H01L21/823807 , H01L21/823828 , H01L21/823842 , H01L21/823878 , H01L21/8249 , H01L27/0922 , H01L27/098 , H01L29/66901 , H01L29/78
摘要： A method of forming a semiconductor device can include forming a first layer of semiconductor material in contact with a first area of a substrate. The first area can be adjacent to at least one electrical isolation structure that extends into the substrate and has a top portion extending above a surface of the substrate. The method can also include etching, with a degree of anisotropy, the first layer to form at least a first structure in contact with the first area. Further, in a step separate from the etching step, retention of residual semiconductor material at a junction of the substrate and the at least one electrical isolation structure can be prevented.
摘要翻译：形成半导体器件的方法可以包括形成与衬底的第一区域接触的第一半导体材料层。第一区域可以与延伸到衬底中的至少一个电隔离结构相邻，并且具有在衬底的表面上方延伸的顶部部分。该方法还可以包括具有一定程度的各向异性的蚀刻，第一层以形成与第一区域接触的至少第一结构。此外，在与蚀刻步骤分离的步骤中，可以防止残留半导体材料在基板和至少一个电隔离结构的接合处的保留。

20. 发明申请

WO2008055095A2 JUNCTION ISOLATED POLY-SILICON GATE JFET 审中-公开
标题翻译：结隔离多晶硅栅极JFET
公开(公告)号：WO2008055095A2
公开(公告)日：2008-05-08
申请号：PCT/US2007/082815
申请日：2007-10-29
申请人： DSM SOLUTIONS, INC. , VORA, Madhukar, B.
发明人： VORA, Madhukar, B.
IPC分类号： H01L21/337 , H01L29/808 , H01L21/761 , H01L27/098
CPC分类号： H01L29/808 , H01L27/098 , H01L29/66901
摘要： An integrated Junction Field Effect Transistor is disclosed which is much smaller and much less expensive to fabricate because it does not use Shallow Trench Isolation or field oxide in the semiconductor substrate to isolate separate transistors. Instead, a layer of insulating material is formed on the top surface of said substrate, and interconnect trenches are etched in said insulating layer which do not go all the way down to the semiconductor substrate. Contact openings are etched in the insulating layer all the way down to the semiconductor layer. Doped poly-silicon is formed in the contact openings and interconnect trenches and silicide is formed on tops of the poly-silicon. This contact and interconnect structure applies to any integrated transistor. The integrated JFET disclosed herein does not use STI or field oxide and uses junction isolation. A conventional JFET is built in a P- well. The P- well is encapsulated in an N-well which is implanted into the substrate. Separate contacts to the P-well, N-well and substrate are formed as well as to the source, drain and gate so that the device can be isolated by reverse-biasing a PN junction. Operating voltage is restricted to less than 0.7 volts to prevent latching.
摘要翻译：公开了一种集成结型场效应晶体管，其制造要小得多，成本更低，因为它不在半导体衬底中使用浅沟槽隔离或场氧化物来隔离单独的晶体管。相反，在所述衬底的顶表面上形成绝缘材料层，并且在所述绝缘层中蚀刻互连沟槽，所述绝缘层不会完全向下到达半导体衬底。接触开口在绝缘层中一直被蚀刻到半导体层。掺杂的多晶硅形成在接触开口和互连沟槽中，硅化物形成在多晶硅的顶部。该接触和互连结构适用于任何集成晶体管。本文公开的集成JFET不使用STI或场氧化物并且使用结隔离。传统的JFET内置在P阱中。 P-阱被封装在植入衬底中的N阱中。形成与P阱，N阱和衬底的单独接触以及源极，漏极和栅极，使得可以通过反向偏置PN结来隔离器件。工作电压限制在小于0.7伏，以防止锁定。

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