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11. 发明授权

US08381227B2 System and method of inter-connection between components using software bus 有权
标题翻译：使用软件总线的组件之间的相互连接的系统和方法
公开(公告)号：US08381227B2
公开(公告)日：2013-02-19
申请号：US12453514
申请日：2009-05-13
申请人： Young Sam Shin , Seung Won Lee
发明人： Young Sam Shin , Seung Won Lee
IPC分类号： G06F9/54
CPC分类号： G06F13/102
摘要： A method for inter-connection between components using a software bus, which may analyze whether a port in which at least one component is connected with each other is a data transmission port or a function interface calling port in accordance with an application of the port, determine an execution attribute of the port based on an analyzed result, and control the port in accordance with the execution attribute of the port. The function interface calling port may be divided into any one of a thread generation-connection port for each request using an attribute of an on-demand function calling port, or a recursive server connection port using an attribute of an on load function calling port in accordance with a type of the called port.
摘要翻译：一种使用软件总线的组件之间的相互连接的方法，其可以分析其中至少一个组件彼此连接的端口是否是根据端口的应用的数据传输端口或功能接口呼叫端口，根据分析结果确定端口的执行属性，并根据端口的执行属性来控制端口。功能接口调用端口可以使用按需功能调用端口的属性或使用加载功能调用端口的属性的递归服务器连接端口将每个请求划分为线程生成连接端口中的任何一个根据被叫端口的类型。

12. 发明授权

US08369874B2 Method and system for providing a mobile terminal search service 失效
标题翻译：提供移动终端搜索服务的方法和系统
公开(公告)号：US08369874B2
公开(公告)日：2013-02-05
申请号：US12400896
申请日：2009-03-10
申请人： Seung Won Lee
发明人： Seung Won Lee
IPC分类号： H04W24/00
CPC分类号： H04M1/72544 , H04L67/18 , H04L67/306 , H04M1/72572 , H04W4/02
摘要： A method and system for providing a mobile terminal search service includes the steps of (a) requesting, by a first mobile terminal, to search for a second mobile terminal, the first mobile terminal having avatar information stored thereon, and (b) searching for the second mobile terminal within a geographical range corresponding to the avatar information of the first mobile terminal.
摘要翻译：一种用于提供移动终端搜索服务的方法和系统包括以下步骤：（a）由第一移动终端请求搜索第二移动终端，所述第一移动终端具有存储在其上的化身信息，以及（b）搜索所述第二移动终端在对应于所述第一移动终端的化身信息的地理范围内。

13. 发明申请

US20120113740A1 ROW DECODER CIRCUIT 失效
标题翻译： ROW解码器电路
公开(公告)号：US20120113740A1
公开(公告)日：2012-05-10
申请号：US13238816
申请日：2011-09-21
申请人： Seung-Won Lee
发明人： Seung-Won Lee
IPC分类号： G11C8/08 , G11C8/10
CPC分类号： G11C8/10 , G11C8/08 , G11C16/08
摘要： A row decoder circuit includes a decoding unit and first and second wordline driving units. The decoding unit generates a first driving signal and a second driving signal based on a selection signal and wordline voltages. A voltage level of the first driving signal and a voltage level of the second driving signal depend on an operation mode. The first wordline driving unit is connected to a first wordline and outputs one of the first driving signal and the second driving signal as a first wordline driving signal based on first driving control signals. The second wordline driving unit is connected to a second wordline and outputs one of the first driving signal and the second driving signal as a second wordline driving signal based on second driving control signals.
摘要翻译：行解码器电路包括解码单元和第一和第二字线驱动单元。解码单元基于选择信号和字线电压产生第一驱动信号和第二驱动信号。第一驱动信号的电压电平和第二驱动信号的电压电平取决于操作模式。第一字线驱动单元连接到第一字线，并且基于第一驱动控制信号，将第一驱动信号和第二驱动信号之一作为第一字线驱动信号输出。第二字线驱动单元连接到第二字线，并且基于第二驱动控制信号输出第一驱动信号和第二驱动信号中的一个作为第二字线驱动信号。

14. 发明申请

US20120086282A1 Smart Cards 有权
标题翻译：智能卡
公开(公告)号：US20120086282A1
公开(公告)日：2012-04-12
申请号：US13268144
申请日：2011-10-07
申请人： Seung-Won Lee
发明人： Seung-Won Lee
IPC分类号： H02J1/00
CPC分类号： G05F1/56 , G05F1/563 , G05F1/613 , G05F1/614 , H02J7/025 , H02J17/00 , H02J50/10 , H02J50/80 , Y10T307/707
摘要： A smart card includes an internal voltage generator, a clock generator, and an internal circuit. The internal voltage generator generates a first internal voltage and a second internal voltage based on an input voltage received through an antenna. A level of the second internal voltage is lower than a level of the first internal voltage. The clock generator receives the first internal voltage and the second internal voltage to generate a clock signal. A frequency of the clock signal is changed according to the level of the first internal voltage. The internal circuit operates based on the clock signal and the second internal voltage.
摘要翻译：智能卡包括内部电压发生器，时钟发生器和内部电路。内部电压发生器基于通过天线接收的输入电压产生第一内部电压和第二内部电压。第二内部电压的电平低于第一内部电压的电平。时钟发生器接收第一内部电压和第二内部电压以产生时钟信号。时钟信号的频率根据第一内部电压的电平而改变。内部电路基于时钟信号和第二内部电压进行工作。

15. 发明授权

US08149635B2 Non-volatile memory device and program method thereof 有权
标题翻译：非易失性存储器件及其程序方法
公开(公告)号：US08149635B2
公开(公告)日：2012-04-03
申请号：US12689091
申请日：2010-01-18
申请人： Seung-Won Lee
发明人： Seung-Won Lee
IPC分类号： G11C7/00
CPC分类号： G11C16/3454 , G11C16/10
摘要： A non-volatile memory device including a memory cell array; a read/write circuit configured to drive bit lines of the memory cell array with a negative bit line voltage according to data to be programmed; a bit line setup-time measuring circuit configured to measure the bit line setup-time, which may be a function of the amount of data to be programmed, at each ISPP program loop; and a control logic configured to control the program voltage and/or the applied time of a program voltage applied to the selected wordline of the memory cell array based on the measured bit line setup-times measured at each ISPP program loop.
摘要翻译：一种包括存储单元阵列的非易失性存储器件; 读/写电路，被配置为根据要编程的数据以负位线电压驱动存储单元阵列的位线; 位线建立时间测量电路，被配置为在每个ISPP程序循环中测量位线建立时间，其可以是要编程的数据量的函数; 以及控制逻辑，被配置为基于在每个ISPP程序循环中测量的测量位线建立时间来控制施加到存储器单元阵列的选定字线的编程电压的施加时间和/或施加时间。

16. 发明申请

US20110231856A1 System and method for dynamically managing tasks for data parallel processing on multi-core system 有权
标题翻译：用于动态管理多核系统数据并行处理任务的系统和方法
公开(公告)号：US20110231856A1
公开(公告)日：2011-09-22
申请号：US12923793
申请日：2010-10-07
申请人： Min Young Son , Shi Hwa Lee , Seung Won Lee , Jeong Joon Yoo , Jae Don Lee , Young Sam Shin
发明人： Min Young Son , Shi Hwa Lee , Seung Won Lee , Jeong Joon Yoo , Jae Don Lee , Young Sam Shin
IPC分类号： G06F9/46
CPC分类号： G06F9/5088
摘要： A dynamic task management system and method for data parallel processing on a multi-core system are provided. The dynamic task management system may generate a registration signal for a task to be parallel processed, may generate a dynamic management signal used to dynamically manage at least one task, in response to the generated registration signal, and may control the at least one task to be created or cancelled in at least one core in response to the generated dynamic management signal.
摘要翻译：提供了一种用于多核系统上数据并行处理的动态任务管理系统和方法。动态任务管理系统可以生成用于待并行处理的任务的注册信号，可以响应于所生成的注册信号而生成用于动态管理至少一个任务的动态管理信号，并且可以将至少一个任务控制为响应于所生成的动态管理信号在至少一个核心中创建或取消。

17. 发明申请

US20110225351A1 MEMORY CARD AND MEMORY SYSTEM HAVING THE SAME 审中-公开
标题翻译：存储卡和存储器系统
公开(公告)号：US20110225351A1
公开(公告)日：2011-09-15
申请号：US13111489
申请日：2011-05-19
申请人： Ki-Hong Kim , Byeong-Hoon Lee , Seung-Won Lee , Sun-Kwon Kim
发明人： Ki-Hong Kim , Byeong-Hoon Lee , Seung-Won Lee , Sun-Kwon Kim
IPC分类号： G06F12/00
CPC分类号： G11C16/20
摘要： A memory card includes: a first memory chip responding to all commands input externally; and a second memory chip responding to commands, among the commands input externally, relevant to reading, programming, and erasing operations with data. Card identification information stored in the first memory chip includes capacity information corresponding to a sum of sizes of the first and second memory chips. The plurality of memory chips of the memory card are useful in designing the memory card with storage capacity in various forms.
摘要翻译：存储卡包括：响应于外部输入的所有命令的第一存储器芯片; 以及响应命令的第二存储器芯片，在外部输入的命令中与数据的读取，编程和擦除操作相关。存储在第一存储器芯片中的卡识别信息包括对应于第一和第二存储器芯片的尺寸之和的容量信息。存储卡的多个存储芯片可用于以各种形式设计具有存储容量的存储卡。

18. 发明申请

US20110119463A1 COMPUTING SYSTEM AND METHOD CONTROLLING MEMORY OF COMPUTING SYSTEM 有权
标题翻译：计算机系统和控制计算机存储器的方法
公开(公告)号：US20110119463A1
公开(公告)日：2011-05-19
申请号：US12881752
申请日：2010-09-14
申请人： Jae Don Lee , Shi Hwa Lee , Seung Won Lee , Chae Seok Lim , Min Kyu Jeong
发明人： Jae Don Lee , Shi Hwa Lee , Seung Won Lee , Chae Seok Lim , Min Kyu Jeong
IPC分类号： G06F12/02
CPC分类号： G06F9/5016
摘要： Provided is a computing system having a hierarchical memory structure. When a data structure is allocated with respect to a task processed in the computing system, the data structure is divided and a portion of the data structure is allocated to a high speed memory of the hierarchical memory structure and a remaining data structure is allocated to a low speed memory of the hierarchical memory.
摘要翻译：提供了具有分层存储器结构的计算系统。当相对于在计算系统中处理的任务分配数据结构时，数据结构被划分，并且数据结构的一部分被分配给分层存储器结构的高速存储器，并且剩余的数据结构被分配给分层存储器的低速存储器。

19. 发明申请

US20110072231A1 Device, method and computer-readable medium relocating remote procedure call data in heterogeneous multiprocessor system on chip 有权
标题翻译：在异构多处理器系统芯片中重新定位远程过程调用数据的设备，方法和计算机可读介质
公开(公告)号：US20110072231A1
公开(公告)日：2011-03-24
申请号：US12923408
申请日：2010-09-20
申请人： Seung Won Lee , Young Sam Shin , Shi Hwa Lee
发明人： Seung Won Lee , Young Sam Shin , Shi Hwa Lee
IPC分类号： G06F12/02
CPC分类号： G06F9/547
摘要： Disclosed is a device, method and computer-readable medium relocating Remote Procedure Call (RPC) data in a heterogeneous multiprocessor System-on-Chip (MPSoC). The method, for example, includes determining a memory where data is to be stored based on a use of a parameter of a function, and data access patterns of a function caller and a function callee, and storing the data in the determined memory.
摘要翻译：公开了一种在异构多处理器片上系统（MPSoC）中重新定位远程过程调用（RPC）数据的设备，方法和计算机可读介质。该方法例如包括基于使用功能的参数以及函数调用者和函数被调用者的数据访问模式来确定要存储数据的存储器，并将数据存储在所确定的存储器中。

20. 发明授权

US07889555B2 Flash memory system capable of operating in a random access mode and data reading method thereof 有权
标题翻译：能够以随机存取模式操作的闪存系统及其数据读取方法
公开(公告)号：US07889555B2
公开(公告)日：2011-02-15
申请号：US11764613
申请日：2007-06-18
申请人： Byeong-Hoon Lee , Ki-Hong Kim , Seung-Won Lee , Sun-Kwon Kim
发明人： Byeong-Hoon Lee , Ki-Hong Kim , Seung-Won Lee , Sun-Kwon Kim
IPC分类号： G11C16/04
CPC分类号： G11C16/0483
摘要： A memory system includes a memory and a memory controller operating to control the memory. The memory includes a random accessible memory including a memory cell array operable in a random access mode, a NAND flash memory, and a selection circuit making the memory controller operate either one of the random accessible memory or the NAND flash memory.
摘要翻译：存储器系统包括操作以控制存储器的存储器和存储器控制器。存储器包括随机存取存储器，其包括以随机存取模式操作的存储单元阵列，NAND闪速存储器和使存储器控制器操作随机存取存储器或NAND闪速存储器之一的选择电路。

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