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11. 发明授权

US06853584B2 Circuit for compensating programming current required, depending upon programming state 有权
标题翻译：根据编程状态，补偿编程电流所需的电路
公开(公告)号：US06853584B2
公开(公告)日：2005-02-08
申请号：US10428742
申请日：2003-05-02
申请人： Hung Q. Nguyen , Sang Thanh Nguyen , Elbert Lin , Anh Ly
发明人： Hung Q. Nguyen , Sang Thanh Nguyen , Elbert Lin , Anh Ly
IPC分类号： G11C5/14 , G11C11/34 , G11C16/06 , G11C16/30
CPC分类号： G11C16/30 , G11C5/147
摘要： A non-volatile memory semiconductor device has a circuit to compensate for the variation in the data pattern to be programmed. The variation in the data patter creates a variation in the current requirement. The array receives a plurality of data pattern signals which affect the total amount of current flowing into a plurality of columns and into the memory array. A high voltage source generates an output which is supplied along a conducting path connected to the group of columns. A pass transistor is in the conducting path controlling the current flow in the conducting path. A current source has a first terminal and a second terminal with the first terminal connected to the output of the high voltage generator and the second terminal connected to the gate of the pass transistor. A plurality of current sources are collectively connected to a node. Each of the plurality of current sources receives a plurality of second signals with each second signal being an inverse of the first signal, and controlling the total amount of current flowing through the node. A current mirror circuit is connected to the node and to the gate of the pass transistor and controls the pass transistor in response to the amount of current flowing through the node.
摘要翻译：非易失性存储器半导体器件具有用于补偿要编程的数据模式的变化的电路。数据模式的变化会导致当前需求的变化。阵列接收多个数据模式信号，这些数据模式信号影响流入多个列的电流的总量并进入存储器阵列。高电压源产生沿着连接到一组列的导电路径提供的输出。传导晶体管处于控制导电路径中的电流的导电路径中。电流源具有第一端子和第二端子，其第一端子连接到高电压发生器的输出端，第二端子连接到传输晶体管的栅极。多个电流源共同连接到节点。多个电流源中的每一个接收多个第二信号，其中每个第二信号是第一信号的倒数，并且控制流过节点的总电流量。电流镜电路连接到节点和传输晶体管的栅极，并根据流过节点的电流量来控制传输晶体管。

12. 发明授权

US08674749B2 Fast start charge pump for voltage regulators 有权
标题翻译：用于稳压器的快速启动电荷泵
公开(公告)号：US08674749B2
公开(公告)日：2014-03-18
申请号：US12726249
申请日：2010-03-17
申请人： Hieu Van Tran , Sang Thanh Nguyen , Anh Ly , Hung Q. Nguyen , Wingfu AAron Lau , Nasrin Jaffari , Thuan Trong Vu , Vishal Sarin , Loc B. Hoang
发明人： Hieu Van Tran , Sang Thanh Nguyen , Anh Ly , Hung Q. Nguyen , Wingfu AAron Lau , Nasrin Jaffari , Thuan Trong Vu , Vishal Sarin , Loc B. Hoang
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： H02M3/07 , H02M1/36 , H02M1/44
摘要： A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping.
摘要翻译：数字多电平存储器系统包括电荷泵和用于产生用于各种存储器操作的调节高电压的电压调节器。电荷泵可以包括多个升压电路，以在快速启动期间升高电荷泵的输出。之后，升压电路被禁止，使电荷泵产生高电压而不加速。升压电路可以被连续地使能以升高电压。升压电路可以是无负载的。电压调节器可以在开环中工作，并且可以包括电阻分压器作为用于调节来自电荷泵的高电压的参考电压。电荷泵可以包括扩频泵时钟，以减少用于电容器或电感器片上电荷泵浦的电磁推理。

13. 发明申请

US20130187707A1 Charge Pump Systems and Methods 有权
标题翻译：电荷泵系统和方法
公开(公告)号：US20130187707A1
公开(公告)日：2013-07-25
申请号：US13726522
申请日：2012-12-24
申请人： Hieu Van Tran , Sang Thanh Nguyen , Nasrin Jaffari , Hung Quoc Nguyen , Anh Ly
发明人： Hieu Van Tran , Sang Thanh Nguyen , Nasrin Jaffari , Hung Quoc Nguyen , Anh Ly
IPC分类号： G05F3/02
CPC分类号： G05F3/02 , H02M3/073 , H02M2001/322
摘要： Digital multilevel memory systems and methods include a charge pump for generating regulated high voltages for various memory operations. The charge pump may include a plurality of pump stages. Aspects of exemplary systems may include charge pumps that performs orderly charging and discharging at low voltage operation conditions. Additional aspects may include features that enable state by state pumping, for example, circuitry that avoids cascaded short circuits among pump stages. Each pump stage may also include circuitry that discharges its nodes, such as via self-discharge through associated pump interconnection(s). Further aspects may also include features that: assist power-up in the various pump stages, double voltage, shift high voltage levels, provide anti-parallel circuit configurations, and/or enable buffering or precharging features, such as self-buffering and self-precharging circuitry.
摘要翻译：数字多电平存储器系统和方法包括用于为各种存储器操作产生调节的高电压的电荷泵。电荷泵可以包括多个泵级。示例性系统的方面可以包括在低电压操作条件下执行有序充电和放电的电荷泵。其他方面可以包括使状态状态泵送的特征，例如避免泵级之间的级联短路的电路。每个泵级还可以包括排放其节点的电路，例如通过相关联的泵互连通过自放电。另外的方面还可以包括以下功能：辅助各个泵级的上电，双电压，高电平移位，提供反并联电路配置和/或实现缓冲或预充电特征，例如自缓冲和自缓冲，预充电电路。

14. 发明授权

US08270213B2 Flash memory array system including a top gate memory cell 有权
标题翻译：包括顶栅存储单元的闪存阵列系统
公开(公告)号：US08270213B2
公开(公告)日：2012-09-18
申请号：US12962343
申请日：2010-12-07
申请人： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Thanh Nguyen , Loc B. Hoang , Steve Choi , Thuan T. Vu
发明人： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Thanh Nguyen , Loc B. Hoang , Steve Choi , Thuan T. Vu
IPC分类号： G11C16/12
CPC分类号： G11C8/10 , G11C16/0433 , G11C16/08 , G11C29/832
摘要： A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.
摘要翻译：存储器系统包括布置在扇区中的存储器单元。对应于扇区的解码器禁止具有缺陷顶门的存储单元。解码器可以包括用于禁用的低电压或高电压锁存器。包括顶栅处理算法。存储器系统可以包括动态顶栅耦合。包括具有顶栅处理的编程算法和波形。

15. 发明授权

US08020055B2 Method and apparatus for testing the connectivity of a flash memory chip 有权
标题翻译：用于测试闪存芯片连接性的方法和装置
公开(公告)号：US08020055B2
公开(公告)日：2011-09-13
申请号：US12629302
申请日：2009-12-02
申请人： Sang Thanh Nguyen , Hieu Van Tran , Hung O. Nguyen , Phil Klotzkin
发明人： Sang Thanh Nguyen , Hieu Van Tran , Hung O. Nguyen , Phil Klotzkin
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/02 , G11C29/022 , G11C2029/3202
摘要： In one embodiment of the invention, circuitry and hardware for connectivity testing are fabricated on an IC, and in particular an IC containing a flash memory array. This testing circuitry is electrically connected to the bond pads of the IC. In some embodiments, the testing circuitry includes a boundary scan cell connected to each bond pad, allowing for rapid connectivity testing of flash memory chips in accordance with testing standards such as the JTAG standard. The invention further includes methods in which the pins and/or memory cells of a flash memory chip are sequentially sent a series of data so as to test the connectivity of portions of the IC. The sequentially-sent data is then retrieved and compared to the original data. Discrepancies between these sets of data thus highlight connectivity problems in the IC.
摘要翻译：在本发明的一个实施例中，用于连接测试的电路和硬件被制造在IC上，特别是包含闪存阵列的IC。该测试电路电连接到IC的接合焊盘。在一些实施例中，测试电路包括连接到每个接合焊盘的边界扫描单元，允许根据诸如JTAG标准的测试标准对闪存芯片进行快速连接测试。本发明还包括其中闪存芯片的引脚和/或存储单元被顺序发送一系列数据以测试IC的部分连通性的方法。然后检索顺序发送的数据并将其与原始数据进行比较。因此，这些数据集之间的差异突出了IC中的连接问题。

16. 发明授权

US07778080B2 Flash memory array system including a top gate memory cell 有权
公开(公告)号：US07778080B2
公开(公告)日：2010-08-17
申请号：US12200930
申请日：2008-08-28
申请人： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Thanh Nguyen , Loc B. Hoang , Steve Choi , Thuan T. Vu
发明人： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Thanh Nguyen , Loc B. Hoang , Steve Choi , Thuan T. Vu
IPC分类号： G11C16/34
CPC分类号： G11C8/10 , G11C16/0433 , G11C16/08 , G11C29/832
摘要： A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.

17. 发明申请

US20100001765A1 SENSE AMPLIFIER FOR LOW VOLTAGE HIGH SPEED SENSING 有权
标题翻译：用于低电压高速感应的感应放大器
公开(公告)号：US20100001765A1
公开(公告)日：2010-01-07
申请号：US12493240
申请日：2009-06-28
申请人： Hieu Van Tran , Sang Thanh Nguyen , Hung Quoc Nguyen
发明人： Hieu Van Tran , Sang Thanh Nguyen , Hung Quoc Nguyen
IPC分类号： H03F3/45 , G01R19/00
CPC分类号： G11C11/5642 , G11C7/06 , G11C7/062
摘要： A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to the low impedance circuit and a reference voltage node. A second input of the comparator is coupled to a data voltage node. The first load circuit loads a reference cell coupled to the reference voltage node. The second load circuit loads a data cell coupled to the data voltage node.
摘要翻译：存储器系统包括用于通过与存储在参考单元中的电压进行比较来检测数据存储单元的内容的读出放大器。读出放大器可以包括比较器，第一和第二负载电路以及低阻抗电路。比较器的第一输入耦合到低阻抗电路和参考电压节点。比较器的第二输入耦合到数据电压节点。第一负载电路加载耦合到参考电压节点的参考电池。第二负载电路加载耦合到数据电压节点的数据单元。

18. 发明申请

US20080290931A1 Charge pump systems and methods 有权
标题翻译：电荷泵系统和方法
公开(公告)号：US20080290931A1
公开(公告)日：2008-11-27
申请号：US11805765
申请日：2007-05-23
申请人： Hieu Van Tran , Sang Thanh Nguyen , Nasrin Jaffari , Hung Quoc Nguyen , Anh Ly
发明人： Hieu Van Tran , Sang Thanh Nguyen , Nasrin Jaffari , Hung Quoc Nguyen , Anh Ly
IPC分类号： G05F1/10
CPC分类号： G05F3/02 , H02M3/073 , H02M2001/322
摘要： Digital multilevel memory systems and methods include a charge pump for generating regulated high voltages for various memory operations. The charge pump may include a plurality of pump stages. Aspects of exemplary systems may include charge pumps that performs orderly charging and discharging at low voltage operation conditions. Additional aspects may include features that enable state by state pumping, for example, circuitry that avoids cascaded short circuits among pump stages. Each pump stage may also include circuitry that discharges its nodes, such as via self-discharge through associated pump interconnection(s). Further aspects may also include features that: assist power-up in the various pump stages, double voltage, shift high voltage levels, provide anti-parallel circuit configurations, and/or enable buffering or precharging features, such as self-buffering and self-precharging circuitry.
摘要翻译：数字多电平存储器系统和方法包括用于为各种存储器操作产生调节的高电压的电荷泵。电荷泵可以包括多个泵级。示例性系统的方面可以包括在低电压操作条件下执行有序充电和放电的电荷泵。其他方面可以包括使状态状态泵送的特征，例如避免泵级之间的级联短路的电路。每个泵级还可以包括排放其节点的电路，例如通过相关联的泵互连通过自放电。另外的方面还可以包括以下功能：辅助各个泵级的上电，双电压，高电平移位，提供反并联电路配置和/或实现缓冲或预充电特征，例如自缓冲和自缓冲，预充电电路。

19. 发明授权

US07263005B2 Method of programming a non-volatile memory cell by controlling the channel current during the rise period 有权
标题翻译：通过在上升期间控制通道电流来对非易失性存储单元进行编程的方法
公开(公告)号：US07263005B2
公开(公告)日：2007-08-28
申请号：US11487135
申请日：2006-07-14
申请人： Alexander Kotov , Yuniarto Widjaja , Tho Ngoc Dang , Hung Q. Nguyen , Sang Thanh Nguyen
发明人： Alexander Kotov , Yuniarto Widjaja , Tho Ngoc Dang , Hung Q. Nguyen , Sang Thanh Nguyen
IPC分类号： G11C16/04
CPC分类号： G11C16/12
摘要： A method to eliminate program deceleration and to enhance the resistance to program disturbance of a non-volatile floating gate memory cell is disclosed. This method eliminates or minimizes the impact of the hole displacement current. This can be done, for example, by increasing the rise time of the high programming voltage applied to the high voltage terminal. Alternatively, the transistor of the non-volatile floating gate memory cell can be turned off until the voltage applied to the high voltage terminal has reached the programming voltage. This can be done, for example by delaying the voltage applied to either the low voltage terminal or to the control gate to turn on the transistor until the voltage at the high voltage terminal has past the ramp up voltage and has reached a level programming voltage.
摘要翻译：公开了一种消除程序减速并增强对非易失性浮动栅极存储单元的编程干扰的阻力的方法。该方法消除或最小化孔位移电流的影响。这可以通过例如增加施加到高电压端子的高编程电压的上升时间来实现。或者，非易失性浮栅存储单元的晶体管可以被截止，直到施加到高电压端子的电压达到编程电压。这可以通过例如通过延迟施加到低电压端子或控制栅极的电压来导通晶体管，直到高压端子处的电压已经超过斜坡上升电压并达到电平编程电压。

20. 发明授权

US06788595B2 Embedded recall apparatus and method in nonvolatile memory 有权
标题翻译：非易失性存储器中的嵌入式调用装置和方法
公开(公告)号：US06788595B2
公开(公告)日：2004-09-07
申请号：US10213243
申请日：2002-08-05
申请人： Hung Q. Nguyen , Sang Thanh Nguyen , Loc B. Hoang , Tam M. Nguyen
发明人： Hung Q. Nguyen , Sang Thanh Nguyen , Loc B. Hoang , Tam M. Nguyen
IPC分类号： G11C700
CPC分类号： G11C29/70 , G11C29/38 , G11C2029/0407
摘要： Predetermined data is stored in first and second predetermined locations of a memory. The first location may be in a first part of the memory, and the second location may be in a redundant part of the memory. At power up or reset, the first predetermined location of the memory successively is read and compared to data stored in a register until the comparison indicates a match for a predefined number of consecutive reads and comparisons. The successive reading may be stopped if the number of comparisons indicating a failure equals another predefined number of times. The data stored in the second predetermined location also is read. This data may be compared to the data previously read from the second predetermined location. The reading and comparing from the first predetermined location and the reading from the second predetermined location are continued until the number of times data is read from the second predetermined location equals a third predetermined number. The voltage signal is then determined to be valid after sufficient successive reads of the first predetermined location of the memory.
摘要翻译：预定数据存储在存储器的第一和第二预定位置中。第一位置可以在存储器的第一部分中，并且第二位置可以在存储器的冗余部分中。在上电或复位时，存储器的第一预定位置连续被读取并与存储在寄存器中的数据进行比较，直到比较指示对于预定数量的连续读取和比较的匹配。如果指示故障的比较数等于另一预定义次数，则可能停止连续读取。存储在第二预定位置的数据也被读取。该数据可以与先前从第二预定位置读取的数据进行比较。继续从第一预定位置读取和比较第二预定位置的读数，直到从第二预定位置读取数据等于第三预定数目的次数。然后在充分连续读取存储器的第一预定位置之后，将电压信号确定为有效。

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