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11. 发明申请

WO2012121968A2 LOGICAL ADDRESS TRANSLATION 审中-公开
标题翻译：逻辑地址翻译
公开(公告)号：WO2012121968A2
公开(公告)日：2012-09-13
申请号：PCT/US2012027265
申请日：2012-03-01
申请人： MICRON TECHNOLOGY INC , CULLEY MARTIN L , MANNING TROY A , LARSEN TROY D
发明人： CULLEY MARTIN L , MANNING TROY A , LARSEN TROY D
IPC分类号： G06F12/02 , G06F13/14
CPC分类号： G06F3/0665 , G06F12/00 , G06F12/0246 , G06F12/0292 , G06F12/04 , G06F12/10 , G06F12/1027 , G06F12/1408 , G06F12/1475 , G06F2212/7201 , G06F2212/7202 , Y02B60/1225 , Y02D10/13
摘要： The present disclosure includes methods for logical address translation, methods for operating memory systems, and memory systems. One such method includes receiving a command associated with a LA, wherein the LA is in a particular range of LAs and translating the LA to a physical location in memory using an offset corresponding to a number of physical locations skipped when writing data associated with a range of LAs other than the particular range.
摘要翻译：本公开包括用于逻辑地址转换的方法，用于操作存储器系统的方法和存储器系统。一种这样的方法包括接收与LA相关联的命令，其中LA在LAs的特定范围内，并且使用对应于当写入与范围相关联的数据时跳过的物理位置的数量来将LA转换到存储器中的物理位置的特定范围以外的。

12. 发明申请

WO2010042496A3 STACKED DEVICE REMAPPING AND REPAIR 审中-公开
标题翻译：堆叠设备重新修复和维修
公开(公告)号：WO2010042496A3
公开(公告)日：2010-07-22
申请号：PCT/US2009059669
申请日：2009-10-06
申请人： MICRON TECHNOLOGY INC , KEETH BRENT , MARTIN CHRIS G , MANNING TROY A , JEDDELOH JOE M , COWLES TIMOTHY B , REHMEYER JIM , LABERGE PAUL A
发明人： KEETH BRENT , MARTIN CHRIS G , MANNING TROY A , JEDDELOH JOE M , COWLES TIMOTHY B , REHMEYER JIM , LABERGE PAUL A
IPC分类号： G11C8/04 , G11C8/06
CPC分类号： G06F12/08 , G06F12/10 , G11C5/025 , G11C29/04 , G11C29/18 , G11C29/76 , G11C29/78 , G11C29/808 , G11C29/812 , G11C29/883 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/17181 , H01L2924/00014 , H01L2924/15311 , H01L2224/05599
摘要： Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die.
摘要翻译：各种实施例包括具有布置在堆叠中的多个骰子的装置，系统和方法，其中有缺陷的单元可以被同一裸片上的备用单元或不同的管芯替代。

13. 发明申请

WO2010042496A2 STACKED DEVICE REMAPPING AND REPAIR 审中-公开
标题翻译：堆叠设备重新包装和维修
公开(公告)号：WO2010042496A2
公开(公告)日：2010-04-15
申请号：PCT/US2009/059669
申请日：2009-10-06
申请人： MICRON TECHNOLOGY, INC. , KEETH, Brent , MARTIN, Chris G. , MANNING, Troy A. , JEDDELOH, Joe M. , COWLES, Timothy B. , REHMEYER, Jim , LABERGE, Paul A.
发明人： KEETH, Brent , MARTIN, Chris G. , MANNING, Troy A. , JEDDELOH, Joe M. , COWLES, Timothy B. , REHMEYER, Jim , LABERGE, Paul A.
IPC分类号： G11C8/04 , G11C8/06
CPC分类号： G06F12/08 , G06F12/10 , G11C5/025 , G11C29/04 , G11C29/18 , G11C29/76 , G11C29/78 , G11C29/808 , G11C29/812 , G11C29/883 , H01L2224/0554 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/17181 , H01L2924/00014 , H01L2924/15311 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die.
摘要翻译：各种实施例包括具有以堆叠方式布置的多个管芯的设备，系统和方法，其中有缺陷的单元可以被同一管芯或不同管芯上的备用单元替换。

14. 发明申请

WO2004001846A2 METHOD AND STRUCTURES FOR REDUCED PARASITIC CAPACITANCE IN INTEGRATED CIRCUIT METALLIZATIONS 审中-公开
标题翻译：集成电路金属化中降低PARASIIC电容的方法与结构
公开(公告)号：WO2004001846A2
公开(公告)日：2003-12-31
申请号：PCT/US2003/021029
申请日：2003-06-18
申请人： MICRON TECHNOLOGY, INC. , BATRA, Shubneesh , CHAINE, Michael, D. , KEETH, Brent , AKRAM, Salman , MANNING, Troy, A. , JOHNSON, Brian , MARTIN, Chris, G. , MERRITT, Todd, A. , SMITH, Eric, J.
发明人： BATRA, Shubneesh , CHAINE, Michael, D. , KEETH, Brent , AKRAM, Salman , MANNING, Troy, A. , JOHNSON, Brian , MARTIN, Chris, G. , MERRITT, Todd, A. , SMITH, Eric, J.
IPC分类号： H01L23/485
CPC分类号： H01L24/05 , H01L23/5222 , H01L24/03 , H01L2224/05093 , H01L2224/05095 , H01L2224/05096 , H01L2224/05556 , H01L2224/05624 , H01L2224/05647 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/0102 , H01L2924/01029 , H01L2924/01033 , H01L2924/01041 , H01L2924/01061 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/30105
摘要： A method of reducing parasitic capacitance in an integrated circuit having three or more metal levels (M1, M2, M3, etc) is described. The method comprises forming a bond pad (20) at least partially exposed at the top surface of the integrated circuit, forming a metal pad (22) on the metal level (42) below the bond pad (20) and forming an underlying metal pad (26b) on each of the one or more lower metal levels. In the illustrated embodiments, the ratio of an area of at least one of the underlying metal pads (22, 26b) to the area of the bond pad (20) is less than 30%. Parasitic capacitance is thus greatly reduced and signal propagation speeds improved.
摘要翻译：描述了一种降低具有三个或更多个金属水平（M1，M2，M3等）的集成电路中的寄生电容的方法。该方法包括形成至少部分地暴露在集成电路的顶表面处的接合焊盘（20），在接合焊盘（20）下方的金属层（42）上形成金属焊盘（22），并形成下面的金属焊盘（26b）在所述一个或多个下层金属层中的每一个上。在所示实施例中，下面的金属焊盘（22,26b）中的至少一个的面积与焊盘（20）的面积之比小于30％。寄生电容因此大大降低，信号传播速度提高。

15. 发明申请

WO2012094481A3 MEMORY ADDRESS TRANSLATION 审中-公开
标题翻译：存储地址翻译
公开(公告)号：WO2012094481A3
公开(公告)日：2012-09-20
申请号：PCT/US2012020312
申请日：2012-01-05
申请人： MICRON TECHNOLOGY INC , MANNING TROY A , CULLEY MARTIN L , LARSEN TROY D
发明人： MANNING TROY A , CULLEY MARTIN L , LARSEN TROY D
IPC分类号： G06F12/06 , G06F12/10
CPC分类号： G06F12/1045 , G06F12/0246 , G06F12/0292 , G06F12/1009 , G06F12/1027 , G06F2212/1004 , G06F2212/7201 , Y02B60/1225 , Y02D10/13
摘要： The present disclosure includes devices, systems, and methods for memory address translation. One or more embodiments include a memory array and a controller coupled to the array. The array includes a first table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a data segment stored in the array and a logical address. The controller includes a second table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the first table and a logical address. The controller also includes a third table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the second table and a logical address.
摘要翻译：本公开包括用于存储器地址转换的装置，系统和方法。一个或多个实施例包括存储器阵列和耦合到阵列的控制器。阵列包括具有多个记录的第一表，其中每个记录包括多个条目，其中每个条目包括对应于阵列中存储的数据段的物理地址和逻辑地址。控制器包括具有多个记录的第二表，其中每个记录包括多个条目，其中每个条目包括对应于第一表中的记录的物理地址和逻辑地址。控制器还包括具有多个记录的第三表，其中每个记录包括多个条目，其中每个条目包括对应于第二表中的记录的物理地址和逻辑地址。

16. 发明申请

WO2010016879A8 ROW MASK ADDRESSING 审中-公开
公开(公告)号：WO2010016879A8
公开(公告)日：2010-09-16
申请号：PCT/US2009004443
申请日：2009-08-03
申请人： MICRON TECHNOLOGY INC , MANNING TROY A
发明人： MANNING TROY A
IPC分类号： G11C8/00 , G11C8/08 , G11C8/10 , G11C8/18
CPC分类号： G11C8/10 , G11C11/4087
摘要： Electronic apparatus, systems, and methods may operate structures to access a portion of a row of a memory array without accessing the entire row. Additional apparatus, systems, and methods are disclosed.
摘要翻译：电子设备，系统和方法可以操作结构以访问存储器阵列的一部分行而不访问整个行。公开了另外的设备，系统和方法。

17. 发明申请

WO2005073974A1 MEMORY DEVICE HAVING MULTIPLE-FUNCTION STROBE TERMINALS 审中-公开
标题翻译：具有多功能结构端子的存储器件
公开(公告)号：WO2005073974A1
公开(公告)日：2005-08-11
申请号：PCT/US2005/000809
申请日：2005-01-11
申请人： MICRON TECHNOLOGY, INC. , CHOI, Joo, S. , MANNING, Troy, A.
发明人： CHOI, Joo, S. , MANNING, Troy, A.
IPC分类号： G11C7/22
CPC分类号： G11C7/1078 , G11C7/1051 , G11C7/1063 , G11C7/1066 , G11C7/1072 , G11C7/109 , G11C7/1093 , G11C2207/2254
摘要： A memory device has data transceivers, write strobe transceivers, and read strobe transceivers. The data transceivers transfer input data to the memory device and transfer output data from the memory device. The write strobe transceivers transfer timing information of the input data. The read strobe transceivers transfer timing information of the output data. The memory device also has an auxiliary circuit for generating auxiliary information. The auxiliary information includes information different from the timing information of the input data and the output data. The auxiliary circuit uses the write and read transceivers to transfer the auxiliary information to and from the memory device.
摘要翻译：存储器件具有数据收发器，写选通收发器和读选通收发器。数据收发器将输入数据传输到存储器件并从存储器件传送输出数据。写入选通收发器传送输入数据的定时信息。读选通收发器传输输出数据的定时信息。存储装置还具有用于产生辅助信息的辅助电路。辅助信息包括与输入数据和输出数据的定时信息不同的信息。辅助电路使用写入和读取收发器将辅助信息传送到存储器件和从存储器件传送辅助信息。

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