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    • 11. 发明授权
    • Semiconductor integrated circuit for processing audio and video signals
    • 用于处理音视频信号的半导体集成电路
    • US07518431B2
    • 2009-04-14
    • US11232683
    • 2005-09-22
    • Taku KobayashiKeiichi Fujii
    • Taku KobayashiKeiichi Fujii
    • G05F1/10G05F3/02
    • H02M3/07
    • A semiconductor integrated circuit includes a charge pump circuit that repeats charge and discharge of a capacitor based on a clock signal when an ON/OFF control voltage is ON; a first delay circuit that delays the ON/OFF control voltage; a switch that shorts an output of the charge pump circuit and a GND input terminal when the delayed ON/OFF control voltage is OFF and opens when the delayed ON/OFF control voltage is ON; a first circuit block that is driven by a power voltage which is supplied from a power source input terminal and the charge pump circuit; and a second circuit block that is driven by a power voltage which is supplied from the power source input terminal and the GND input terminal. The first and second circuit blocks are mounted on the same semiconductor integrated circuit chip.
    • 半导体集成电路包括电荷泵电路,其在ON / OFF控制电压为ON时基于时钟信号重复电容器的充电和放电; 延迟ON / OFF控制电压的第一延迟电路; 当延迟的ON / OFF控制电压为OFF时,断开电荷泵电路的输出和GND输入端子的开关,当延迟的ON / OFF控制电压为ON时,该开关断开; 由从电源输入端子和电荷泵电路供给的电源电压驱动的第一电路块; 以及由从电源输入端子和GND输入端子提供的电源电压驱动的第二电路块。 第一和第二电路块安装在相同的半导体集成电路芯片上。
    • 13. 发明授权
    • Step-down voltage output circuit
    • 降压电压输出电路
    • US07307465B2
    • 2007-12-11
    • US10923848
    • 2004-08-24
    • Taku KobayashiKeiichi Fujii
    • Taku KobayashiKeiichi Fujii
    • G05F1/10
    • H02M3/07H02M2003/072
    • To provide a step-down voltage output circuit which causes no latch-up phenomenon for the period between activation of a power supply and complete start of operation of a charge pump circuit. The step-down voltage output circuit of the present invention has the charge pump circuit with a first oscillator; a timer circuit in which a timer period is set according to an oscillating frequency of the above-mentioned first oscillator; and an N-channel MOS transistor in which one N-type diffusion layer is connected to an output terminal of the above-mentioned charge pump circuit, the other N-type diffusion layer is connected to ground potential, and a gate electrode is connected to an output terminal of the above-mentioned timer circuit to become conductive for the above-mentioned timer period.
    • 提供降压电压输出电路,其在电源的激活和电荷泵电路的完全启动之间的期间不引起闩锁现象。 本发明的降压电压输出电路具有带有第一振荡器的电荷泵电路; 定时器电路,其中根据上述第一振荡器的振荡频率设置定时器周期; 以及N沟道MOS晶体管,其中一个N型扩散层连接到上述电荷泵电路的输出端,另一个N型扩散层连接到地电位,栅电极连接到 上述定时器电路的输出端子在上述定时器周期中变为导通。
    • 15. 发明申请
    • Semiconductor integrated circuit
    • 半导体集成电路
    • US20070024347A1
    • 2007-02-01
    • US11488503
    • 2006-07-18
    • Toshinobu NagasawaTetsushi ToyookaKeiichi Fujii
    • Toshinobu NagasawaTetsushi ToyookaKeiichi Fujii
    • G05F1/10
    • H02M3/07H02M1/36
    • A semiconductor integrated circuit includes a charge pump circuit for stepping down or stepping up a voltage supplied from a single voltage supply VDD and outputting the voltage, by repeating an operation of charging a flying capacitor C1 and transferring charges stored in the flying capacitor to a storage capacitor C2. During the operation of the charge pump circuit, current supply for charging the flying capacitor is carried out by a current mirror operation. The semiconductor integrated circuit thus obtained by including the charge pump circuit is characterized in that rush current on startup of charge pumping is reduced and that output performance of a DC-CD converter is not impaired.
    • 半导体集成电路包括电荷泵电路,用于通过重复对飞跨电容器C1进行充电的操作并将存储在飞行电容器中的电荷转移到一个电压源中,从而降低或升高从单个电压源VDD提供的电压并输出该电压 存储电容器C 2。 在充电泵电路的操作期间,通过电流反射镜操作来执行用于对飞跨电容器充电的电流源。 由此获得的包含电荷泵电路的半导体集成电路的特征在于,电荷泵浦启动时的冲击电流降低,DC-CD转换器的输出性能不受损害。
    • 16. 发明授权
    • AGC circuit
    • AGC电路
    • US07015759B2
    • 2006-03-21
    • US10899006
    • 2004-07-27
    • Takuma IshidaKeiichi Fujii
    • Takuma IshidaKeiichi Fujii
    • H03G3/10
    • H03G3/001H03G3/3026
    • An AGC circuit of the present invention includes a first up/down counter for converting the amount of change in an output voltage higher than a threshold voltage into a count value and controlling a gain of a variable gain amplifier circuit and a second up/down counter to which a reference clock having a lower frequency than that of a reference clock supplied to the first up/down counter is supplied. Count values of the first and second up/down counters are D/A-converted and then compared with each other by a voltage comparator. An up/down count of the first up/down counter is controlled based on a comparison result and the gain of the variable gain amplifier circuit is controlled using only a signal based on the count value of the first up/down counter, thereby suppressing distortion of an output waveform and the generation of a frequency signal which is not originally input.
    • 本发明的AGC电路包括:第一上/下计数器,用于将高于阈值电压的输出电压的变化量转换成计数值,并控制可变增益放大器电路和第二上/下计数器的增益 提供具有比提供给第一向上/向下计数器的参考时钟低的参考时钟的参考时钟。 第一和第二上/下计数器的计数值进行D / A转换,然后通过电压比较器进行比较。 基于比较结果控制第一向上/向下计数器的向上/向下计数,并且仅使用基于第一向上/向下计数器的计数值的信号来控制可变增益放大器电路的增益,由此抑制失真 的输出波形和不是最初输入的频率信号的产生。
    • 17. 发明授权
    • AGC circuit
    • AGC电路
    • US06977550B2
    • 2005-12-20
    • US10713274
    • 2003-11-17
    • Takuma IshidaTaku KobayashiKeiichi Fujii
    • Takuma IshidaTaku KobayashiKeiichi Fujii
    • H03G3/20H03G3/30
    • H03G3/3036
    • An AGC circuit, which does not require any signal integration circuit comprised of a capacitor and a resistor, is provided. To achieve the above object, when amplifying or attenuating input signal by a variable gain control circuit controlled by the gain control voltage, output signal of the variable gain amplifier circuit is rectified by a rectification circuit, the output signal of the rectification circuit is compared to an arbitrary set voltage by a voltage comparator. The up-count operation and the down-count operation of the up/down counter is controlled to changeover by the output signal of the voltage comparator, and a voltage corresponding to the count value of the up/down counter is output from the D/A conversion circuit. Thus, gain control voltage corresponding to the voltage output from the D/A conversion circuit is supplied to the variable gain amplifier circuit.
    • 提供了不需要由电容器和电阻器组成的任何信号积分电路的AGC电路。 为了实现上述目的,当通过由增益控制电压控制的可变增益控制电路放大或衰减输入信号时,可变增益放大器电路的输出信号由整流电路整流,将整流电路的输出信号与 通过电压比较器的任意设定电压。 上升计数器的递增计数操作和递减计数操作被控制以通过电压比较器的输出信号切换,并且与D / D计数器的计数值对应的电压从D / A转换电路。 因此,与D / A转换电路输出的电压相对应的增益控制电压被提供给可变增益放大器电路。
    • 19. 发明申请
    • Enclosure and substrate structure for a tuner module
    • 调谐器模块的外壳和基板结构
    • US20050017830A1
    • 2005-01-27
    • US10852590
    • 2004-05-23
    • Kazunori OkuiHiroshi OgasawaraTakatsugu KamataKeiichi FujiiChristopher Li
    • Kazunori OkuiHiroshi OgasawaraTakatsugu KamataKeiichi FujiiChristopher Li
    • H03J1/00H03J3/00H05K1/02
    • H03J1/00H05K1/0218
    • A tuner module comprising a tuner and a tuner enclosure. The tuner includes a substrate containing filter coils and the tuner enclosure includes at least one partition plate placed between filter coils of the tuner to improve the isolation between the filter coils. The substrate may also contain plated through holes placed beneath a partition plate which further improves isolation between the filter coils. In some embodiments, the substrate is comprised of a coil layer having a planar coil, a shield layer, and a dielectric layer. The dielectric layer is placed between the coil and shield layers and provides a distance between the two layers to achieve a particular quality factor level of the planar coil. In some embodiments, the tuner enclosure further includes a shielding case that extends to the base of the substrate, is comprised of a metal material, and is mechanically connected with the substrate.
    • 一种调谐器模块,包括调谐器和调谐器外壳。 调谐器包括含有滤波器线圈的基板,调谐器外壳包括放置在调谐器的滤波器线圈之间的至少一个分隔板,以改善滤波器线圈之间的隔离。 衬底还可以包含设置在隔板下方的电镀通孔,这进一步改善了过滤器线圈之间的隔离。 在一些实施例中,衬底由具有平面线圈,屏蔽层和电介质层的线圈层组成。 电介质层被放置在线圈和屏蔽层之间,并且提供两层之间的距离以实现平面线圈的特定质量因子水平。 在一些实施例中,调谐器外壳还包括延伸到基底的屏蔽壳体,由金属材料构成,并且与基底机械连接。