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11. 发明申请

US20070033481A1 Decoding device and decoding method and program 失效
标题翻译：解码设备和解码方法及程序
公开(公告)号：US20070033481A1
公开(公告)日：2007-02-08
申请号：US11476679
申请日：2006-06-29
申请人： Katsutoshi Seki
发明人： Katsutoshi Seki
IPC分类号： H03M13/00
CPC分类号： H03M13/11
摘要： To provide an LDPC decoder, to which SPA is applied, and a method wherein decoding characteristics are improved by reducing the ratio of a message from a check node within messages sent to the same check node. In a decoding device that decodes a received LDPC code by repeating the passing of messages between a plurality of check nodes and a plurality of bit nodes corresponding to a check matrix in each iteration, the order of message computation at a cluster in an iteration out of at least two iterations that have a before-and-after relationship in time and the order of message computation at a cluster in another iteration are varied.
摘要翻译：为了提供应用了SPA的LDPC解码器以及通过减少发送到同一校验节点的消息内的来自校验节点的消息的比率来改进解码特性的方法。在解码装置中，通过重复在多个校验节点之间的消息和与每次迭代中的校验矩阵相对应的多个比特节点之间的消息来解码所接收的LDPC码，将迭代中的簇处的消息计算顺序排除在时间上具有前后关系的至少两次迭代和在另一次迭代中的群集处的消息计算的顺序是变化的。

12. 发明授权

US06924754B2 Iterative decoding method and iterative decoding apparatus 有权
标题翻译：迭代解码方法和迭代解码装置
公开(公告)号：US06924754B2
公开(公告)日：2005-08-02
申请号：US10732215
申请日：2003-12-11
申请人： Katsutoshi Seki
发明人： Katsutoshi Seki
IPC分类号： G06F11/10 , H03M13/29 , H03M13/35 , H04L1/00 , H03M13/00
CPC分类号： H03M13/6502 , H03M13/29 , H03M13/2909 , H03M13/2948 , H03M13/37
摘要： A first stage inner code decoder performs a first error correction process for a plurality of inner code words. A first stage outer code decoder performs a second error correction process for a plurality of outer code words. A second stage inner code decoder performs a third error correction process for one or more inner code words whose number of errors has been decreased by the second error correction process and skips the third error correction process for one or more inner code words whose number of errors has not been decreased by the second error correcting process.
摘要翻译：第一级内码解码器对多个内码字执行第一纠错处理。第一级外码解码器对多个外码字执行第二纠错处理。第二级内码解码器对通过第二纠错处理减少错误数的一个或多个内码字执行第三纠错处理，并且针对一个或多个错误数目的内码字跳过第三纠错处理通过第二纠错处理没有减少。

13. 发明授权

US06871315B2 Decoding circuit and decoding method thereof 有权
标题翻译：解码电路及其解码方法
公开(公告)号：US06871315B2
公开(公告)日：2005-03-22
申请号：US09905968
申请日：2001-07-17
申请人： Katsutoshi Seki
发明人： Katsutoshi Seki
IPC分类号： G06F11/10 , H03M13/15 , H03M13/27 , H03M13/00
CPC分类号： H03M13/1595 , H03M13/1515 , H03M13/152 , H03M13/1525 , H03M13/153 , H03M13/1535 , H03M13/154 , H03M13/1545 , H03M13/1555 , H03M13/158
摘要： A decoding circuit and a decoding method thereof can significantly reduce circuit scale and power consumption. The decoding circuit, in which a plurality of code words are transmitted in interleaved manner and a plurality of code words are simultaneously decoded on reception side, comprises a decoder which decodes a plurality of said code words simultaneously.
摘要翻译：解码电路及其解码方法可以显着降低电路规模和功耗。在接收侧同时解码以交织方式发送多个码字的解码电路和多个码字，包括同时解码多个所述码字的解码器。

14. 发明授权

US09424230B2 Converting a data placement between memory banks and an array processing section 有权
标题翻译：在存储体和阵列处理部分之间转换数据放置
公开(公告)号：US09424230B2
公开(公告)日：2016-08-23
申请号：US12594757
申请日：2008-02-22
申请人： Tomoyoshi Kobori , Katsutoshi Seki
发明人： Tomoyoshi Kobori , Katsutoshi Seki
IPC分类号： G06F15/173 , G06F15/80 , G06T1/20
CPC分类号： G06F15/8046 , G06F15/17381 , G06T1/20
摘要： In an array processing section, using data strings entered from input ports, a plurality of data processor elements execute predetermined operations while transferring data to each other, and output data strings of results of the operations from a plurality of output ports. A first data string converter converts data strings stored in a plurality of data storages of a data storage group into a placement suitable for the operations in the array processing section, and enters the converted data strings into the input ports of the array processing section. A second data string converter converts the data strings output from output ports of the array processing section into a placement to be stored in the plurality of data storages of the data storage group.
摘要翻译：在阵列处理部分中，使用从输入端口输入的数据串，多个数据处理器元件在彼此传送数据的同时执行预定的操作，并从多个输出端口输出操作结果的数据串。第一数据串转换器将存储在数据存储组的多个数据存储器中的数据串转换成适用于阵列处理部分中的操作的放置，并将转换的数据串输入到阵列处理部分的输入端口。第二数据串转换器将从阵列处理部分的输出端口输出的数据串转换为要存储在数据存储组的多个数据存储器中的放置。

15. 发明授权

US09021003B2 Processor and operating method 有权
标题翻译：处理器和操作方法
公开(公告)号：US09021003B2
公开(公告)日：2015-04-28
申请号：US13805519
申请日：2011-06-16
申请人： Katsutoshi Seki
发明人： Katsutoshi Seki
IPC分类号： G06F17/14 , G06F7/548 , G06F7/544
CPC分类号： G06F7/548 , G06F7/5446 , G06F17/141
摘要： Disclosed is a processor that is able to efficiently execute DFT operations without having part of a basic operational circuit idle even during non-DFT-operation processing. The processor (1) has an operational means (operation unit) (2) and a control means (control unit) (3). The operation means (2) has a plurality of shift addition-and-subtraction means connected such that CORDIC (COordinate Rotation DIgital Computer) operations can be executed. The shift adding-and-subtracting means also execute shift addition-and-subtraction processing of butterfly operations that process shift addition-and-subtraction for one stage or more. The control means (3) instructs the operation means (2) to execute either CORDIC operations or butterfly operations, based on a plurality of data received from the outside.
摘要翻译：公开了一种处理器，即使在非DFT操作处理期间也能够有效地执行DFT操作而不使基本操作电路的一部分空闲。处理器（1）具有操作装置（操作单元）（2）和控制装置（控制单元）（3）。操作装置（2）具有连接使得可以执行CORDIC（协调旋转二进制计算机）操作的多个移位加法和减法装置。移位加减法装置还执行处理一级以上的移位加减法的蝶形运算的移位加法运算处理。控制装置（3）基于从外部接收的多个数据指示操作装置（2）执行CORDIC操作或蝶形操作。

16. 发明申请

US20130097214A1 PROCESSOR AND OPERATING METHOD 有权
标题翻译：处理器和操作方法
公开(公告)号：US20130097214A1
公开(公告)日：2013-04-18
申请号：US13805519
申请日：2011-06-16
申请人： Katsutoshi Seki
发明人： Katsutoshi Seki
IPC分类号： G06F7/548
CPC分类号： G06F7/548 , G06F7/5446 , G06F17/141
摘要： Disclosed is a processor that is able to efficiently execute DFT operations without having part of a basic operational circuit idle even during non-DFT-operation processing. The processor (1) has an operational means (operation unit) (2) and a control means (control unit) (3). The operation means (2) has a plurality of shift addition-and-subtraction means connected such that CORDIC (COordinate Rotation DIgital Computer) operations can be executed. The shift adding-and-subtracting means also execute shift addition-and-subtraction processing of butterfly operations that process shift addition-and-subtraction for one stage or more. The control means (3) instructs the operation means (2) to execute either CORDIC operations or butterfly operations, based on a plurality of data received from the outside.
摘要翻译：公开了一种处理器，即使在非DFT操作处理期间也能够有效地执行DFT操作而不使基本操作电路的一部分空闲。处理器（1）具有操作装置（操作单元）（2）和控制装置（控制单元）（3）。操作装置（2）具有连接使得可以执行CORDIC（协调旋转二进制计算机）操作的多个移位加法和减法装置。移位加减法装置还执行处理一级以上的移位加减法的蝶形运算的移位加法运算处理。控制装置（3）基于从外部接收的多个数据指示操作装置（2）执行CORDIC操作或蝶形操作。

17. 发明授权

US08195733B2 Systolic array 失效
标题翻译：收缩阵列
公开(公告)号：US08195733B2
公开(公告)日：2012-06-05
申请号：US11878058
申请日：2007-07-20
申请人： Katsutoshi Seki
发明人： Katsutoshi Seki
IPC分类号： G06F7/32 , G06F7/38
CPC分类号： G06F17/16
摘要： Disclosed is a one-dimensional MFA systolic array for matrix computation using an MFA (modified Faddeeva algorithm), in which downward square MFA array processing and upward square MFA array processing are mapped to a one-dimensional array in horizontal directions, respectively. In each PE in the one-dimensional array, downward and upward MFA matrix calculations for two threads are executed. An input and an output are provided for each of PEs at both ends of the one-dimensional array.
摘要翻译：公开了使用MFA（修正的Faddeeva算法）的矩阵计算的一维MFA收缩阵列，其中向下平方MFA阵列处理和向上平方MFA阵列处理分别映射到水平方向上的一维阵列。在一维阵列的每个PE中，执行两个线程的向下和向上的MFA矩阵计算。为一维阵列两端的每个PE提供输入和输出。

18. 发明申请

US20110010408A1 CORDIC COMPUTATION CIRCUIT AND METHOD 有权
标题翻译： CORDIC计算电路和方法
公开(公告)号：US20110010408A1
公开(公告)日：2011-01-13
申请号：US12919632
申请日：2009-03-05
申请人： Katsutoshi Seki
发明人： Katsutoshi Seki
IPC分类号： G06F7/44 , G06F7/42 , G06F11/00
CPC分类号： G06F7/5446 , G06T3/604
摘要： Disclosed is a CORDIC circuit in which scale correction process is divided into two stages: rough correction and fine correction, and a second-process of a pseudo-rotation process is performed in parallel with the fine scale correction. A range of the fine scale correction is set so that it is not necessary to perform a scale correction with regard to a remaining rotation angle of the first half of the pseudo-rotation process.
摘要翻译：公开了一种CORDIC电路，其中缩放校正处理被分为两个阶段：粗略校正和精细校正，并且与精细刻度校正并行执行伪旋转处理的第二处理。精确刻度校正的范围被设定为不需要对伪旋转处理的前半部分的剩余旋转角进行刻度校正。

19. 发明授权

US06944805B2 Self orthogonal decoding circuit and self orthogonal decoding method 有权
标题翻译：自正交解码电路和自正交解码方法
公开(公告)号：US06944805B2
公开(公告)日：2005-09-13
申请号：US09964195
申请日：2001-09-26
申请人： Katsutoshi Seki
发明人： Katsutoshi Seki
IPC分类号： G06F11/10 , H03M13/23 , H03M13/33 , H03M13/39
CPC分类号： H03M13/33 , H03M13/23
摘要： A self orthogonal decoding circuit and a method thereof, can be realized with simple circuit construction and can significantly improve error correction performance. The self orthogonal decoding circuit performing decoding for self orthogonal code repeats decoding for the self orthogonal code for a plurality of times.
摘要翻译：可以通过简单的电路结构实现自正交解码电路及其方法，可以显着提高纠错性能。执行自正交码的解码的自正交解码电路重复对于自正交码多次的解码。

20. 发明授权

US07805654B2 Decoding device and decoding method and program 失效
标题翻译：解码设备和解码方法及程序
公开(公告)号：US07805654B2
公开(公告)日：2010-09-28
申请号：US11476679
申请日：2006-06-29
申请人： Katsutoshi Seki
发明人： Katsutoshi Seki
IPC分类号： H03M13/00
CPC分类号： H03M13/11
摘要： To provide an LDPC decoder, to which SPA is applied, and a method wherein decoding characteristics are improved by reducing the ratio of a message from a check node within messages sent to the same check node. In a decoding device that decodes a received LDPC code by repeating the passing of messages between a plurality of check nodes and a plurality of bit nodes corresponding to a check matrix in each iteration, the order of message computation at a cluster in an iteration out of at least two iterations that have a before-and-after relationship in time and the order of message computation at a cluster in another iteration are varied.
摘要翻译：为了提供应用了SPA的LDPC解码器以及通过减少发送到同一校验节点的消息内的来自校验节点的消息的比率来改进解码特性的方法。在解码装置中，通过重复在多个校验节点之间的消息和与每次迭代中的校验矩阵相对应的多个比特节点之间的消息来解码所接收的LDPC码，将迭代中的簇处的消息计算顺序排除在时间上具有前后关系的至少两次迭代和在另一次迭代中的群集处的消息计算的顺序是变化的。

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