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11. 发明申请

US20090152612A1 HIGH YIELD, HIGH DENSITY ON-CHIP CAPACITOR DESIGN 有权
标题翻译：高密度片上电容设计
公开(公告)号：US20090152612A1
公开(公告)日：2009-06-18
申请号：US12371756
申请日：2009-02-16
申请人： Jonghae Kim , Moon J. Kim , Jean-Olivier Plouchart , Robert E. Trzcinski
发明人： Jonghae Kim , Moon J. Kim , Jean-Olivier Plouchart , Robert E. Trzcinski
IPC分类号： H01L29/94
CPC分类号： H01L27/0811 , H01L23/5223 , H01L27/0688 , H01L27/0805 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A capacitance circuit assembly mounted on a semiconductor chip, and methods for forming the same, are provided. A plurality of divergent capacitors is provided in a parallel circuit connection between first and second ports, the plurality providing at least one Metal Oxide Silicon Capacitor and at least one Vertical Native Capacitor or Metal-Insulator-Metal Capacitor. An assembly has a vertical orientation, a Metal Oxide Silicon capacitor located at the bottom and defining a footprint, with a middle Vertical Native Capacitor having a plurality of horizontal metal layers, including a plurality of parallel positive plates alternating with a plurality of parallel negative plates. In another aspect, vertically asymmetric orientations provide a reduced total parasitic capacitance.
摘要翻译：设置安装在半导体芯片上的电容电路组件及其形成方法。多个发散电容器设置在第一和第二端口之间的并联电路连接中，多个提供至少一个金属氧化物硅电容器和至少一个垂直本机电容器或金属绝缘体金属电容器。组件具有垂直取向，金属氧化物硅电容器位于底部并限定占地面积，中间垂直本机电容器具有多个水平金属层，包括多个平行的正极板，与多个平行的负极板交替。在另一方面，垂直不对称取向提供减小的总寄生电容。

12. 发明申请

US20090108349A1 HIGH-PERFORMANCE FET DEVICE LAYOUT 失效
标题翻译：高性能FET器件布局
公开(公告)号：US20090108349A1
公开(公告)日：2009-04-30
申请号：US11923919
申请日：2007-10-25
申请人： Jonghae Kim , Sungjae Lee , Jean-Olivier Plouchart , Scott Keith Springer
发明人： Jonghae Kim , Sungjae Lee , Jean-Olivier Plouchart , Scott Keith Springer
IPC分类号： H01L29/786
CPC分类号： H01L27/0207 , H01L21/84 , H01L29/4238
摘要： A fast FET, a method and system for designing the fast FET and a design structure of the fast FET. The method includes: selecting a reference design for a field effect transistor, the field effect transistor including a source, a drain, a channel between the source and drain, a gate electrode over the channel, at least one source contact to the source and at least one contact to the drain, the at least one source contact spaced a first distance from the gate electrode and the at least one drain contact spaced a second distance from the gate electrode; and adjusting the first distance and the second distance to maximize a performance parameter of the field effect transistor to create a fast design for the field effect transistor.
摘要翻译：一种用于设计快速FET的快速FET，方法和系统以及快速FET的设计结构。该方法包括：选择场效应晶体管的参考设计，场效应晶体管包括源极，漏极，源极和漏极之间的沟道，沟道上的栅电极，至少一个源极和源极所述至少一个源极接触件与所述栅电极隔开第一距离，所述至少一个漏极接触件与所述栅电极间隔开第二距离; 并且调整第一距离和第二距离以最大化场效应晶体管的性能参数以产生用于场效应晶体管的快速设计。

13. 发明申请

US20070267733A1 Symmetrical MIMCAP capacitor design 审中-公开
标题翻译：对称MIMCAP电容设计
公开(公告)号：US20070267733A1
公开(公告)日：2007-11-22
申请号：US11436251
申请日：2006-05-18
申请人： Choongyeun Cho , Jonghae Kim , Moon Kim , Jean-Olivier Plouchart , Robert Trzcinski
发明人： Choongyeun Cho , Jonghae Kim , Moon Kim , Jean-Olivier Plouchart , Robert Trzcinski
IPC分类号： H01L23/06
CPC分类号： H01L29/94 , H01L23/5223 , H01L27/0805 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor chip capacitance circuits and methods are provided comprising at least two capacitors mounted close to a substrate, wherein each capacitor has a lateral lower conductive plate mounted near enough to the substrate to have extrinsic capacitance greater than an upper plate extrinsic capacitance. One half of lower plates and one half of upper plates are connected to a first port, and a remaining one half of upper plates and lower plates are connected to a second port, the first and second port having about equal extrinsic capacitance from the lower plates. In one aspect, the substrate comprises a front-end-of-line capacitor defining a substrate footprint, and the at least two capacitors are back-end-of-line Metal-Insulator-Metal Capacitors disposed above the footprint. In another aspect, the at least two capacitors are at least four capacitors arrayed in a rectangular array generally parallel to the substrate.
摘要翻译：提供半导体芯片电容电路和方法，其包括安装在基板附近的至少两个电容器，其中每个电容器具有安装在基板附近的侧向下导电板，以具有大于上板外部电容的非本征电容。下板的一半和上板的一半连接到第一端口，并且上板和下板的剩余的一半连接到第二端口，第一和第二端口具有与下板大致相等的外在电容。在一个方面，衬底包括限定衬底占位面积的前端电容器，并且至少两个电容器是设置在覆盖区之上的后端金属 - 绝缘体 - 金属电容器。在另一方面，所述至少两个电容器是至少四个电容器，其排列成大致平行于衬底的矩形阵列。

14. 发明申请

US20070267673A1 Adjustable on-chip sub-capacitor design 有权
标题翻译：可调片上子电容设计
公开(公告)号：US20070267673A1
公开(公告)日：2007-11-22
申请号：US11436249
申请日：2006-05-18
申请人： Jonghae Kim , Moon J. Kim , Jean-Olivier Plouchart , Robert E. Trzcinski
发明人： Jonghae Kim , Moon J. Kim , Jean-Olivier Plouchart , Robert E. Trzcinski
IPC分类号： H01L27/108 , H01L29/94 , H01L29/76 , H01L31/119
CPC分类号： H01L27/0805 , H01L23/5223 , H01L27/0688 , H01L27/0808 , H01L2924/0002 , H01L2924/00
摘要： One or more on-chip VNCAP or MIMCAP capacitors utilize a variable MOS capacitor to improve the uniform capacitance value of the capacitors. This permits the production of silicon semiconductor chips on which are mounted capacitors having capacitive values that are precisely adjusted to be within a range of between about 1% and 5% of their design value. This optimization can be achieved by the use of a back-to-back connection between a pair of the variable MOS capacitors for DC decoupling. It involves the parallelization of on-chip BEOL capacitance of VNCAP and/or MIMCAP capacitors by the insertion in the FEOL of pairs of back-to-back variable MOS capacitors.
摘要翻译：一个或多个片上VNCAP或MIMCAP电容器利用可变MOS电容来改善电容器的均匀电容值。这允许生产硅半导体芯片，其上安装有具有精确调节的电容值的电容器在其设计值的约1％至5％的范围内。该优化可以通过使用一对用于DC去耦的可变MOS电容器之间的背对背连接来实现。它涉及VOCAP和/或MIMCAP电容器的片上BEOL电容的并联，通过在FEOL中插入成对的背对背可变MOS电容器。

15. 发明授权

US06518903B1 Analog-to-digital converter 有权
标题翻译：模数转换器
公开(公告)号：US06518903B1
公开(公告)日：2003-02-11
申请号：US09649733
申请日：2000-08-28
申请人： Laurent C. Perraud , Jean-Olivier Plouchart , Mehmet Soyuer , Nicolas Sornin
发明人： Laurent C. Perraud , Jean-Olivier Plouchart , Mehmet Soyuer , Nicolas Sornin
IPC分类号： H03M300
CPC分类号： H03M3/47
摘要： A Sigma Delta A/D converter architecture which allows the multiplexed conversion of several high bandwidth analog signals.
摘要翻译：一个Sigma Delta A / D转换器架构，允许多路转换多个高带宽模拟信号。

16. 发明授权

US08937355B2 Striped on-chip inductor 有权
公开(公告)号：US08937355B2
公开(公告)日：2015-01-20
申请号：US13469464
申请日：2012-05-11
申请人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon J. Kim , Jean-Olivier Plouchart , Robert E. Trzcinski
发明人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon J. Kim , Jean-Olivier Plouchart , Robert E. Trzcinski
IPC分类号： H01L21/00 , H01L49/02 , H01L23/522 , H01L27/02 , H01F17/00
CPC分类号： H01L28/10 , H01F17/0013 , H01F2017/0073 , H01L23/5227 , H01L27/0203 , H01L2924/0002 , H01L2924/00
摘要： Sub-100 nanometer semiconductor devices and methods and program products for manufacturing devices are provided, in particular inductors comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and each having width, heights, spacing and cross-sectional areas determined as a function of Design Rule Check rules. For one planarization process rule a metal density ratio of 80% metal to 20% dielectric surface is determined and produced. In one example a sum of metal line spacing gaps is less than a sum of metal line interior sidewall heights. In one aspect at least one of line height, width and line spacing dimensions is selected to optimize one or more chip yield, chip performance, chip manufacturability and inductor Q factor parameters.

17. 发明授权

US08872279B2 Transistor structure having an electrical contact structure with multiple metal interconnect levels staggering one another 有权
标题翻译：晶体管结构具有电接触结构，多个金属互连层互相交错
公开(公告)号：US08872279B2
公开(公告)日：2014-10-28
申请号：US13347851
申请日：2012-01-11
申请人： David R. Greenberg , Jean-Olivier Plouchart , Alberto Valdes-Garcia
发明人： David R. Greenberg , Jean-Olivier Plouchart , Alberto Valdes-Garcia
IPC分类号： H01L27/088 , H01L23/482 , H01L29/423 , H01L29/78
CPC分类号： H01L27/0207 , H01L23/4824 , H01L23/528 , H01L27/088 , H01L29/41758 , H01L29/42376 , H01L29/4238 , H01L29/78 , H01L2924/0002 , H01L2924/14 , H01L2924/30105 , H01L2924/00
摘要： An electrical contact structure distributes current along a length thereof. The electrical contact structure includes a plurality of n metal rectangles on n levels of metal. The rectangle on one metal level is at least as wide in width and vertically covers in width the rectangle on the metal level immediately below. The rectangle on one metal level is shorter in length than and substantially aligned at a first end with the rectangle on the metal level immediately below. Rectangle first ends are substantially aligned. Features of an exemplary FET transistor of this invention are a source and drain terminal electrical contact structure, a multi-level metal ring connecting gate rectangles on both ends, and a wider-than-minimum gate-to-gate spacing. The invention is useful, for example, in an electromigration-compliant, high performance transistor.
摘要翻译：电接触结构沿其长度分布电流。电接触结构包括在n级金属上的多个n个金属矩形。一个金属层上的矩形至少具有宽度的宽度，并且垂直地在宽度上覆盖紧接在下面的金属层上的矩形。一个金属层上的矩形长度短于第一端，并且在紧靠下方的金属层上的矩形基本对齐。矩形的第一端基本对齐。本发明的示例性FET晶体管的特征是源极和漏极端子电接触结构，在两端连接栅极矩形的多级金属环和大于最小栅极至栅极间隔。本发明例如在电迁移兼容的高性能晶体管中是有用的。

18. 发明授权

US07939910B2 Structure for symmetrical capacitor 有权
标题翻译：对称电容器结构
公开(公告)号：US07939910B2
公开(公告)日：2011-05-10
申请号：US12851814
申请日：2010-08-06
申请人： Choongyeun Cho , Jonghae Kim , Moon J. Kim , Jean-Olivier Plouchart , Robert E. Trzcinski
发明人： Choongyeun Cho , Jonghae Kim , Moon J. Kim , Jean-Olivier Plouchart , Robert E. Trzcinski
IPC分类号： H01L29/00
CPC分类号： H01L29/94 , H01L23/5223 , H01L27/0805 , H01L2924/0002 , H01L2924/00
摘要： Capacitance circuits are provided disposing a lower vertical-native capacitor metal layer above a planar front-end-of-line semiconductor base substrate, planar metal bottom plates spaced a bottom plate distance from the base and top plates above the bottom plates spaced a top plate distance from the base defining metal-insulator-metal capacitors, top plate footprints disposed above the base substrate smaller than bottom plate footprints and exposing bottom plate remainder upper lateral connector surfaces; disposing parallel positive port and negative port upper vertical-native capacitor metal layers over and each connected to top plate and bottom plate upper remainder lateral connector surface. Moreover, electrical connecting of the first top plate and the second bottom plate to the positive port metal layer and of the second top plate and the first bottom to the negative port metal layer impart equal total negative port and positive port metal-insulator-metal capacitor extrinsic capacitance.
摘要翻译：提供电容电路，其设置在平面前端半导体基底基板上方的下垂直电容器金属层，与底板间隔开的底板距离的平面金属底板和位于底板上方的顶板，间隔开顶板距离限定金属 - 绝缘体 - 金属电容器的基底的距离，设置在基底基板之上的顶板印迹小于底板印迹并且暴露底板剩余的上横向连接器表面; 将平行的正端口和负端口上垂直电容器金属层布置在每个顶板和底板的上部剩余侧面连接器表面上。此外，第一顶板和第二底板与正端口金属层以及第二顶板和第一底部到负极金属层的电连接赋予相等的总负端口和正端口金属 - 绝缘体 - 金属电容器外在电容。

19. 发明申请

US20100259107A1 Systems and Methods for Providing Power to a Device Under Test 审中-公开
标题翻译：向被测设备供电的系统和方法
公开(公告)号：US20100259107A1
公开(公告)日：2010-10-14
申请号：US12679204
申请日：2008-11-14
申请人： Peter Kinget , Jean-Olivier Plouchart
发明人： Peter Kinget , Jean-Olivier Plouchart
IPC分类号： H02J17/00
CPC分类号： G01R31/315 , G01R31/3025
摘要： Systems and methods for providing power to a device under test are prcn ided. In some embodiments, systems for providing power to a device under test are provided, the systems comprising a power source for providing an alternating current, a probe having a probe inductor coupled to the power source; and a device under test having a device inductor magnetically coupled to the probe inductor, and having a circuit to be tested that receives power produced in the device inductor, In some embodiments, devices that receive power from a probe having an inductor that is coupled to an alternating current power source are provided, the devices comprising: a device inductor magnetically coupled to the probe inductor; and a circuit to be tested that receives power produced in the device inductor.
摘要翻译：准备向被测设备供电的系统和方法。在一些实施例中，提供了用于向受测设备提供电力的系统，所述系统包括用于提供交流电的电源，具有耦合到所述电源的探针电感器的探针; 以及被测器件，其具有与探头电感器磁耦合的器件电感器，并且具有接收在器件电感器中产生的功率的待测试电路。在一些实施例中，从具有耦合到提供交流电源，所述装置包括：与所述探针电感器磁耦合的器件电感器; 以及接收在器件电感器中产生的功率的待测电路。

20. 发明授权

US07791160B2 High-performance FET device layout 失效
标题翻译：高性能FET器件布局
公开(公告)号：US07791160B2
公开(公告)日：2010-09-07
申请号：US11923919
申请日：2007-10-25
申请人： Jonghae Kim , Sungjae Lee , Jean-Olivier Plouchart , Scott Keith Springer
发明人： Jonghae Kim , Sungjae Lee , Jean-Olivier Plouchart , Scott Keith Springer
IPC分类号： H01L29/786
CPC分类号： H01L27/0207 , H01L21/84 , H01L29/4238
摘要： A fast FET, a method and system for designing the fast FET and a design structure of the fast FET. The method includes: selecting a reference design for a field effect transistor, the field effect transistor including a source, a drain, a channel between the source and drain, a gate electrode over the channel, at least one source contact to the source and at least one contact to the drain, the at least one source contact spaced a first distance from the gate electrode and the at least one drain contact spaced a second distance from the gate electrode; and adjusting the first distance and the second distance to maximize a performance parameter of the field effect transistor to create a fast design for the field effect transistor.
摘要翻译：一种用于设计快速FET的快速FET，方法和系统以及快速FET的设计结构。该方法包括：选择场效应晶体管的参考设计，场效应晶体管包括源极，漏极，源极和漏极之间的沟道，沟道上的栅电极，至少一个源极和源极所述至少一个源极接触件与所述栅电极隔开第一距离，所述至少一个漏极接触件与所述栅电极间隔开第二距离; 并且调整第一距离和第二距离以最大化场效应晶体管的性能参数以产生用于场效应晶体管的快速设计。

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