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11. 发明授权

US07814300B2 Configurable pipeline to process an operation at alternate pipeline stages depending on ECC/parity protection mode of memory access 有权
标题翻译：根据ECC /奇偶校验保护存储器访问模式，可配置流水线处理备用流水线阶段的操作
公开(公告)号：US07814300B2
公开(公告)日：2010-10-12
申请号：US12112583
申请日：2008-04-30
申请人： William C. Moyer , Jeffrey W. Scott
发明人： William C. Moyer , Jeffrey W. Scott
IPC分类号： G06F9/38
CPC分类号： G06F9/3875 , G06F9/3004 , G06F9/30181 , G06F9/30189 , G06F9/38 , G06F9/3861 , G06F9/3867 , G06F11/1004 , G06F11/1008 , G06F11/1076
摘要： A method includes providing a data processor having an instruction pipeline, where the instruction pipeline has a plurality of instruction pipeline stages, and where the plurality of instruction pipeline stages includes a first instruction pipeline stage and a second instruction pipeline stage. The method further includes providing a data processor instruction that causes the data processor to perform a first set of computational operations during execution of the data processor instruction, performing the first set of computational operations in the first instruction pipeline stage if the data processor instruction is being executed and a first mode has been selected, and performing the first set of computational operations in the second instruction pipeline stage if the data processor instruction is being executed and a second mode has been selected.
摘要翻译：一种方法包括提供具有指令流水线的数据处理器，其中指令流水线具有多个指令流水线级，并且其中多条指令流水线级包括第一指令流水线级和第二指令流水线级。该方法还包括提供数据处理器指令，使数据处理器在数据处理器指令的执行期间执行第一组计算操作，如果数据处理器指令正在执行，则在第一指令流水线阶段执行第一组计算操作执行并且已经选择了第一模式，并且如果正在执行数据处理器指令并且已经选择了第二模式，则在第二指令流水线级中执行第一组计算操作。

12. 发明申请

US20100166124A1 DIGITAL ARCHITECTURE FOR RADIO-FREQUENCY APPARATUS AND ASSOCIATED METHODS 有权
标题翻译：无线电频率设备数码建筑及相关方法
公开(公告)号：US20100166124A1
公开(公告)日：2010-07-01
申请号：US12715361
申请日：2010-03-01
申请人： Richard T. Behrens , Tod Paulus , Mark S. Spurbeck , Vishnu S. Srinivasan , Donald A. Kerth , Jeffrey W. Scott , G. Tyson Tuttle , G. Diwakar Vishakhadatta
发明人： Richard T. Behrens , Tod Paulus , Mark S. Spurbeck , Vishnu S. Srinivasan , Donald A. Kerth , Jeffrey W. Scott , G. Tyson Tuttle , G. Diwakar Vishakhadatta
IPC分类号： H04L27/00 , H04B1/10
CPC分类号： H04B1/28 , H04B1/0003 , H04B1/38 , H04B1/406 , H04B15/02 , H04B15/04 , H04B2215/064
摘要： A radio-frequency (RF) receiver includes a receiver analog circuitry and a receiver digital circuitry. The receiver analog circuitry resides within a first integrated circuit and the receiver digital circuitry resides within a second integrated circuit. The second integrated circuit couples to the first integrated circuit via a one-bit digital interface. The receiver analog circuitry receives an RF signal and processes the received RF signal to generate a digital signal. The receiver analog circuitry provides the digital signal to the receiver digital circuitry. The receiver digital circuitry includes a digital down-converter circuitry that mixes the digital signal with an intermediate frequency (IF) local oscillator (LO) signal to generate a digital down-converted signal. The receiver digital circuitry also includes a digital filter circuitry that filters the digital down-converted signal to generate a filtered digital signal.
摘要翻译：射频（RF）接收机包括接收机模拟电路和接收机数字电路。接收器模拟电路驻留在第一集成电路内，并且接收器数字电路位于第二集成电路内。第二集成电路通过一位数字接口耦合到第一集成电路。接收机模拟电路接收RF信号并处理所接收的RF信号以产生数字信号。接收机模拟电路将数字信号提供给接收机数字电路。接收机数字电路包括数字下变频器电路，其将数字信号与中频（IF）本地振荡器（LO）信号混合以产生数字下变频信号。接收机数字电路还包括数字滤波器电路，其对数字下变频信号进行滤波以产生经滤波的数字信号。

13. 发明申请

US20100031010A1 BRANCH TARGET BUFFER ALLOCATION 有权
标题翻译：分支目标缓冲区分配
公开(公告)号：US20100031010A1
公开(公告)日：2010-02-04
申请号：US12181363
申请日：2008-07-29
申请人： William C. Moyer , Jeffrey W. Scott
发明人： William C. Moyer , Jeffrey W. Scott
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/3844
摘要： A data processing system and method are provided for allocating an entry in a branch target buffer (BTB). The method comprises: receiving a branch instruction to be executed in a data processor; determining that the BTB does not include an entry corresponding to the branch instruction; identifying an entry in the BTB for allocation, the identified entry in the BTB comprising a target identifier and a first prediction value for a previously received branch instruction; determining whether to allocate the branch instruction to the identified entry in the BTB based on a comparison of the first prediction value to a second prediction value, wherein the second prediction value is generated from a branch history table (BHT); and allocating the branch instruction to the identified entry if the second prediction value indicates a more strongly taken prediction than the first prediction value.
摘要翻译：提供了一种用于在分支目标缓冲器（BTB）中分配条目的数据处理系统和方法。该方法包括：接收要在数据处理器中执行的分支指令; 确定BTB不包括对应于分支指令的条目; 识别BTB中用于分配的条目，BTB中识别的条目包括目标标识符和用于先前接收到的分支指令的第一预测值; 基于第一预测值与第二预测值的比较，确定是否将分支指令分配给BTB中的识别条目，其中从分支历史表（BHT）生成第二预测值; 以及如果所述第二预测值指示比所述第一预测值更强烈地采取预测，则将所述分支指令分配给所识别的条目。

14. 发明申请

US20090276587A1 SELECTIVELY PERFORMING A SINGLE CYCLE WRITE OPERATION WITH ECC IN A DATA PROCESSING SYSTEM 审中-公开
标题翻译：在数据处理系统中选择性地执行ECC的单周期写操作
公开(公告)号：US20090276587A1
公开(公告)日：2009-11-05
申请号：US12112580
申请日：2008-04-30
申请人： William C. Moyer , Jeffrey W. Scott
发明人： William C. Moyer , Jeffrey W. Scott
IPC分类号： G06F12/00
CPC分类号： G06F11/1044 , G11C2029/0411
摘要： A circuit includes a memory having error correction, circuitry which initiates a write operation to memory. When error correction is enabled and the write operation to the memory has the width of N bits, the write operation to the memory is performed in one access to the memory, and when error correction is enabled and the write operation to the memory has the width of M bits, where M bits is less than N bits, the write operation to the memory is performed in more than one access to the memory. In one example, the one access to the memory includes a write access to the memory, and the more than one access to the memory includes a read access to the memory and a write access to the memory.
摘要翻译：电路包括具有纠错的存储器，其启动对存储器的写入操作的电路。当启用纠错并且对存储器的写操作具有N位的宽度时，对存储器的写入操作在对存储器的一次访问中执行，并且当使能错误校正并且对存储器的写入操作具有宽度的M位，其中M位小于N位，对存储器的写入操作在对存储器的多次访问中执行。在一个示例中，对存储器的一次访问包括对存储器的写访问，并且对存储器的多个访问包括对存储器的读访问和对存储器的写访问。

15. 发明申请

US20090222645A1 METRIC FOR SELECTIVE BRANCH TARGET BUFFER (BTB) ALLOCATION 有权
标题翻译：选择性分支目标缓冲区（BTB）分配的公制
公开(公告)号：US20090222645A1
公开(公告)日：2009-09-03
申请号：US12040210
申请日：2008-02-29
申请人： William C. Moyer , Jeffrey W Scott
发明人： William C. Moyer , Jeffrey W Scott
IPC分类号： G06F9/32 , G06F9/312
CPC分类号： G06F9/3806 , G06F9/30058 , G06F9/3804 , G06F9/382
摘要： A method and data processing system allocates entries in a branch target buffer (BTB). Instructions are fetched from a plurality of instructions and one of the plurality of instructions is determined to be a branch instruction. A corresponding branch target address is determined. A determination is made whether the branch target address is stored in a branch target buffer (BTB). When the branch target address is not stored in the branch target buffer, an entry in the branch target buffer is identified for allocation to receive the branch target address based upon stored metrics such as data processing cycle saving information and branch prediction state. In one form the stored metrics are stored in predetermined fields of the entries of the BTB.
摘要翻译：方法和数据处理系统在分支目标缓冲器（BTB）中分配条目。指令从多个指令中取出，并且多个指令中的一个被确定为分支指令。确定相应的分支目标地址。确定分支目标地址是否存储在分支目标缓冲器（BTB）中。当分支目标地址未被存储在分支目标缓冲器中时，识别分支目标缓冲器中的条目用于分配以基于存储的诸如数据处理周期保存信息和分支预测状态的指标来接收分支目标地址。在一种形式中，存储的度量被存储在BTB的条目的预定字段中。

16. 发明授权

US07366478B2 Partitioned radio-frequency apparatus and associated methods 有权
公开(公告)号：US07366478B2
公开(公告)日：2008-04-29
申请号：US10878880
申请日：2004-06-28
申请人： Donald A. Kerth , Richard T. Behrens , Jeffrey W. Scott , G. Diwakar Vishakhadatta , G. Tyson Tuttle , Vishnu Shankar Srinivasan
发明人： Donald A. Kerth , Richard T. Behrens , Jeffrey W. Scott , G. Diwakar Vishakhadatta , G. Tyson Tuttle , Vishnu Shankar Srinivasan
IPC分类号： H04B1/40
CPC分类号： H04B1/109 , H04B1/0003 , H04B1/28 , H04B1/406 , H04B15/02 , H04B15/04 , H04B2215/064 , H04L27/2649
摘要： Radio-frequency (RF) apparatus includes receiver analog circuitry that receives an RF signal and provides at least one digital signal to receiver digital circuitry that functions in cooperation with the receiver analog circuitry. The receiver analog circuitry and the receiver digital circuitry are partitioned so that interference effects between the receiver analog circuitry and the receiver digital circuitry tend to be reduced.

17. 发明授权

US07177610B2 Calibrated low-noise current and voltage references and associated methods 有权
标题翻译：校准的低噪声电流和电压参考及相关方法
公开(公告)号：US07177610B2
公开(公告)日：2007-02-13
申请号：US10081121
申请日：2002-02-22
申请人： Jeffrey W. Scott , G. Diwakar Vishakhadatta , Donald A. Kerth , Richard T. Behrens , G. Tyson Tuttle , Vishnu S. Srinivasan
发明人： Jeffrey W. Scott , G. Diwakar Vishakhadatta , Donald A. Kerth , Richard T. Behrens , G. Tyson Tuttle , Vishnu S. Srinivasan
IPC分类号： H04B1/06 , H04B7/00
CPC分类号： H04B1/0003 , H04B1/28 , H04B1/406 , H04B15/02 , H04B15/04 , H04B2215/064
摘要： A low-noise current reference circuitry includes a voltage source, a current source, and a controller. The voltage source generates a reference voltage. The current source provides a low-noise output current in response to a control signal. The controller provides the control signal based at least in part on the relative magnitudes of the reference voltage and a voltage derived from the output current. A low-noise voltage reference circuitry includes a reference voltage source, a voltage source, and a controller. The reference voltage source generates a reference voltage. The voltage source provides a low-noise output voltage in response to a control signal. The controller provides the control signal based at least in part on the relative magnitudes of the output voltage and the reference voltage.
摘要翻译：低噪声电流参考电路包括电压源，电流源和控制器。电压源产生参考电压。电流源提供响应于控制信号的低噪声输出电流。控制器至少部分地基于参考电压的相对幅度和从输出电流导出的电压来提供控制信号。低噪声电压参考电路包括参考电压源，电压源和控制器。参考电压源产生参考电压。电压源响应于控制信号提供低噪声输出电压。控制器至少部分地基于输出电压和参考电压的相对幅度提供控制信号。

18. 发明授权

US07096348B2 Method and apparatus for allocating entries in a branch target buffer 有权
标题翻译：用于在分支目标缓冲器中分配条目的方法和装置
公开(公告)号：US07096348B2
公开(公告)日：2006-08-22
申请号：US10736393
申请日：2003-12-15
申请人： William C. Moyer , Jeffrey W. Scott
发明人： William C. Moyer , Jeffrey W. Scott
IPC分类号： G06F9/00
CPC分类号： G06F9/382 , G06F9/3806
摘要： A method (200) and apparatus (100) for allocating entries in a branch target buffer (BTB) (144) in a pipelined data processing system includes: sequentially fetching instructions; determining that one of the instructions is a branch instruction (210, 215, 220); decoding the branch instruction to determine a branch target address; determining if the branch target address can be obtained without causing a stall condition in the pipelined data processing system; and selectively allocating an entry of the BTB (144) based on the determination. In one embodiment, an entry of the BTB (144) is allocated if the branch instruction is not loaded into a predetermined slot (S1) of a prefetch buffer (102) and no other stall condition will occur. The method (200) and apparatus (100) combine the advantages of using a BTB (144) and branch lookahead to reduce stall conditions in the data processing system.
摘要翻译：一种用于在流水线数据处理系统中分配目标缓冲器（BTB）（144）中的条目的方法（200）和装置（100）包括：顺序取指令; 确定所述指令之一是分支指令（210,215,220）; 解码分支指令以确定分支目标地址; 确定是否可以获得分支目标地址而不导致流水线数据处理系统中的停顿状态; 以及基于所述确定来选择性地分配所述BTB（144）的条目。在一个实施例中，如果分支指令未被加载到预取缓冲器（102）的预定时隙（S1）中并且不会发生其他失速条件，则分配BTB（144）的条目。方法（200）和装置（100）组合使用BTB（144）和分支前视的优点来减少数据处理系统中的失速状况。

19. 发明授权

US07050509B2 Digital isolation system with hybrid circuit in ADC calibration loop 失效
公开(公告)号：US07050509B2
公开(公告)日：2006-05-23
申请号：US10161902
申请日：2002-06-04
申请人： Andrew W. Krone , Timothy J. Dupuis , Jeffrey W. Scott , Navdeep S. Sooch , David R. Welland
发明人： Andrew W. Krone , Timothy J. Dupuis , Jeffrey W. Scott , Navdeep S. Sooch , David R. Welland
IPC分类号： H04B1/38 , H04B15/00
CPC分类号： H04M1/573 , H04L7/033 , H04L25/0266 , H04L25/06 , H04M11/06 , H04M19/001 , H04M19/02
摘要： An improved digital capacitive isolation barrier system is provided that is suitable for use in a telephone or modem where the locally powered circuits must be effectively isolated from the public telephone system, while permitting data transfer across the barrier. In particular, an automatic ADC offset calibration system is provided for determining the magnitude of the ADC offset signal required in the system during a calibration operation, and for providing the calibrated ADC offset signal during normal operation of the isolation barrier system. A modified hybrid circuit is provided for isolating the system input from the telephone line during calibration, and for completing the calibration loop. Fixed bias signals are also provided for the ADC and for a DAC in the system. In a preferred embodiment, the ADC is located on the isolated side of the isolation barrier, while the integrator and register that determine and hold the offset signal are located on the powered side of the isolation barrier.

20. 发明授权

US07003023B2 Digital isolation system with ADC offset calibration 失效
标题翻译：具有ADC偏移校准的数字隔离系统
公开(公告)号：US07003023B2
公开(公告)日：2006-02-21
申请号：US10672259
申请日：2003-09-26
申请人： Andrew W. Krone , Timothy J. Dupuis , Jeffrey W. Scott , Navdeep S. Sooch , David R. Welland
发明人： Andrew W. Krone , Timothy J. Dupuis , Jeffrey W. Scott , Navdeep S. Sooch , David R. Welland
IPC分类号： H04B1/38
CPC分类号： H04M1/573 , H04L7/033 , H04L25/0266 , H04L25/06 , H04M11/06 , H04M19/001 , H04M19/02
摘要： An improved digital capacitive isolation barrier system is provided that is suitable for use in a telephone or modem where the locally powered circuits must be effectively isolated from the public telephone system, while permitting data transfer across the barrier. In particular, an automatic ADC offset calibration system is provided for determining the magnitude of the ADC offset signal required in the system during a calibration operation, and for providing the calibrated ADC offset signal during normal operation of the isolation barrier system. A modified hybrid circuit is provided for isolating the system input from the telephone line during calibration, and for completing the calibration loop. Fixed bias signals are also provided for the ADC and for a DAC in the system. In a preferred embodiment, the ADC is located on the isolated side of the isolation barrier, while the integrator and register that determine and hold the offset signal are located on the powered side of the isolation barrier.
摘要翻译：提供了一种改进的数字电容隔离屏障系统，其适用于电话或调制解调器，其中本地供电的电路必须与公共电话系统有效地隔离，同时允许跨屏障的数据传输。特别地，提供了一种自动ADC偏移校准系统，用于在校准操作期间确定系统中所需的ADC偏移信号的幅度，并在隔离屏障系统的正常操作期间提供校准的ADC偏移信号。提供了一种改进的混合电路，用于在校准期间隔离来自电话线的系统输入，并用于完成校准循环。还为ADC和系统中的DAC提供固定偏置信号。在优选实施例中，ADC位于隔离屏障的隔离侧，而确定和保持偏移信号的积分器和寄存器位于隔离屏障的动力侧。

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