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11. 发明授权

US08450788B2 Three-dimensional microelectronic devices including horizontal and vertical patterns 有权
公开(公告)号：US08450788B2
公开(公告)日：2013-05-28
申请号：US13300818
申请日：2011-11-21
申请人： Sun-Il Shim , Sung-Hoi Hur , Jin-Ho Kim , Su-Youn Yi
发明人： Sun-Il Shim , Sung-Hoi Hur , Jin-Ho Kim , Su-Youn Yi
IPC分类号： H01L29/76
CPC分类号： H01L27/1158 , H01L27/11521 , H01L27/11524 , H01L27/11551 , H01L27/11556 , H01L27/11568 , H01L27/11578 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792 , H01L29/7926
摘要： A vertical NAND flash memory device includes a substrate having a face and a string of serially connected flash memory cells on the substrate. A first flash memory cell is adjacent the face, and a last flash memory cell is remote from the face. The flash memory cells include repeating layer patterns that are stacked on the face, and a pillar that extends through the series of repeating layer patterns. The pillar includes at least one oblique wall. At least two of the series of repeating layer patterns in the string are of different thicknesses. Other vertical microelectronic devices and related fabrication methods are also described.

12. 发明申请

US20130044545A1 NON-VOLATILE MEMORY DEVICE HAVING VERTICAL STRUCTURE AND METHOD OF OPERATING THE SAME 审中-公开
标题翻译：具有垂直结构的非易失性存储器件及其操作方法
公开(公告)号：US20130044545A1
公开(公告)日：2013-02-21
申请号：US13658461
申请日：2012-10-23
申请人： Jae-hun Jeong , Han-soo Kim , Won-seok Cho , Jae-hoon Jang , Sun-il Shim
发明人： Jae-hun Jeong , Han-soo Kim , Won-seok Cho , Jae-hoon Jang , Sun-il Shim
IPC分类号： G11C16/10
CPC分类号： G11C16/0483 , G11C16/10 , G11C16/26 , H01L23/5226 , H01L27/11524 , H01L27/11551 , H01L27/11556 , H01L27/11582 , H01L29/66825 , H01L29/7881
摘要： A non-volatile memory device having a vertical structure includes a NAND string having a vertical structure. The NAND string includes a plurality of memory cells, and at least one pair of first selection transistors arranged to be adjacent to a first end of the plurality of memory cells. A plurality of word lines are coupled to the plurality of memory cells of the NAND string. A first selection line is commonly connected to the at least one pair of first selection transistors of the NAND string.
摘要翻译：具有垂直结构的非易失性存储器件包括具有垂直结构的NAND串。 NAND串包括多个存储单元，并且至少一对第一选择晶体管布置成与多个存储单元的第一端相邻。多个字线耦合到NAND串的多个存储单元。第一选择线通常连接到NAND串的至少一对第一选择晶体管。

13. 发明申请

US20120061741A1 THREE-DIMENSIONAL MICROELECTRONIC DEVICES INCLUDING HORIZONTAL AND VERTICAL PATTERNS 有权
标题翻译：包括水平和垂直图案的三维微电子器件
公开(公告)号：US20120061741A1
公开(公告)日：2012-03-15
申请号：US13300818
申请日：2011-11-21
申请人： Sun-Il Shim , Sung-Hoi Hur , Jin-Ho Kim , Su-Youn Yi
发明人： Sun-Il Shim , Sung-Hoi Hur , Jin-Ho Kim , Su-Youn Yi
IPC分类号： H01L29/78
CPC分类号： H01L27/1158 , H01L27/11521 , H01L27/11524 , H01L27/11551 , H01L27/11556 , H01L27/11568 , H01L27/11578 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792 , H01L29/7926
摘要： A vertical NAND flash memory device includes a substrate having a face and a string of serially connected flash memory cells on the substrate. A first flash memory cell is adjacent the face, and a last flash memory cell is remote from the face. The flash memory cells include repeating layer patterns that are stacked on the face, and a pillar that extends through the series of repeating layer patterns. The pillar includes at least one oblique wall. At least two of the series of repeating layer patterns in the string are of different thicknesses. Other vertical microelectronic devices and related fabrication methods are also described.
摘要翻译：垂直NAND闪速存储器件包括在衬底上具有面和串联的闪存单元串的衬底。第一闪存单元与面相邻，并且最后的闪存单元远离面。闪存单元包括堆叠在表面上的重复层图案和延伸穿过一系列重复层图案的柱。支柱包括至少一个斜壁。串中重复层图案的系列中的至少两个具有不同的厚度。还描述了其它垂直微电子器件和相关的制造方法。

14. 发明申请

US20110013353A1 MULTI-CHIP PACKAGE STRUCTURE SUITABLE FOR MULTI-PROCESSOR SYSTEM HAVING MEMORY LINK ARCHITECTURE 审中-公开
标题翻译：适用于具有存储器链接架构的多处理器系统的多芯片封装结构
公开(公告)号：US20110013353A1
公开(公告)日：2011-01-20
申请号：US12717027
申请日：2010-03-03
申请人： Jin-Hyoung Kwon , Bo-Il Shim
发明人： Jin-Hyoung Kwon , Bo-Il Shim
IPC分类号： G06F1/16
CPC分类号： G06F1/183 , H01L23/3128 , H01L24/16 , H01L24/48 , H01L25/03 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L25/18 , H01L2224/16225 , H01L2224/16227 , H01L2224/32145 , H01L2224/48225 , H01L2224/48227 , H01L2224/73215 , H01L2224/73265 , H01L2225/0651 , H01L2225/06565 , H01L2225/06568 , H01L2225/06596 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/13091 , H01L2924/1432 , H01L2924/14335 , H01L2924/1436 , H01L2924/1438 , H01L2924/15192 , H01L2924/15311 , H01L2924/15313 , H01L2924/15321 , H01L2924/15331 , H01L2924/19107 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A multi-chip package structure can include a first package that includes a first circuit board that includes a lower surface including a first circuit pattern thereon and an upper surface, that is opposite the lower surface, and includes an upper pad layer thereon. The multi-chip package structure can further include at least one processor chip that is mounted on the lower surface of the first circuit board. A second package can be mounted on the first package and can include a second circuit board including an upper surface that includes a second circuit pattern thereon and a lower surface, which is opposite the upper surface, which can includes a lower pad layer thereon that is electrically connected to the upper pad layer of the first circuit board. At least one memory chip can be laminated and molded on the upper surface of the second package.
摘要翻译：多芯片封装结构可以包括第一封装，其包括第一电路板，第一电路板包括其上的第一电路图案的下表面和与下表面相对的上表面，并且在其上包括上焊盘层。多芯片封装结构还可以包括安装在第一电路板的下表面上的至少一个处理器芯片。第二包装可以安装在第一包装上，并且可以包括第二电路板，其包括其上的第二电路图案的上表面和与上表面相对的下表面，其可以包括在其上的下垫层，电连接到第一电路板的上焊盘层。可以在第二包装的上表面上层压和模制至少一个存储芯片。

15. 发明申请

US20100078701A1 THREE-DIMENSIONAL MICROELECTRONIC DEVICES INCLUDING REPEATING LAYER PATTERNS OF DIFFERENT THICKNESSES 有权
标题翻译：三维微电子器件，包括重复不同厚度的层状图案
公开(公告)号：US20100078701A1
公开(公告)日：2010-04-01
申请号：US12420518
申请日：2009-04-08
申请人： Sun-Il Shim , Sung-Hoi Hur , Jin-Ho Kim , Su-Youn Yi
发明人： Sun-Il Shim , Sung-Hoi Hur , Jin-Ho Kim , Su-Youn Yi
IPC分类号： H01L29/788 , H01L29/66
CPC分类号： H01L27/1158 , H01L27/11521 , H01L27/11524 , H01L27/11551 , H01L27/11556 , H01L27/11568 , H01L27/11578 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792 , H01L29/7926
摘要： A vertical NAND flash memory device includes a substrate having a face and a string of serially connected flash memory cells on the substrate. A first flash memory cell is adjacent the face, and a last flash memory cell is remote from the face. The flash memory cells include repeating layer patterns that are stacked on the face, and a pillar that extends through the series of repeating layer patterns. The pillar includes at least one oblique wall. At least two of the series of repeating layer patterns in the string are of different thicknesses. Other vertical microelectronic devices and related fabrication methods are also described.
摘要翻译：垂直NAND闪速存储器件包括在衬底上具有面和串联的闪存单元串的衬底。第一闪存单元与面相邻，并且最后的闪存单元远离面。闪存单元包括堆叠在表面上的重复层图案和延伸穿过一系列重复层图案的柱。支柱包括至少一个斜壁。串中重复层图案的系列中的至少两个具有不同的厚度。还描述了其它垂直微电子器件和相关的制造方法。

16. 发明申请

US20050173783A1 Semiconductor package with passive device integration 有权
标题翻译：半导体封装采用无源器件集成
公开(公告)号：US20050173783A1
公开(公告)日：2005-08-11
申请号：US10773716
申请日：2004-02-05
申请人： Seng Chow , Il Shim , Ming Ying , Byung Ahn
发明人： Seng Chow , Il Shim , Ming Ying , Byung Ahn
IPC分类号： H01L21/56 , H01L21/68 , H01L21/98 , H01L23/31 , H01L23/495 , H01L25/065 , H01L25/16 , H05K3/20 , H05K3/34
CPC分类号： H01L21/568 , H01L21/56 , H01L23/3107 , H01L23/3114 , H01L23/49503 , H01L23/49548 , H01L23/49551 , H01L23/49575 , H01L23/49589 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L25/0657 , H01L25/16 , H01L25/50 , H01L2224/05554 , H01L2224/16245 , H01L2224/27013 , H01L2224/2919 , H01L2224/32145 , H01L2224/32245 , H01L2224/32257 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/49171 , H01L2224/73265 , H01L2224/83051 , H01L2224/83192 , H01L2224/8385 , H01L2224/92247 , H01L2225/0651 , H01L2225/06517 , H01L2225/06582 , H01L2924/00014 , H01L2924/01027 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19103 , H01L2924/19105 , H01L2924/19106 , H05K3/202 , H05K3/3442 , H05K2201/09745 , H05K2201/10636 , Y02P70/611 , Y02P70/613 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A system is provided for an integrated circuit package including a leadframe having a lead finger. A groove is formed in a lead finger for a conductive bonding agent and a passive device is placed in the groove to be held by the conductive bonding agent.
摘要翻译：提供一种用于集成电路封装的系统，该集成电路封装包括具有引线指的引线框架。在用于导电粘合剂的引线指中形成凹槽，并且将无源器件放置在沟槽中以由导电粘合剂保持。

17. 发明申请

US20160284419A1 NONVOLATILE MEMORY DEVICES, OPERATING METHODS THEREOF AND MEMORY SYSTEMS INCLUDING THE SAME 审中-公开
标题翻译：非易失性存储器件，其操作方法和包括其的存储器系统
公开(公告)号：US20160284419A1
公开(公告)日：2016-09-29
申请号：US15176269
申请日：2016-06-08
申请人： Sun-Il SHIM , Jae-Hoon JANG , Donghyuk CHAE , Youngho LIM , Hansoo KIM , Jaehun JEONG
发明人： Sun-Il SHIM , Jae-Hoon JANG , Donghyuk CHAE , Youngho LIM , Hansoo KIM , Jaehun JEONG
IPC分类号： G11C16/34 , G11C16/10 , G11C16/08 , G11C16/04
CPC分类号： G11C16/3459 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/12 , G11C16/14 , G11C16/26 , G11C16/3418 , H01L27/1157 , H01L27/11582
摘要： Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.
摘要翻译：非易失性存储器件，其操作方法和包括其的存储器系统。非易失性存储器件可以包括存储单元阵列和字线驱动器。存储单元阵列可以包括多个存储单元。字线驱动器可以被配置为分别将字线电压施加到连接到多个存储器单元的多个字线。字线电压的大小可以根据多个字线的位置来确定。

18. 发明申请

US20160118122A1 VERTICAL STRUCTURE SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 审中-公开
公开(公告)号：US20160118122A1
公开(公告)日：2016-04-28
申请号：US14960839
申请日：2015-12-07
申请人： Sung-Min HWANG , Han-soo KIM , Sun-il SHIM
发明人： Sung-Min HWANG , Han-soo KIM , Sun-il SHIM
IPC分类号： G11C16/04 , H01L27/02 , H01L27/115 , G11C16/26 , G11C16/08
CPC分类号： G11C16/0483 , G11C16/08 , G11C16/26 , H01L23/48 , H01L27/0207 , H01L27/088 , H01L27/11524 , H01L27/11551 , H01L27/11556 , H01L27/1157 , H01L27/11578 , H01L27/11582 , H01L29/7827 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor memory device includes: a semiconductor region extending vertically from a first region of a substrate; a plurality of gate electrodes disposed on the first region of the substrate in a vertical direction, but separated from each other along a sidewall of the semiconductor region; a gate dielectric layer disposed between the semiconductor region and the plurality of gate electrodes; a substrate contact electrode extending vertically from the impurity-doped second region of the substrate; and an insulating region formed as an air gap between the substrate contact electrode and at least one of the plurality of gate electrodes.

19. 发明申请

US20150380093A1 NON-VOLATILE MEMORY DEVICES, OPERATING METHODS THEREOF AND MEMORY SYSTEMS INCLUDING THE SAME 审中-公开
标题翻译：非易失性存储器件，其操作方法和包括其的存储器系统
公开(公告)号：US20150380093A1
公开(公告)日：2015-12-31
申请号：US14849029
申请日：2015-09-09
申请人： Sun-il SHIM , Jae-Hoon JANG , Donghyuk CHAE , Youngho LIM , Hansoo KIM , Jaehun JEONG
发明人： Sun-il SHIM , Jae-Hoon JANG , Donghyuk CHAE , Youngho LIM , Hansoo KIM , Jaehun JEONG
IPC分类号： G11C16/12 , G11C16/34 , G11C16/04
CPC分类号： G11C16/3459 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/12 , G11C16/14 , G11C16/26 , G11C16/3418 , H01L27/1157 , H01L27/11582
摘要： Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.
摘要翻译：非易失性存储器件，其操作方法和包括其的存储器系统。非易失性存储器件可以包括存储单元阵列和字线驱动器。存储单元阵列可以包括多个存储单元。字线驱动器可以被配置为分别将字线电压施加到连接到多个存储器单元的多个字线。字线电压的大小可以根据多个字线的位置来确定。

20. 发明授权

US08944312B2 Packing box 有权
标题翻译：包装盒
公开(公告)号：US08944312B2
公开(公告)日：2015-02-03
申请号：US13288186
申请日：2011-11-03
申请人： Jin Sik Won , Jung Il Shim
发明人： Jin Sik Won , Jung Il Shim
IPC分类号： B65D5/43 , B65D5/54 , B65D5/02 , B65D5/70 , B65D5/10 , B65D5/66
CPC分类号： B65D5/0254 , B65D5/10 , B65D5/6608 , B65D5/701 , Y10S206/807
摘要： A packing box includes a main body, an opening formed on one surface of the main body, left and right flaps extended from the left and right edges of the opening so as to cover the opening, a rear flap extended from the rear edge of the opening so as to be folded to the upper surfaces of the left and right flaps, an insertion flap extended from the front end of the rear flap so as to be inserted into an insertion hole, locking flaps extended from both sides of the insertion flap so as to maintain a closed state of the rear flap and unfolded to be supported by the left and right flaps after insertion of the locking flaps into the insertion hole, and fracture guide cutting lines formed at folded parts of the left and right flaps.
摘要翻译：包装箱包括主体，形成在主体的一个表面上的开口，从开口的左边缘和右边缘延伸的左右翼片以覆盖开口;后挡板，打开以便折叠到左右翼片的上表面，从后翼片的前端延伸的插入片插入到插入孔中，从插入片的两侧延伸的锁定片为了保持后挡板的关闭状态，并且在将锁定襟翼插入到插入孔中之后展开以被左右襟翼支撑，并且在左襟翼和右襟翼的折叠部分处形成断裂导向切割线。

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