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11. 发明申请

US20090080391A1 Network interworking system and method for negotiating qos in network interworking system 审中-公开
标题翻译：网络互通系统中的协商qos网络互通系统和方法
公开(公告)号：US20090080391A1
公开(公告)日：2009-03-26
申请号：US11920996
申请日：2005-11-04
申请人： Hye Yeon Kwon , Hyung-Cheol Shin , Kwang-Hyun Ro , Jae-Wook Shin , Kwang-Ryul Jung , You-Sun Hwang , Kyung-Yul Cheon , Ae-Soon Park
发明人： Hye Yeon Kwon , Hyung-Cheol Shin , Kwang-Hyun Ro , Jae-Wook Shin , Kwang-Ryul Jung , You-Sun Hwang , Kyung-Yul Cheon , Ae-Soon Park
IPC分类号： H04W74/00
CPC分类号： H04W28/24 , H04W76/15
摘要： A 3GPP-WLAN interworking system to which WLAN user equipment is accessed includes a WLAN access network including a WLAN access point, a 3GPP packet-switched service network including terminal equipment, a 3GPP core network connecting the WLAN access network and the 3GPP packet-switched service network, and a packet data gateway relaying the 3GPP core network and the 3GPP packet-switched service network. The WLAN user equipment negotiates a QoS according to a wireless environment with the WLAN access point to generate a WLAN bearer, negotiates a QoS according to a type of user data with the packet data gateway to generate a WLAN 3GPP IP access bearer, and negotiates a QoS according to data process performance of the terminal equipment with the terminal equipment to generate an end-to-end bearer.
摘要翻译：接入WLAN用户设备的3GPP-WLAN互通系统包括WLAN接入网，包括WLAN接入点，包括终端设备的3GPP分组交换业务网络，连接WLAN接入网的3GPP核心网和3GPP分组交换服务网络和中继3GPP核心网络和3GPP分组交换服务网络的分组数据网关。 WLAN用户设备根据WLAN接入点的无线环境协商QoS，生成WLAN承载，根据分组数据网关的用户数据类型协商QoS，生成WLAN 3GPP IP接入承载，并协商 QoS根据终端设备的数据处理性能与终端设备生成端到端承载。

12. 发明授权

US06563151B1 Field effect transistors having gate and sub-gate electrodes that utilize different work function materials and methods of forming same 有权
公开(公告)号：US06563151B1
公开(公告)日：2003-05-13
申请号：US09654859
申请日：2000-09-05
申请人： Hyung-cheol Shin , Jong-ho Lee , Sang-yeon Han
发明人： Hyung-cheol Shin , Jong-ho Lee , Sang-yeon Han
IPC分类号： H01L2976
CPC分类号： H01L29/66643 , H01L21/2807 , H01L21/28105 , H01L29/1083 , H01L29/4983 , H01L29/7831 , H01L29/7836
摘要： Field effect transistors include a semiconductor substrate having a channel region of first conductivity type therein extending adjacent a surface thereof. Source and drain regions of second conductivity type are also provided at opposite ends of the channel region. The source and drain regions extend in the semiconductor substrate and form P-N rectifying junctions with the channel region. A gate electrode extends on the channel region and comprises a first electrically conductive material having a first work function. A first sub-gate electrode extends on the channel region and comprises a second electrically conductive material having a second work function that is unequal to the first work function. The second electrically conductive material is preferably selected so that a difference between the second work function and a work function of the channel region is sufficient to form an inversion-layer in a portion of the channel region extending opposite the first sub-gate electrode when the first sub-gate electrode is at a zero potential bias relative to the channel region.

13. 发明申请

US20110142142A1 APPARATUS AND METHOD FOR ESTIMATING CHANNEL IN CHANNEL DOMAIN 失效
标题翻译：在通道域中估计通道的装置和方法
公开(公告)号：US20110142142A1
公开(公告)日：2011-06-16
申请号：US12967556
申请日：2010-12-14
申请人： Hye-Kyung JWA , Il-Gyu Kim , Mu-Yong Shin , Hyung-Cheol Shin , Duk-Hyun You
发明人： Hye-Kyung JWA , Il-Gyu Kim , Mu-Yong Shin , Hyung-Cheol Shin , Duk-Hyun You
IPC分类号： H04L27/00 , H04B7/00
CPC分类号： H04L25/022 , H04L25/024
摘要： A method and apparatus for estimating a channel in a frequency domain are provided. The apparatus acquires frequency selectivity information using a cell-specific reference signal, selects a channel estimation scheme using a user specific reference signal according to the acquired frequency selectivity information, and estimates a frequency channel using the selected channel estimation scheme. Accordingly, more accurate channel estimation with respect to a region to which a physical downstream shared channel is allocated can be performed.
摘要翻译：提供了一种用于估计频域中的信道的方法和装置。该装置使用小区特定参考信号获取频率选择性信息，根据获取的频率选择性信息，使用用户特定参考信号选择信道估计方案，并使用所选择的信道估计方案估计频道。因此，可以执行关于分配物理下行共享信道的区域的更准确的信道估计。

14. 发明申请

US20080094089A1 SEMICONDUCTOR PROBE HAVING EMBOSSED RESISTIVE TIP AND METHOD OF FABRICATING THE SAME 有权
标题翻译：具有可塑性电阻提示的半导体探针及其制造方法
公开(公告)号：US20080094089A1
公开(公告)日：2008-04-24
申请号：US11772441
申请日：2007-07-02
申请人： Ju-hwan JUNG , Jae-hong LEE , Hyung-cheol SHIN , Jun-soo KIM , Seung-bum HONG
发明人： Ju-hwan JUNG , Jae-hong LEE , Hyung-cheol SHIN , Jun-soo KIM , Seung-bum HONG
IPC分类号： G01R1/067 , H01L21/00
CPC分类号： G01Q60/30
摘要： A semiconductor probe having an embossed resistive tip and a method of fabricating the semiconductor probe are provided. The semiconductor probe includes a protrusion portion protruded to a predetermined height on a cantilever in a first direction crossing a length direction of the cantilever, an embossed resistive tip formed on the protrusion portion, and first and second semiconductor electrode regions formed at opposite sides of the embossed resistive tip at the protrusion portion, wherein the cantilever is doped with a first dopant, the first and second semiconductor electrode regions and the embossed resistive tip are doped with a second dopant having a different polarity from the first dopant, and the embossed resistive tip is doped with a concentration lower than the first and second semiconductor electrode regions
摘要翻译：提供具有压花电阻端头的半导体探针和制造半导体探针的方法。半导体探针包括突起部，该突起部在与悬臂的长度方向交叉的第一方向上在悬臂上突出规定的高度，形成在突出部上的压电电阻端子以及形成在突起部的相反侧的第一和第二半导体电极区域在突出部分处的压电电阻尖端，其中所述悬臂掺杂有第一掺杂剂，所述第一和第二半导体电极区域和所述压电电阻尖端掺杂有与所述第一掺杂剂具有不同极性的第二掺杂剂，并且所述压花电阻尖端掺杂浓度低于第一和第二半导体电极区域

15. 发明申请

US20070267385A1 SEMICONDUCTOR PROBE WITH HIGH RESOLUTION RESISTIVE TIP AND METHOD OF FABRICATING THE SAME 有权
标题翻译：具有高分辨率电阻提示的半导体探针及其制造方法
公开(公告)号：US20070267385A1
公开(公告)日：2007-11-22
申请号：US11835874
申请日：2007-08-08
申请人： Ju-hwan JUNG , Jun-soo Kim , Hyung-cheol Shin , Seung-bum Hong
发明人： Ju-hwan JUNG , Jun-soo Kim , Hyung-cheol Shin , Seung-bum Hong
IPC分类号： B44C1/22
CPC分类号： G01Q60/30 , G01Q60/38
摘要： A semiconductor probe with a high-resolution tip and a method of fabricating the same are provided. The semiconductor probe includes: a cantilever doped with a first impurity; a resistive convex portion projecting from an end portion of the cantilever and lightly doped with a second impurity opposite in polarity to the first impurity; and first and second electrode regions formed on either side of the resistive convex portion and heavily doped with the second impurity.
摘要翻译：提供了具有高分辨率尖端的半导体探针及其制造方法。半导体探针包括：掺杂有第一杂质的悬臂; 从所述悬臂的端部突出并轻微掺杂与所述第一杂质极性相反的第二杂质的电阻凸部; 以及第一和第二电极区域，形成在电阻凸部的任一侧上并且重掺杂有第二杂质。

16. 发明授权

US07287421B2 Semiconductor probe with high resolution resistive tip and method of fabricating the same 有权
标题翻译：具有高分辨率电阻尖端的半导体探针及其制造方法
公开(公告)号：US07287421B2
公开(公告)日：2007-10-30
申请号：US11482690
申请日：2006-07-10
申请人： Ju-hwan Jung , Jun-soo Kim , Hyung-cheol Shin , Seung-bum Hong
发明人： Ju-hwan Jung , Jun-soo Kim , Hyung-cheol Shin , Seung-bum Hong
IPC分类号： G01R31/02
CPC分类号： G01Q60/30 , G01Q60/38
摘要： A semiconductor probe with a high-resolution tip and a method of fabricating the same are provided. The semiconductor probe includes: a cantilever doped with a first impurity; a resistive convex portion projecting from an end portion of the cantilever and lightly doped with a second impurity opposite in polarity to the first impurity; and first and second electrode regions formed on either side of the resistive convex portion and heavily doped with the second impurity.
摘要翻译：提供了具有高分辨率尖端的半导体探针及其制造方法。半导体探针包括：掺杂有第一杂质的悬臂; 从所述悬臂的端部突出并轻微掺杂与所述第一杂质极性相反的第二杂质的电阻凸部; 以及第一和第二电极区域，形成在电阻凸部的任一侧上并且重掺杂有第二杂质。

17. 发明授权

US06680224B2 Methods of forming and operating field effect transistors having gate and sub-gate electrodes 有权
标题翻译：形成和操作具有栅极和子栅电极的场效应晶体管的方法
公开(公告)号：US06680224B2
公开(公告)日：2004-01-20
申请号：US10389846
申请日：2003-03-17
申请人： Hyung-cheol Shin , Jong-ho Lee , Sang-yeon Han
发明人： Hyung-cheol Shin , Jong-ho Lee , Sang-yeon Han
IPC分类号： H01L218234
CPC分类号： H01L29/66643 , H01L21/2807 , H01L21/28105 , H01L29/1083 , H01L29/4983 , H01L29/7831 , H01L29/7836
摘要： Field effect transistors include a semiconductor substrate having a channel region of first conductivity type therein extending adjacent a surface thereof. Source and drain regions of second conductivity type are also provided at opposite ends of the channel region. The source and drain regions extend in the semiconductor substrate and form P-N rectifying junctions with the channel region. A gate electrode extends on the channel region and comprises a first electrically conductive material having a first work function. A first sub-gate electrode extends on the channel region and comprises a second electrically conductive material having a second work function that is unequal to the first work function. The second electrically conductive material is preferably selected so that a difference between the second work function and a work function of the channel region is sufficient to form an inversion-layer in a portion of the channel region extending opposite the first sub-gate electrode when the first sub-gate electrode is at a zero potential bias relative to the channel region.
摘要翻译：场效应晶体管包括其中具有第一导电类型的沟道区的半导体衬底，其在其表面附近延伸。第二导电类型的源极和漏极区域也设置在沟道区域的相对端。源区和漏区在半导体衬底中延伸并与沟道区形成P-N整流结。栅电极在沟道区域上延伸并且包括具有第一功函数的第一导电材料。第一子栅极电极在沟道区域上延伸并且包括具有不等于第一功函数的第二功函数的第二导电材料。优选选择第二导电材料，使得第二功函数和沟道区的功函数之间的差足以在沟道区域的与第一子栅电极相对延伸的部分中形成反转层，当第第一子栅极电极相对于沟道区域处于零电位偏置。

18. 发明授权

US08854107B2 Integrator circuit with inverting integrator and non-inverting integrator 有权
标题翻译：具有反相积分器和非反相积分器的积分器电路
公开(公告)号：US08854107B2
公开(公告)日：2014-10-07
申请号：US13105055
申请日：2011-05-11
申请人： Oh-Jin Kwon , Il-Hyun Yun , Seon-Woong Jang , Hyung-Cheol Shin
发明人： Oh-Jin Kwon , Il-Hyun Yun , Seon-Woong Jang , Hyung-Cheol Shin
IPC分类号： G06G7/18 , G06F3/041 , G06F3/044 , G06G7/184
CPC分类号： G06G7/184 , G06F3/0416 , G06F3/044
摘要： A switched capacitor integrator circuit is disclosed. The switched capacitor integrator circuit comprises an inverting switched capacitor integrator circuit, and a non-inverting switched capacitor integrator circuit connected to the inverting switched capacitor integrator circuit. A sampling capacitor of the inverting switched capacitor integrator circuit is shared by the non-inverting switched capacitor integrator circuit.
摘要翻译：公开了一种开关电容积分电路。开关电容积分电路包括反相开关电容积分电路和连接到反相开关电容积分电路的非反相开关电容积分电路。反相开关电容积分电路的采样电容由非反相开关电容积分电路共用。

19. 发明授权

US08405133B2 Semiconductor device including graphene and method of manufacturing the semiconductor device 有权
标题翻译：包括石墨烯的半导体器件和制造半导体器件的方法
公开(公告)号：US08405133B2
公开(公告)日：2013-03-26
申请号：US13286592
申请日：2011-11-01
申请人： Hyun-jong Chung , Jae-ho Lee , Jae-hong Lee , Hyung-cheol Shin , Sun-ae Seo , Sung-hoon Lee , Jin-seong Heo , Hee-jun Yang
发明人： Hyun-jong Chung , Jae-ho Lee , Jae-hong Lee , Hyung-cheol Shin , Sun-ae Seo , Sung-hoon Lee , Jin-seong Heo , Hee-jun Yang
IPC分类号： H01L29/76
CPC分类号： H01L29/1606 , H01L29/41758 , H01L29/66477 , H01L29/778
摘要： In a semiconductor device including graphene, a gate insulating layer may be formed between a gate electrode and a graphene layer, and an interlayer insulating layer may be formed under a portion of the graphene layer under which the gate insulating layer is not formed. The gate insulating layer may include a material that has higher dielectric permittivity than the interlayer insulating layer.
摘要翻译：在包括石墨烯的半导体器件中，可以在栅电极和石墨烯层之间形成栅极绝缘层，并且可以在没有形成栅极绝缘层的石墨烯层的一部分下方形成层间绝缘层。栅极绝缘层可以包括具有比层间绝缘层更高的介电常数的材料。

20. 发明申请

US20120112250A1 Semiconductor Device Including Graphene And Method Of Manufacturing The Semiconductor Device 有权
标题翻译：包括石墨烯的半导体器件及其半导体器件的制造方法
公开(公告)号：US20120112250A1
公开(公告)日：2012-05-10
申请号：US13286592
申请日：2011-11-01
申请人： Hyun-jong Chung , Jae-ho Lee , Jae-hong Lee , Hyung-cheol Shin , Sun-ae Seo , Sung-hoon Lee , Jin-seong Heo , Hee-jun Yang
发明人： Hyun-jong Chung , Jae-ho Lee , Jae-hong Lee , Hyung-cheol Shin , Sun-ae Seo , Sung-hoon Lee , Jin-seong Heo , Hee-jun Yang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/1606 , H01L29/41758 , H01L29/66477 , H01L29/778
摘要： In a semiconductor device including graphene, a gate insulating layer may be formed between a gate electrode and a graphene layer, and an interlayer insulating layer may be formed under a portion of the graphene layer under which the gate insulating layer is not formed. The gate insulating layer may include a material that has higher dielectric permittivity than the interlayer insulating layer.
摘要翻译：在包括石墨烯的半导体器件中，可以在栅电极和石墨烯层之间形成栅极绝缘层，并且可以在没有形成栅极绝缘层的石墨烯层的一部分下方形成层间绝缘层。栅极绝缘层可以包括具有比层间绝缘层更高的介电常数的材料。

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