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11. 发明授权

US07567449B2 One-time-programmable logic bit with multiple logic elements 有权
标题翻译：具有多个逻辑元件的一次可编程逻辑位
公开(公告)号：US07567449B2
公开(公告)日：2009-07-28
申请号：US11588775
申请日：2006-10-27
申请人： Sunhom Paak , Hsung Jai Im , Boon Yong Ang
发明人： Sunhom Paak , Hsung Jai Im , Boon Yong Ang
IPC分类号： G11C17/00
CPC分类号： G11C17/18 , H01L23/5252 , H01L23/5256 , H01L27/101 , H01L27/105 , H01L27/112 , H01L27/11206 , H01L27/11286 , H01L27/11807 , H01L2924/0002 , H01L2924/00
摘要： A memory cell with a logic bit has a first one-time-programmable (“OTP”) memory element providing a first OTP memory element output and a second OTP memory element providing a second OTP memory element output. A logic operator coupled to the first OTP memory element output and to the second OTP memory element output and provides a binary memory output of the memory cell. In a particular embodiment, the first OTP memory element is a different type of OTP memory than the second OTP memory element.
摘要翻译：具有逻辑位的存储器单元具有提供第一OTP存储器元件输出的第一一次可编程（“OTP”）存储器元件和提供第二OTP存储器元件输出的第二OTP存储器元件。耦合到第一OTP存储器元件输出和第二OTP存储器元件输出的逻辑运算器，并提供存储器单元的二进制存储器输出。在特定实施例中，第一OTP存储器元件是与第二OTP存储器元件不同类型的OTP存储器。

12. 发明授权

US07501879B1 eFuse resistance sensing scheme with improved accuracy 有权
标题翻译： eFuse电阻传感方案具有提高的精度
公开(公告)号：US07501879B1
公开(公告)日：2009-03-10
申请号：US11717836
申请日：2007-03-13
申请人： Kwansuhk Oh , Raymond C. Pang , Hsung Jai Im , Sunhom Paak
发明人： Kwansuhk Oh , Raymond C. Pang , Hsung Jai Im , Sunhom Paak
IPC分类号： G11C17/18 , H01H85/00
CPC分类号： G11C17/16 , G11C17/18
摘要： An eFuse sensing circuit replaces the inverters used to provide the “read” output state of a conventional eFuse circuit. The sensing circuit includes a comparator with one input coupled to the eFuse circuitry, and a second input coupled to a reference voltage generator circuit. The reference voltage generator circuit includes an internal resistor. Transistors of the sense circuit are provided to mimic the transistors of the eFuse circuit, so that variations of transistors due to process, voltage and temperature will be substantially the same. The resistor of the sense circuit is then effectively compared with the resistance of the eFuse by the comparator irrespective of temperature and process variations.
摘要翻译： eFuse感测电路取代了用于提供常规eFuse电路的“读取”输出状态的逆变器。感测电路包括具有耦合到eFuse电路的一个输入和耦合到参考电压发生器电路的第二输入的比较器。参考电压发生器电路包括内部电阻器。提供感测电路的晶体管以模拟eFuse电路的晶体管，使得由于工艺，电压和温度而导致的晶体管的变化将基本相同。然后将感测电路的电阻与比较器的eFuse的电阻进行有效的比较，而与温度和工艺变化无关。

13. 发明授权

US07688639B1 CMOS-compatible non-volatile memory cell with lateral inter-poly programming layer 失效
标题翻译： CMOS兼容非易失性存储单元，具有横向多层间编程层
公开(公告)号：US07688639B1
公开(公告)日：2010-03-30
申请号：US11974361
申请日：2007-10-12
申请人： Sunhom Paak , Boon Yong Ang , Hsung Jai Im , Daniel Gitlin
发明人： Sunhom Paak , Boon Yong Ang , Hsung Jai Im , Daniel Gitlin
IPC分类号： G11C16/06
CPC分类号： H01L21/28282 , G11C16/0466 , H01L29/66833
摘要： An electrically erasable programmable read-only memory (“CMOS NON-VOLATILE MEMORY”) cell is fabricated using standard CMOS fabrication processes. First and second polysilicon gates are patterned over an active area of the cell between source and drain regions. Thermal oxide is grown on the polysilicon gates to provide an isolating layer. Silicon nitride is deposited between the first and second polysilicon gates to form a lateral programming layer.
摘要翻译：使用标准CMOS制造工艺制造电可擦除可编程只读存储器（“CMOS NON-VOLATILE MEMORY”）单元。第一和第二多晶硅栅极在源极和漏极区域之间的电池的有源区域上被图案化。在多晶硅栅极上生长热氧化物以提供隔离层。氮化硅沉积在第一和第二多晶硅栅极之间以形成横向编程层。

14. 发明申请

US20090224323A1 INTEGRATED CIRCUIT WITH MOSFET FUSE ELEMENT 有权
标题翻译：集成电路与MOSFET保险丝元件
公开(公告)号：US20090224323A1
公开(公告)日：2009-09-10
申请号：US12043914
申请日：2008-03-06
申请人： Hsung Jai Im , Sunhom Paak , Boon Yong Ang
发明人： Hsung Jai Im , Sunhom Paak , Boon Yong Ang
IPC分类号： H01L23/62 , H01L21/336
CPC分类号： H01L27/101 , G11C17/16 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： At least one MOS parameter of a MOS fuse is characterized to provide at least one MOS parameter reference value. Then, the MOS fuse is programmed by applying a programming signal to the fuse terminals so that programming current flows through the fuse link. The fuse resistance is measured to provide a measured fuse resistance associated with a first logic value. A MOS parameter of the programmed MOS fuse is measured to provide a measured MOS parameter value. The measured MOS parameter value is compared to the reference MOS parameter value to determine a second logic value of the MOS fuse, and a bit value is output based on the comparison.
摘要翻译： MOS熔丝的至少一个MOS参数的特征在于提供至少一个MOS参数参考值。然后，通过向熔丝端子施加编程信号来编程MOS熔丝，使得编程电流流过熔丝链。测量熔丝电阻以提供与第一逻辑值相关联的测量的熔丝电阻。测量编程的MOS保险丝的MOS参数，以提供测量的MOS参数值。将测量的MOS参数值与参考MOS参数值进行比较，以确定MOS熔丝的第二逻辑值，并且基于比较输出位值。

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