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11. 发明授权

US08237148B2 4F2 self align side wall active phase change memory 有权
标题翻译： 4F2自对准侧壁有源相变存储器
公开(公告)号：US08237148B2
公开(公告)日：2012-08-07
申请号：US12792604
申请日：2010-06-02
申请人： Hsiang-Lan Lung
发明人： Hsiang-Lan Lung
IPC分类号： H01L47/00
CPC分类号： G11C13/0007 , B82Y10/00 , G11C11/5664 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0014 , G11C13/0016 , G11C2213/31 , G11C2213/32 , G11C2213/79 , H01L27/2436 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/124 , H01L45/14 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/1625 , H01L45/1641 , H01L45/1691
摘要： Arrays of memory cells are described along with devices thereof and method for manufacturing. Memory cells described herein include self-aligned side wall memory members comprising an active programmable resistive material. In preferred embodiments the area of the memory cell is 4F2, F being the feature size for a lithographic process used to manufacture the memory cell, and more preferably F being equal to a minimum feature size. Arrays of memory cells described herein include memory cells arranged in a cross point array, the array having a plurality of word lines and source lines arranged in parallel in a first direction and having a plurality of bit lines arranged in parallel in a second direction perpendicular to the first direction.
摘要翻译：描述存储器单元的阵列及其装置及其制造方法。本文所述的存储单元包括自对准侧壁存储器构件，其包括有源可编程电阻材料。在优选实施例中，存储单元的面积为4F2，F为用于制造存储单元的光刻工艺的特征尺寸，更优选地，F等于最小特征尺寸。本文描述的存储器单元的阵列包括布置在交叉点阵列中的存储单元，该阵列具有多个字线和源极线，其沿第一方向平行布置，并且具有沿与第一方向垂直的第二方向平行布置的多个位线第一个方向。

12. 发明申请

US20120181599A1 LOW COST SCALABLE 3D MEMORY 有权
标题翻译：低成本可扩展3D内存
公开(公告)号：US20120181599A1
公开(公告)日：2012-07-19
申请号：US13070323
申请日：2011-03-23
申请人： HSIANG-LAN LUNG
发明人： HSIANG-LAN LUNG
IPC分类号： H01L29/792 , H01L21/28
CPC分类号： H01L27/11578 , H01L27/11582 , H01L29/792
摘要： An integrated circuit device is described that includes a 3D memory comprising a plurality of self-aligned stacks of word lines orthogonal to and interleaved with a plurality of self-aligned stacks of bit lines. Data storage structures such as dielectric charge storage structures, are provided at cross points between word lines and bit lines in the plurality of self-aligned stacks of word lines interleaved with the plurality of self-aligned stacks of bit lines.
摘要翻译：描述了一种集成电路装置，其包括3D存储器，该3D存储器包括多个自对准堆叠的字线，其与多个自对准堆叠的位线正交并交错。诸如介电电荷存储结构之类的数据存储结构被提供在与多条自对准堆叠的位线交错的字线的多个自对齐堆叠中的字线和位线之间的交叉点处。

13. 发明授权

US08178386B2 Phase change memory cell array with self-converged bottom electrode and method for manufacturing 有权
标题翻译：具有自会聚底电极的相变存储单元阵列及其制造方法
公开(公告)号：US08178386B2
公开(公告)日：2012-05-15
申请号：US11855983
申请日：2007-09-14
申请人： Hsiang-Lan Lung , Chung Hon Lam , Matthew J. Breitwisch
发明人： Hsiang-Lan Lung , Chung Hon Lam , Matthew J. Breitwisch
IPC分类号： H01L21/06
CPC分类号： H01L45/144 , H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/1625 , H01L45/1641 , H01L45/1675
摘要： An array of phase change memory cells is manufactured by forming a separation layer over an array of contacts, forming a patterning layer on the separation layer and forming an array of mask openings in the patterning layer using lithographic process. Etch masks are formed within the mask openings by a process that compensates for variation in the size of the mask openings that result from the lithographic process. The etch masks are used to etch through the separation layer to define an array of electrode openings exposing the underlying contacts. Electrode material is deposited within the electrode openings; and memory elements are formed over the bottom electrodes. Finally, bit lines are formed over the memory elements to complete the memory cells. In the resulting memory array, the critical dimension of the top surface of bottom electrode varies less than the width of the memory elements in the mask openings.
摘要翻译：通过在触点阵列上形成分离层，在分离层上形成图形层并使用光刻工艺在图案形成层中形成掩模开口阵列来制造相变存储器单元的阵列。通过补偿由平版印刷工艺产生的掩模开口的尺寸变化的过程，在掩模开口内形成蚀刻掩模。蚀刻掩模用于蚀刻通过分离层以限定暴露下面的触点的电极开口的阵列。电极材料沉积在电极开口内; 并且存储元件形成在底部电极上。最后，在存储器元件上形成位线以完成存储器单元。在所得到的存储器阵列中，底部电极的顶表面的临界尺寸小于掩模开口中存储元件的宽度。

14. 发明授权

US08154128B2 3D integrated circuit layer interconnect 有权
标题翻译： 3D集成电路层互连
公开(公告)号：US08154128B2
公开(公告)日：2012-04-10
申请号：US12579192
申请日：2009-10-14
申请人： Hsiang-Lan Lung
发明人： Hsiang-Lan Lung
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L23/522 , H01L27/0207 , H01L27/0688 , H01L27/105 , H01L27/1052 , H01L27/11206 , H01L27/11286 , H01L2924/0002 , H01L2924/00
摘要： A three-dimensional 3D interconnect structure with a small footprint is described, useful for connection from above to levels of circuit structures in a multi-level device. Also, an efficient and low cost method for manufacturing the 3D interconnect structure is provided.
摘要翻译：描述了具有小占地面积的三维3D互连结构，其用于从多层设备中的上述电路结构层次的连接。另外，提供了用于制造3D互连结构的有效且低成本的方法。

15. 发明授权

US08143612B2 Phase change memory cell in via array with self-aligned, self-converged bottom electrode and method for manufacturing 有权
标题翻译：具有自对准，自会聚底电极的通孔阵列中的相变存储单元及其制造方法
公开(公告)号：US08143612B2
公开(公告)日：2012-03-27
申请号：US12621000
申请日：2009-11-18
申请人： Hsiang-Lan Lung , Chung Hon Lam
发明人： Hsiang-Lan Lung , Chung Hon Lam
IPC分类号： H01L29/06
CPC分类号： H01L45/144 , H01L27/2436 , H01L45/06 , H01L45/122 , H01L45/1253 , H01L45/1625 , H01L45/1641 , H01L45/1683
摘要： An array of “mushroom” style phase change memory cells is manufactured by forming a separation layer over an array of contacts, forming an isolation layer on the separation layer and forming an array of memory element openings in the isolation layer using a lithographic process. Etch masks are formed within the memory element openings by a process that compensates for variation in the size of the memory element openings that results from the lithographic process. The etch masks are used to etch through the separation layer to define an array of electrode openings. Electrode material is deposited within the electrode openings; and memory elements are formed within the memory element openings. The memory elements and bottom electrodes are self-aligned.
摘要翻译：通过在触点阵列上形成分离层，在分离层上形成隔离层并使用光刻工艺在隔离层中形成阵列的存储元件开口来制造“蘑菇”型相变存储器单元的阵列。通过补偿由光刻工艺产生的存储元件开口的尺寸变化的过程，在存储元件开口内形成蚀刻掩模。蚀刻掩模用于蚀刻穿过分离层以限定电极开口的阵列。电极材料沉积在电极开口内; 并且存储元件形成在存储元件开口内。存储元件和底部电极是自对准的。

16. 发明授权

US08101938B2 Method of forming a chalcogenide memory cell having an ultrasmall cross-sectional area and a chalcogenide memory cell produced by the method 有权
标题翻译：形成具有超小横截面积的硫族化物记忆体的方法和通过该方法制备的硫族化物记忆体
公开(公告)号：US08101938B2
公开(公告)日：2012-01-24
申请号：US11903236
申请日：2007-09-20
申请人： Hsiang-Lan Lung
发明人： Hsiang-Lan Lung
IPC分类号： H01L29/04 , H01L29/06 , H01L47/00 , H01L23/52 , G11C17/00 , G11C11/00
CPC分类号： H01L27/24 , G11C11/5678 , G11C13/0004 , G11C2213/72
摘要： A method of fabricating a chalcogenide memory cell is described. The cross-sectional area of a chalcogenide memory element within the cell is controlled by the thickness of a bottom electrode and the width of a word line. The method allows the formation of ultra small chalcogenide memory cells.
摘要翻译：描述了制造硫族化物记忆体的方法。单元内的硫族化物存储元件的横截面面积由底部电极的厚度和字线的宽度来控制。该方法允许形成超小型硫族化物记忆细胞。

17. 发明授权

US08093661B2 Integrated circuit device with single crystal silicon on silicide and manufacturing method 有权
标题翻译：硅化硅单晶硅集成电路器件及其制造方法
公开(公告)号：US08093661B2
公开(公告)日：2012-01-10
申请号：US12349903
申请日：2009-01-07
申请人： Hsiang-Lan Lung , Erh-Kun Lai
发明人： Hsiang-Lan Lung , Erh-Kun Lai
IPC分类号： H01L29/86 , H01L21/334
CPC分类号： H01L27/1021 , H01L21/743 , H01L27/105 , H01L29/7827 , H01L29/861
摘要： A silicide element separates a single crystal silicon node from an underlying silicon substrate, and is capable of acting as a conductive element for interconnecting devices on the device. The single crystal silicon node can act as one terminal of a diode, and a second semiconductor node on top of it can act as the other terminal of the diode. The single crystal silicon node can act as one of the terminals of the transistor, and second and third semiconductor nodes are formed in series on top of it, providing a vertical transistor structure, which can be configured as a field effect transistor or bipolar junction transistor. The silicide element can be formed by a process that consumes a base of a protruding single crystal element by silicide formation processes, while shielding upper portions of the protruding element from the silicide formation process.
摘要翻译：硅化物元件将单晶硅节点与底层硅衬底分开，并且能够用作用于互连器件上的器件的导电元件。单晶硅节点可以作为二极管的一个端子，其顶部的第二个半导体节点可以作为二极管的另一个端子。单晶硅节点可以用作晶体管的端子之一，并且第二和第三半导体节点在其顶部上串联形成，提供垂直晶体管结构，其可被配置为场效应晶体管或双极结型晶体管。硅化物元件可以通过利用硅化物形成工艺消耗突出的单晶元件的基底，同时屏蔽突出元件的上部从硅化物形成工艺形成的工艺。

18. 发明授权

US08089137B2 Integrated circuit memory with single crystal silicon on silicide driver and manufacturing method 有权
标题翻译：集成电路存储器采用单晶硅硅化硅驱动器及制造方法
公开(公告)号：US08089137B2
公开(公告)日：2012-01-03
申请号：US12349874
申请日：2009-01-07
申请人： Hsiang-Lan Lung , Erh-Kun Lai
发明人： Hsiang-Lan Lung , Erh-Kun Lai
IPC分类号： H01L27/10 , H01L29/861 , H01L21/324
CPC分类号： H01L45/1675 , G11C13/0004 , G11C2213/72 , H01L27/1021 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/142 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/1625 , H01L45/1641 , H01L45/1683
摘要： A memory device includes a diode driver and a data storage element, such as an element comprising phase change memory material, and in which the diode driver comprises a silicide element on a silicon substrate with a single crystal silicon node on the silicide element. The silicide element separates the single crystal silicon node from the underlying silicon substrate, preventing the flow of carriers from the single crystal silicon node into the substrate, and is capable of acting as a conductive element for interconnecting devices on the device. The single crystal silicon node acts as one terminal of a diode, and a second semiconductor node is formed on top of it, acting as the other terminal of the diode.
摘要翻译：存储器件包括二极管驱动器和诸如包括相变存储器材料的元件的数据存储元件，并且其中二极管驱动器在硅衬底上包括在硅化物元件上具有单晶硅节点的硅化物元件。硅化物元件将单晶硅节点与下面的硅衬底分开，防止载体从单晶硅节点流入衬底，并且能够用作用于互连器件上的器件的导电元件。单晶硅节点用作二极管的一个端子，第二半导体节点形成在二极管的顶部，充当二极管的另一个端子。

19. 发明授权

US08064248B2 2T2R-1T1R mix mode phase change memory array 有权
标题翻译： 2T2R-1T1R混合模式相变存储器阵列
公开(公告)号：US08064248B2
公开(公告)日：2011-11-22
申请号：US12561556
申请日：2009-09-17
申请人： Hsiang-Lan Lung
发明人： Hsiang-Lan Lung
IPC分类号： G11C11/00
CPC分类号： G11C7/1045 , G11C7/067 , G11C13/0004 , G11C13/0026 , G11C13/004 , G11C2013/0042 , G11C2013/0054
摘要： A memory device as described herein includes an array of programmable resistance memory cells. The memory device further includes sense circuitry having a dual memory cell (2T-2R) mode to read a data value stored in a pair of memory cells in the array based on a difference in resistance between a first memory cell in the pair and a second memory cell in the pair. The sense circuitry also has a single memory cell (1T-1R) mode to read a data value in a particular memory cell in the array based on the resistance of the particular memory cell.
摘要翻译：如本文所述的存储器件包括可编程电阻存储器单元的阵列。存储装置还包括具有双存储单元（2T-2R）模式的感测电路，该模式基于该对中的第一存储单元之间的电阻差来读取阵列中存储在一对存储单元中的数据值，存储单元在对。感测电路还具有单个存储器单元（1T-1R）模式，以基于特定存储器单元的电阻来读取阵列中的特定存储器单元中的数据值。

20. 发明授权

US08030635B2 Polysilicon plug bipolar transistor for phase change memory 有权
标题翻译：用于相变存储器的多晶硅插头双极晶体管
公开(公告)号：US08030635B2
公开(公告)日：2011-10-04
申请号：US12353219
申请日：2009-01-13
申请人： Hsiang-Lan Lung , Erh-Kun Lai , Bipin Rajendran , Chung Hon Lam
发明人： Hsiang-Lan Lung , Erh-Kun Lai , Bipin Rajendran , Chung Hon Lam
IPC分类号： H01L29/02
CPC分类号： H01L45/04 , G11C13/0004 , H01L27/1026 , H01L27/2445 , H01L27/2463 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/142 , H01L45/144 , H01L45/146 , H01L45/1625 , H01L45/1641 , H01L45/1675 , H01L45/1683
摘要： Memory devices and methods for manufacturing are described herein. A memory device described herein includes a plurality of memory cells. Memory cells in the plurality of memory cells comprise respective bipolar junction transistors and memory elements. The bipolar junction transistors are arranged in a common collector configuration and include an emitter comprising doped polysilicon having a first conductivity type, the emitter contacting a corresponding word line in a plurality of word lines to define a pn junction. The bipolar junction transistors include a portion of the corresponding word line underlying the emitter acting as a base, and a collector comprising a portion of the single-crystalline substrate underlying the base.
摘要翻译：本文描述了存储器件和制造方法。本文描述的存储器件包括多个存储器单元。多个存储单元中的存储单元包括相应的双极结型晶体管和存储元件。双极结晶体管被布置成共同的集电极配置，并且包括发射器，其包括具有第一导电类型的掺杂多晶硅，发射极与多个字线中的对应字线接触以限定pn结。双极结晶体管包括作为基极的发射极下面的相应字线的一部分，以及包含基底下方的单晶衬底的一部分的集电极。

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