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11. 发明授权

US06721878B1 Low-latency interrupt handling during memory access delay periods in microprocessors 有权
标题翻译：微处理器内存访问延迟期间的低延迟中断处理
公开(公告)号：US06721878B1
公开(公告)日：2004-04-13
申请号：US09594218
申请日：2000-06-14
申请人： Somnath Paul , Gregory H. Efland
发明人： Somnath Paul , Gregory H. Efland
IPC分类号： G06F1300
CPC分类号： G06F13/24
摘要： A method and processor configured to handle an exception may employ a “retry” signal, which may be associated with a memory access attempt by the processor. The retry signal determines if an exception is to be serviced during a period in which the memory access is delayed. In one embodiment for which the exception is an interrupt, the retry signal is asserted when memory access is delayed and the processor may proceed to service an interrupt request during this period of delayed memory access, regardless of the degree of completion of an instruction by the processor. During a period of delayed memory access, the processor may suspend instruction execution until the memory access becomes available. Upon completion of servicing the interrupt, the processor may resume instruction execution beginning with the last instruction attempted before the suspension of the instruction execution due to the delayed memory access. In one embodiment, the processor may include interrupt handling logic to enable initiation of interrupt service in response to an interrupt request and may further include address selection logic to select an instruction address associated with a delayed memory access.
摘要翻译：配置成处理异常的方法和处理器可以采用可以与处理器的存储器访问尝试相关联的“重试”信号。重试信号确定在存储器访问被延迟的时段期间是否要处理异常。在异常是中断的一个实施例中，当存储器访问被延迟时，重试信号被断言，并且处理器可以在延迟存储器访问的该周期期间继续服务中断请求，而不管由什么程度的指令完成处理器。在延迟存储器访问期间，处理器可以暂停指令执行，直到存储器存取可用。在中断服务完成后，由于延迟的存储器访问，处理器可以在暂停指令执行之前尝试的最后一条指令开始执行指令执行。在一个实施例中，处理器可以包括中断处理逻辑，以响应于中断请求启动中断服务，并且还可以包括地址选择逻辑以选择与延迟存储器访问相关联的指令地址。

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