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11. 发明授权

US07711537B2 Signals for simulation result viewing 失效
标题翻译：用于模拟结果查看的信号
公开(公告)号：US07711537B2
公开(公告)日：2010-05-04
申请号：US11381437
申请日：2006-05-03
申请人： Gabor Bobok , Wolfgang Roesner , Derek E. Williams
发明人： Gabor Bobok , Wolfgang Roesner , Derek E. Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： According to a method of data processing, a data set including at least one entry specifying a signal group by a predetermined signal group name is received by a data processing system. In response to receipt of the data set, the entry in the data set is processed to identify the signal group name. Signal group information associated with an event trace file containing simulation results is accessed to determine signal names of multiple signals that are members of the signal group. Simulation results from the event trace file that are associated with instances of the multiple signals are then included within a presentation of simulation results.
摘要翻译：根据数据处理的方法，由数据处理系统接收包括由预定信号组名称指定信号组的至少一个条目的数据集。响应于数据集的接收，处理数据集中的条目以识别信号组名称。与包含模拟结果的事件跟踪文件相关联的信号组信息被访问以确定作为信号组成员的多个信号的信号名称。然后将与多个信号的实例相关联的事件跟踪文件的仿真结果包含在仿真结果的呈现中。

12. 发明授权

US07617085B2 Program product supporting specification of signals for simulation result viewing 失效
标题翻译：程序产品支持模拟结果查看信号的规范
公开(公告)号：US07617085B2
公开(公告)日：2009-11-10
申请号：US12129813
申请日：2008-05-30
申请人： Gabor Bobok , Wolfgang Roesner , Derek E. Williams
发明人： Gabor Bobok , Wolfgang Roesner , Derek E. Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： According to a method of data processing, a data set including at least one entry specifying a signal group by a predetermined signal group name is received by a data processing system. In response to receipt of the data set, the entry in the data set is processed to identify the signal group name. Signal group information associated with an event trace file containing simulation results is accessed to determine signal names of multiple signals that are members of the signal group. Simulation results from the event trace file that are associated with instances of the multiple signals are then included within a presentation of simulation results.
摘要翻译：根据数据处理的方法，由数据处理系统接收包括由预定信号组名称指定信号组的至少一个条目的数据集。响应于数据集的接收，处理数据集中的条目以识别信号组名称。与包含模拟结果的事件跟踪文件相关联的信号组信息被访问以确定作为信号组成员的多个信号的信号名称。然后将与多个信号的实例相关联的事件跟踪文件的仿真结果包含在仿真结果的呈现中。

13. 发明授权

US07506287B2 Method, system, and program product for pre-compile processing of hardware design language (HDL) source files 失效
标题翻译：方法，系统和程序产品，用于硬件设计语言（HDL）源文件的预编译处理
公开(公告)号：US07506287B2
公开(公告)日：2009-03-17
申请号：US11521917
申请日：2006-09-16
申请人： Gabor Drasny , Gabor Bobok , Ali El-Zein , Fadi Zaraket , Hussein Sharafeddin
发明人： Gabor Drasny , Gabor Bobok , Ali El-Zein , Fadi Zaraket , Hussein Sharafeddin
IPC分类号： G06F17/50
CPC分类号： G06F11/3664 , G06F8/447
摘要： A method includes pre-compilation operations on HDL source code files, creating a “make it” file, on demand processing of the HDL source code in an HDL source browser, and resolving overloaded function and operator calls in an HDL source code browser debugger. Construct a list of all HDL files a list of HDL files to be processed. Send an HDL file in the list for compiling. If compilation is successful, branch to add the HDL file to an end of target file and that HDL file is removed from the list. The list is tested for remaining files and then a next file in the list is sent for compiling. After all files in the list have been processed, the HDL files which have been processed are checked for failures to compile and if any of said HDL files to be processed have failed to compile the method branches back to repeating the process until all runs are successful.
摘要翻译：一种方法包括对HDL源代码文件进行预编译操作，在HDL源浏览器中创建“make it”文件，按需处理HDL源代码，并在HDL源代码浏览器调试器中解析重载函数和操作符调用。构建所有HDL文件的列表，列出要处理的HDL文件。在列表中发送一个HDL文件进行编译。如果编译成功，请将HDL文件添加到目标文件的末尾，并从列表中删除该HDL文件。该列表被测试剩余的文件，然后发送列表中的下一个文件进行编译。在处理列表中的所有文件之后，检查已处理的HDL文件，以便编译失败，并且如果要处理的所有HDL文件中的任何一个无法编译方法分支回到重复进程，直到所有运行成功。

14. 发明申请

US20080294413A1 PROGRAM PRODUCT SUPPORTING PHASE EVENTS IN A SIMULATION MODEL OF A DIGITAL SYSTEM 失效
标题翻译：在数字系统仿真模型中支持相关事件的程序产品
公开(公告)号：US20080294413A1
公开(公告)日：2008-11-27
申请号：US12130104
申请日：2008-05-30
申请人： GABOR BOBOK , Wolfgang Roesner , Derek E. Williams
发明人： GABOR BOBOK , Wolfgang Roesner , Derek E. Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： According to a method of simulation processing, an instrumented simulation executable model of a design is built by compiling one or more hardware description language (HDL) files specifying one or more design entities within the design and one or more instrumentation entities and instantiating instances of the one or more instrumentation entities within instances of the one or more design entities. Operation of the design is then simulated utilizing the instrumented simulation executable model. Simulating operation includes each of multiple instantiations of the one or more instrumentation entities generating a respective external phase signal representing an occurrence of a particular phase of operation and instrumentation combining logic generating from external phase signals of the multiple instantiations of the one or more instrumentation entities an aggregate phase signal representing an occurrence of the particular phase.
摘要翻译：根据模拟处理的方法，通过编译指定设计中的一个或多个设计实体的一个或多个硬件描述语言（HDL）文件和一个或多个设备实体和一个或多个设备实例的实例化来构建设计的仪器化模拟可执行模型在一个或多个设计实体的实例内的一个或多个仪表实体。然后使用仪器化模拟可执行模型对设计的操作进行模拟。模拟操作包括一个或多个仪器实体的多个实例中的每个实例，其产生表示特定操作阶段的出现的相应的外部相位信号，以及组合从一个或多个仪器实体的多个实例的外部相位信号产生的逻辑聚合相位信号表示特定相位的出现。

15. 发明申请

US20080072206A1 Unrolling Hardware Design Generate Statements in a Source Window Debugger 有权
标题翻译：展开硬件设计在源窗口生成语句调试器
公开(公告)号：US20080072206A1
公开(公告)日：2008-03-20
申请号：US11532216
申请日：2006-09-15
申请人： Gabor Drasny , Gabor Bobok , Ali El-Zein , Fadi Zaraket
发明人： Gabor Drasny , Gabor Bobok , Ali El-Zein , Fadi Zaraket
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5022
摘要： Unrolling the “generate” statement of a hardware description language (“HDL”) and displaying the unrolled HDL. For a conditional generate the condition is evaluated. If the statement is true the enclosed HDL code will be displayed. For an iterative generate, the enclosing HDL will be displayed as many times as specified by the bounds of the iteration scheme. This allows, for example, simulation value annotations for signals declared inside the generate statement, semantic navigation inside the generate statements, and allows the user to visualize what is included in the target design.
摘要翻译：展开硬件描述语言（“HDL”）的“生成”语句并显示展开的HDL。对于条件生成条件进行评估。如果声明为真，则将显示附带的HDL代码。对于迭代生成，封闭的HDL将被显示为迭代方案边界所指定的次数。这允许例如生成语句内声明的信号的模拟值注释，生成语句内的语义导航，并允许用户可视化目标设计中包含的内容。

16. 发明授权

US08160857B2 Selective compilation of a simulation model in view of unavailable higher level signals 有权
标题翻译：鉴于不可用的较高电平信号，可选择地编译仿真模型
公开(公告)号：US08160857B2
公开(公告)日：2012-04-17
申请号：US12336019
申请日：2008-12-16
申请人： Gabor Bobok , Wolfgang Roesner , Derek E. Williams
发明人： Gabor Bobok , Wolfgang Roesner , Derek E. Williams
IPC分类号： G06F9/455
CPC分类号： G06F17/5022
摘要： In response to receiving HDL file(s) that specify a plurality of hierarchically arranged design entities defining a design to be simulated and that specify an instrumentation entity for monitoring simulated operation of the design, an instrumented simulation executable model of the design is built. Building the model includes compiling the HDL file(s) specifying the plurality of hierarchically arranged design entities defining the design and instantiating at least one instance of each of the plurality of hierarchically arranged design entities, and further includes instantiating an instance of the instrumentation entity within an instance of a particular design entity among the plurality of design entities and, based upon a reference in an instrumentation statement in the one or more HDL files, logically attaching an input of the instance of the instrumentation entity to an input source within the design that is outside the scope of the particular design entity.
摘要翻译：响应于接收到指定多个分层布置的设计实体的定义待仿真设计的HDL文件，并指定用于监视设计的模拟操作的仪器实体，构建了该设计的仪表化仿真可执行模型。构建模型包括编译指定定义设计的多个分层布置的设计实体的HDL文件，并且实例化多个分级排列的设计实体中的每一个的至少一个实例，并且还包括实例化所述多个分层布置设计实体内的所述检测实体的实例所述多个设计实体中的特定设计实体的实例，并且基于所述一个或多个HDL文件中的检测语句中的引用，将所述检测实体的实例的输入逻辑地附加到所述设计中的输入源，不在特定设计实体的范围之内。

17. 发明授权

US07823097B2 Unrolling hardware design generate statements in a source window debugger 有权
标题翻译：展开硬件设计在源窗口调试器中生成语句
公开(公告)号：US07823097B2
公开(公告)日：2010-10-26
申请号：US11532216
申请日：2006-09-15
申请人： Gabor Drasny , Gabor Bobok , Ali El-Zein , Fadi Zaraket
发明人： Gabor Drasny , Gabor Bobok , Ali El-Zein , Fadi Zaraket
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5022
摘要： Unrolling the “generate” statement of a hardware description language (“HDL”) and displaying the unrolled HDL. For a conditional generate the condition is evaluated. If the statement is true the enclosed HDL code will be displayed. For an iterative generate, the enclosing HDL will be displayed as many times as specified by the bounds of the iteration scheme. This allows, for example, simulation value annotations for signals declared inside the generate statement, semantic navigation inside the generate statements, and allows the user to visualize what is included in the target design.
摘要翻译：展开硬件描述语言（“HDL”）的“生成”语句并显示展开的HDL。对于条件生成条件进行评估。如果声明为真，则将显示附带的HDL代码。对于迭代生成，封闭的HDL将被显示为迭代方案边界所指定的次数。这允许例如生成语句内声明的信号的模拟值注释，生成语句内的语义导航，并允许用户可视化目标设计中包含的内容。

18. 发明申请

US20100223584A1 Logic Design Verification Techniques for Liveness Checking With Retiming 有权
标题翻译：逻辑设计验证技术，用于重新定义活动检查
公开(公告)号：US20100223584A1
公开(公告)日：2010-09-02
申请号：US12394560
申请日：2009-02-27
申请人： Jason R. Baumgartner , Gabor Bobok , Paul Joseph Roessler , Mark Williams
发明人： Jason R. Baumgartner , Gabor Bobok , Paul Joseph Roessler , Mark Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/504 , G06F2217/84
摘要： A technique for verification of a retimed logic design using liveness checking includes assigning a liveness gate to a liveness property for an original netlist and assigning a fairness gate to a fairness constraint for the original netlist. In this case, the fairness gate is associated with the liveness gate and is asserted for at least one time-step during any valid behavioral loop associated with the liveness gate. The original netlist is retimed, using a retiming engine, to provide a retimed netlist. The liveness and fairness gates of the retimed netlist are retimed such that a lag of the fairness gate is no greater than a lag of the liveness gate. Verification analysis is then performed on the retimed netlist. Finally, when the verification analysis yields a valid counter-example trace for the retimed netlist, a liveness violation for the original netlist is returned.
摘要翻译：用于使用活动检查验证重新定时逻辑设计的技术包括将活跃门分配给原始网表的活动属性，并将公平门分配给原始网表的公平约束。在这种情况下，公平门与活跃门相关联，并且在与活跃门相关联的任何有效行为循环期间被断言至少一个时间步长。使用重新定时引擎重新计算原始网表，以提供重新定时的网表。重新定义的网表的活跃和公平的门被重新定位，使得公平门的滞后不大于活跃门的滞后。然后在重新定时的网表上进行验证分析。最后，当验证分析为重新定时的网表产生有效的对照示例时，返回原始网表的活动违反。

19. 发明申请

US20080229193A1 PROGRAM PRODUCT SUPPORTING SPECIFICATION OF SIGNALS FOR SIMULATION RESULT VIEWING 失效
标题翻译：支持模拟结果查询信号规范的程序产品
公开(公告)号：US20080229193A1
公开(公告)日：2008-09-18
申请号：US12129813
申请日：2008-05-30
申请人： GABOR BOBOK , Wolfgang Roesner , Derek E. Williams
发明人： GABOR BOBOK , Wolfgang Roesner , Derek E. Williams
IPC分类号： G06F17/00
CPC分类号： G06F17/5022
摘要： According to a method of data processing, a data set including at least one entry specifying a signal group by a predetermined signal group name is received by a data processing system. In response to receipt of the data set, the entry in the data set is processed to identify the signal group name. Signal group information associated with an event trace file containing simulation results is accessed to determine signal names of multiple signals that are members of the signal group. Simulation results from the event trace file that are associated with instances of said multiple signals are then included within a presentation of simulation results.
摘要翻译：根据数据处理的方法，由数据处理系统接收包括由预定信号组名称指定信号组的至少一个条目的数据集。响应于数据集的接收，处理数据集中的条目以识别信号组名称。与包含模拟结果的事件跟踪文件相关联的信号组信息被访问以确定作为信号组成员的多个信号的信号名称。然后将与所述多个信号的实例相关联的事件跟踪文件的仿真结果包括在仿真结果的呈现中。

20. 发明申请

US20080183458A1 METHOD, SYSTEM AND PROGRAM PRODUCT SUPPORTING PRINT EVENTS IN THE SIMULATION OF A DIGITAL SYSTEM 有权
标题翻译：在数字系统仿真中支持打印事件的方法，系统和程序产品
公开(公告)号：US20080183458A1
公开(公告)日：2008-07-31
申请号：US11668542
申请日：2007-01-30
申请人： Gabor Bobok , Wolfgang Roesner , Derek E. Williams
发明人： Gabor Bobok , Wolfgang Roesner , Derek E. Williams
IPC分类号： G06G7/62 , G06F17/50
CPC分类号： G06F17/5022
摘要： According to a method of simulation processing, one or more HDL source files describing a digital design including a plurality of hierarchically arranged design entities are received. The one or more HDL source files include one or more statements instantiating a plurality of print events within the plurality of hierarchically arranged design entities, where each print event has an associated message and at least one associated signal in the digital design. The one or more HDL source files are processed to obtain a simulation executable model including a data structure describing the plurality of print events defined for the simulation executable model and associating each of the plurality of print events with its respective associated signal.
摘要翻译：根据模拟处理的方法，接收描述包括多个分层布置的设计实体的数字设计的一个或多个HDL源文件。一个或多个HDL源文件包括实例化多个分层布置的设计实体中的多个打印事件的一个或多个语句，其中每个打印事件具有相关联的消息和数字设计中的至少一个相关联的信号。处理一个或多个HDL源文件以获得模拟可执行模型，其包括描述为模拟可执行模型定义的多个打印事件的数据结构，并将多个打印事件中的每一个与其相应的相关信号相关联。

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