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11. 发明申请

US20120084577A1 CHARGE PUMP APPARATUS, A MEMORY INTEGRATED CIRCUIT AND METHODS OF POWER SUPPLY 有权
标题翻译：充电泵装置，记忆集成电路和电源方法
公开(公告)号：US20120084577A1
公开(公告)日：2012-04-05
申请号：US13315385
申请日：2011-12-09
申请人： Dumitru Cioaca
发明人： Dumitru Cioaca
IPC分类号： G06F1/26
CPC分类号： G11C16/30 , G06F1/26 , G06F1/28
摘要： A power supply, and a method of controlling the power supply, in which more or less power capacity of the power supply is activated depending on the state of a digital data signal on a data bus. The power supply has a control circuit which detects the number of “zero” bits present on the data bus, and responsively activates one or more of a plurality of power supply circuits such as charge pump circuits. The outputs of the charge pump circuits are mutually connected to a driver adapted to program memory cells of a flash memory circuit. A charge pump apparatus and a memory integrated circuit are also described.
摘要翻译：根据数据总线上的数字数据信号的状态，电源和控制电源的方法，其中电源的功率容量或多或少是激活的。电源具有检测数据总线上存在的“零”位的数量的控制电路，并且响应地激活多个电源电路中的一个或多个，例如电荷泵电路。电荷泵电路的输出相互连接到适于编程闪存电路的存储单元的驱动器。还描述了电荷泵装置和存储器集成电路。

12. 发明授权

US08082456B2 Data controlled power supply apparatus 有权
标题翻译：数据控制电源设备
公开(公告)号：US08082456B2
公开(公告)日：2011-12-20
申请号：US12222290
申请日：2008-08-06
申请人： Dumitru Cioaca
发明人： Dumitru Cioaca
IPC分类号： G06F1/26
CPC分类号： G11C16/30 , G06F1/26 , G06F1/28
摘要： A power supply, and a method of controlling the power supply, in which more or less power capacity of the power supply is activated depending on the state of a digital data signal on a data bus. The power supply has a control circuit which detects the number of “zero” bits present on the data bus, and responsively activates one or more of a plurality of power supply circuits such as charge pump circuits. The outputs of the charge pump circuits are mutually connected to a driver adapted to program memory cells of a flash memory circuit.
摘要翻译：根据数据总线上的数字数据信号的状态，电源和控制电源的方法，其中电源的功率容量或多或少是激活的。电源具有检测数据总线上存在的“零”位的数量的控制电路，并且响应地激活多个电源电路中的一个或多个，例如电荷泵电路。电荷泵电路的输出相互连接到适于编程闪存电路的存储单元的驱动器。

13. 发明申请

US20060092718A1 Flash memory data bus for synchronous burst read page 有权
公开(公告)号：US20060092718A1
公开(公告)日：2006-05-04
申请号：US11305287
申请日：2005-12-16
申请人： Dumitru Cioaca
发明人： Dumitru Cioaca
IPC分类号： G11C7/10
CPC分类号： G11C7/103 , G11C16/26
摘要： Memory device is described that utilizes a reduced number of sense amplifiers to sense the data bits of a selected column page. The sense amplifiers are multiplexed and the read data values latched, allowing the sense amplifiers to sense the next set of data lines from the selected column page before the currently latched values have been read out. A specialized decoder and a latch control circuit allows there to be no gaps or latencies while reading data from the memory due to reloading the read latches or in multiplexing the sense amplifiers. The design allows there to be no gaps or latencies while reading data from the memory due to reloading the read latches or multiplexing the sense amplifiers to sense a following set of data bit lines.

14. 发明授权

US06593726B1 Voltage converter system and method having a stable output voltage 有权
标题翻译：电压转换器系统和方法具有稳定的输出电压
公开(公告)号：US06593726B1
公开(公告)日：2003-07-15
申请号：US10076982
申请日：2002-02-15
申请人： Christophe J. Chevallier , Dumitru Cioaca
发明人： Christophe J. Chevallier , Dumitru Cioaca
IPC分类号： G05F144
CPC分类号： G05F1/465
摘要： An apparatus and method for compensating for a decreasing internal voltage that is generated from a higher external voltage. In response to the internal voltage decreasing in excess of a voltage margin, the amount by which the higher external voltage is reduced in generating the internal voltage is adjusted to raise the internal voltage.
摘要翻译：一种用于补偿由较高外部电压产生的内部电压降低的装置和方法。响应于内部电压降低超过电压余量，调节产生内部电压时外部电压越高的量，以提高内部电压。

15. 发明授权

US5101379A Apparatus for page mode programming of an EEPROM cell array with false loading protection 失效
标题翻译：用于具有假负载保护的EEPROM单元阵列的页面模式编程的装置
公开(公告)号：US5101379A
公开(公告)日：1992-03-31
申请号：US551642
申请日：1990-07-10
申请人： Tien-Ler Lin , Dumitru Cioaca
发明人： Tien-Ler Lin , Dumitru Cioaca
IPC分类号： G11C16/10 , G11C16/24 , G11C16/34
CPC分类号： G11C16/3427 , G11C16/10 , G11C16/24 , G11C16/3418
摘要： An apparatus for page mode programming of an EEPROM cell array with false loading protection is disclosed. The system includes a flip-flop operatively connected to a bit line for storing information to be loaded into an EEPROM memory cell, and false loading protection circuitry operatively connected to the bit line for preventing the false loading of an erroneous signal into the flip-flop and/or an EEPROM cell.
摘要翻译：公开了一种用于具有假负载保护的EEPROM单元阵列的页面模式编程的装置。该系统包括可操作地连接到位线的触发器，用于存储要加载到EEPROM存储器单元中的信息，以及可操作地连接到位线的假负载保护电路，用于防止错误信号错误地加载到触发器中和/或EEPROM单元。

16. 发明授权

US4785424A Apparatus for page mode programming of an EEPROM cell array with false loading protection 失效
标题翻译：用于具有假负载保护的EEPROM单元阵列的页面模式编程的装置
公开(公告)号：US4785424A
公开(公告)日：1988-11-15
申请号：US868114
申请日：1986-05-27
申请人： Tien-Ler Lin , Dumitru Cioaca
发明人： Tien-Ler Lin , Dumitru Cioaca
IPC分类号： G11C16/10 , G11C16/24 , G11C16/34 , G11C7/00 , G11C11/40
CPC分类号： G11C16/3427 , G11C16/10 , G11C16/24 , G11C16/3418
摘要： An apparatus for page mode programming of a memory cell with false loading protection is disclosed. The apparatus discharges any residual voltage left on the bit line after a read operation to prevent this voltage from being erroneously loaded into temporary storage apparatus associated with the bit line. In a preferred embodiment, two transistors are placed in series between the bit line and the array V.sub.ss line. A first transistor is controlled by a signal indicating that information is to be loaded into the temporary storage apparatus. The second transistor is controlled by a signal indicating that no memory cell associated with the bit line has been selected for programming.
摘要翻译：公开了一种用于具有假负载保护的存储单元的页面模式编程的装置。在读取操作之后，该装置释放在位线上剩余的任何残余电压，以防止该电压被错误地装载到与位线相关联的临时存储装置中。在优选实施例中，两个晶体管串联放置在位线和阵列Vss线之间。第一晶体管由指示将信息加载到临时存储装置中的信号控制。第二晶体管由表示没有选择与位线相关联的存储单元进行编程的信号控制。

17. 发明授权

US07424629B2 Data controlled power supply apparatus 有权
标题翻译：数据控制电源设备
公开(公告)号：US07424629B2
公开(公告)日：2008-09-09
申请号：US11510848
申请日：2006-08-28
申请人： Dumitru Cioaca
发明人： Dumitru Cioaca
IPC分类号： G06F1/26
CPC分类号： G11C16/30 , G06F1/26 , G06F1/28
摘要： A power supply, and a method of controlling the power supply, in which more or less power capacity of the power supply is activated depending on the state of a digital data signal on a data bus. The power supply has a control circuit which detects the number of “zero” bits present on the data bus, and responsively activates one or more of a plurality of power supply circuits such as charge pump circuits. The outputs of the charge pump circuits are mutually connected to a driver adapted to program memory cells of a flash memory circuit.
摘要翻译：根据数据总线上的数字数据信号的状态，电源和控制电源的方法，其中电源的功率容量或多或少是激活的。电源具有检测数据总线上存在的“零”位的数量的控制电路，并且响应地激活多个电源电路中的一个或多个，例如电荷泵电路。电荷泵电路的输出相互连接到适于编程闪存电路的存储单元的驱动器。

18. 发明申请

US20070050651A1 Data controlled programming pump 有权
标题翻译：数据控制编程泵
公开(公告)号：US20070050651A1
公开(公告)日：2007-03-01
申请号：US11510848
申请日：2006-08-28
申请人： Dumitru Cioaca
发明人： Dumitru Cioaca
IPC分类号： G06F1/00
CPC分类号： G11C16/30 , G06F1/26 , G06F1/28
摘要： A power supply, and a method of controlling the power supply, in which more or less power capacity of the power supply is activated depending on the state of a digital data signal on a data bus. The power supply has a control circuit which detects the number of “zero” bits present on the data bus, and responsively activates one or more of a plurality of power supply circuits such as charge pump circuits. The outputs of the charge pump circuits are mutually connected to a driver adapted to program memory cells of a flash memory circuit.
摘要翻译：根据数据总线上的数字数据信号的状态，电源和控制电源的方法，其中电源的功率容量或多或少是激活的。电源具有检测数据总线上存在的“零”位的数量的控制电路，并且响应地激活多个电源电路中的一个或多个，例如电荷泵电路。电荷泵电路的输出相互连接到适于编程闪存电路的存储单元的驱动器。

19. 发明授权

US06906965B2 Temperature-compensated output buffer circuit 失效
标题翻译：温度补偿输出缓冲电路
公开(公告)号：US06906965B2
公开(公告)日：2005-06-14
申请号：US10675692
申请日：2003-09-30
申请人： Dumitru Cioaca
发明人： Dumitru Cioaca
IPC分类号： G05F3/24 , G11C7/04 , G11C7/10 , H03K19/003 , H03K19/0185 , G11C7/00
CPC分类号： G11C7/04 , G05F3/245 , G11C7/1051 , G11C7/1057 , H03K19/00384 , H03K19/018528
摘要： An output buffer circuit that compensates for ambient temperature changes facilitates more consistent current drive capacity across a range of ambient temperatures. The number of output buffer stages utilized to generate the data output signal is varied in response to changes in ambient temperature.
摘要翻译：补偿环境温度变化的输出缓冲电路有助于在一定范围的环境温度下实现更一致的电流驱动能力。用于产生数据输出信号的输出缓冲器级数随着环境温度的变化而变化。

20. 发明授权

US06885589B2 Synchronous up/down address generator for burst mode read 有权
标题翻译：用于突发模式读取的同步上/下地址发生器
公开(公告)号：US06885589B2
公开(公告)日：2005-04-26
申请号：US10901566
申请日：2004-07-29
申请人： Dumitru Cioaca
发明人： Dumitru Cioaca
IPC分类号： G11C7/10 , G11C8/04 , G11C16/06
CPC分类号： G11C7/1072 , G11C7/1021 , G11C7/1027 , G11C8/04
摘要： A symmetrical divide-by-2 circuit has a master latch made up of two inverters. The circuit has an inverter on each output. The capacitance of these inverters forms a dynamic slave latch that is connected to the master latch through a transmission gate on each master latch output. The data is transferred from the master latch to the dynamic slave latch every clock cycle by an enable clock and an inverse of the enable clock. Capacitance leakage is reduced by the transmission gates until the next clock cycle. The circuit is clocked by a one-shot clock that is self-aligning to the latest transition of either the enable clock or inverse enable clock.
摘要翻译：对称的2分频电路具有由两个逆变器组成的主锁存器。该电路在每个输出端都有一个反相器。这些反相器的电容形成动态从锁存器，其通过每个主锁存器输出上的传输门连接到主锁存器。每个时钟周期将数据从主机锁存器传送到动态从机锁存器，使能时钟和使能时钟的反相。通过传输门减少电容泄漏直到下一个时钟周期。该电路由单触发时钟提供时钟，该时钟自动对准到使能时钟或反向使能时钟的最新转换。

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