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11. 发明授权

US08180980B2 Device emulation support within a host data processing apparatus 有权
标题翻译：主机数据处理设备内的设备仿真支持
公开(公告)号：US08180980B2
公开(公告)日：2012-05-15
申请号：US12453806
申请日：2009-05-22
申请人： Stewart David Biles , David Hennah Mansell , Richard Roy Grisenthwaite
发明人： Stewart David Biles , David Hennah Mansell , Richard Roy Grisenthwaite
IPC分类号： G06F12/00
CPC分类号： G06F9/45558 , G06F2009/45583
摘要： A data processing apparatus 12 is provided with a memory management unit 24 which triggers memory aborts. When a memory abort occurs, data characterizing the memory abort is written to a fault status register 28 (memory-abort register). The data characterizing the memory abort includes data identifying a register number associated with the memory access which gave rise to the memory abort. This register identifying data is used to emulate the action of the memory access instruction without having to read the program instruction lead to the memory abort. This is useful in providing virtualization support for a virtual data processing apparatus 2.
摘要翻译：数据处理装置12设置有触发存储器中止的存储器管理单元24。当发生存储器中止时，表征存储器中止的数据被写入故障状态寄存器28（存储器中止寄存器）。表征存储器中止的数据包括识别与存储器访问相关联的寄存器号的数据，这导致存储器中止。该寄存器识别数据用于模拟存储器访问指令的动作，而不必读取导致存储器中止的程序指令。这对于为虚拟数据处理设备2提供虚拟化支持是有用的。

12. 发明申请

US20110307681A1 Apparatus and method for mapping architectural registers to physical registers 有权
标题翻译：将架构寄存器映射到物理寄存器的装置和方法
公开(公告)号：US20110307681A1
公开(公告)日：2011-12-15
申请号：US12801576
申请日：2010-06-15
申请人： Frederic Claude Marie Piry , Louis-Marie Vincent Mouton , Luca Scalabrino , Richard Roy Grisenthwaite , David Hennah Mansell
发明人： Frederic Claude Marie Piry , Louis-Marie Vincent Mouton , Luca Scalabrino , Richard Roy Grisenthwaite , David Hennah Mansell
IPC分类号： G06F12/10
CPC分类号： G06F9/30098 , G06F9/3012 , G06F9/3838 , G06F9/384 , G06F9/3861 , G06F9/45558
摘要： An apparatus and method are provided for performing register renaming, whereby architectural registers from a set of architectural registers are mapped to physical registers from a set of physical registers. Available register identifying circuitry is provided which is responsive to a current state of the apparatus to identify which physical registers form a pool of physical registers available to be mapped by register renaming circuitry to an architectural register specified by an instruction to be executed. Configuration storage stores configuration data whose value is modified during operation of the processing circuitry, such that when the configuration data has a first value, the configuration data identifies at least one architectural register of the architectural register set which does not require mapping to a physical register by the register renaming circuitry. The available register identifying circuitry is arranged to reference the configuration storage, such that when the configuration data has the first value, the number of physical registers in the pool is increased due to the reduction in the number of architectural registers which require mapping to physical registers. This enables the performance benefits from performing register renaming to be improved, without the need to increase the number of physical registers within the physical register set.
摘要翻译：提供了一种用于执行寄存器重命名的装置和方法，其中来自一组架构寄存器的架构寄存器从一组物理寄存器映射到物理寄存器。提供了可用的寄存器识别电路，其响应于设备的当前状态，以识别哪些物理寄存器形成可被寄存器重命名电路映射到可由要执行的指令指定的架构寄存器的物理寄存器池。配置存储器存储其值在处理电路的操作期间被修改的配置数据，使得当配置数据具有第一值时，配置数据标识架构寄存器集的至少一个体系结构寄存器，其不需要映射到物理寄存器通过寄存器重命名电路。可用的寄存器识别电路被布置为引用配置存储器，使得当配置数据具有第一值时，由于需要映射到物理寄存器的架构寄存器的数量的减少，池中的物理寄存器的数量增加。这使得能够改进执行寄存器重命名的性能优势，而不需要增加物理寄存器集中的物理寄存器的数量。

13. 发明授权

US08041930B2 Data processing apparatus and method for controlling thread access of register sets when selectively operating in secure and non-secure domains 有权
标题翻译：当选择性地在安全和非安全域中操作时，用于控制寄存器组的线程访问的数据处理装置和方法
公开(公告)号：US08041930B2
公开(公告)日：2011-10-18
申请号：US11919757
申请日：2005-05-11
申请人： David Hennah Mansell , Stuart David Biles , David Michael Gilday , Daniel Kershaw
发明人： David Hennah Mansell , Stuart David Biles , David Michael Gilday , Daniel Kershaw
IPC分类号： G06F9/00
CPC分类号： G06F9/30123 , G06F9/3012 , G06F9/3851
摘要： The data processing apparatus has processing logic for performing data processing operations and a register bank for storing data associated with the processing logic. The register bank has at least one register group, each register group having a plurality of register sets. The processing logic has an operating state associated with each register group defining how that register group is used, a first operating state being a state in which each register set in the register group is used to support an independent execution thread of the processing logic, and a second operating state being a state in which the register sets of the register group are collectively used to support a single execution thread of the processing logic. Control logic is provided to control how the register sets of each register group are used dependent on the operating state associated with that register group.
摘要翻译：数据处理装置具有用于执行数据处理操作的处理逻辑和用于存储与处理逻辑相关联的数据的寄存器组。寄存器组具有至少一个寄存器组，每个寄存器组具有多个寄存器组。处理逻辑具有与定义如何使用该寄存器组的每个寄存器组相关联的操作状态，第一操作状态是其中在寄存器组中设置的每个寄存器用于支持处理逻辑的独立执行线程的状态，以及第二操作状态是将寄存器组的寄存器组集中用于支持处理逻辑的单个执行线程的状态。提供控制逻辑以根据与该寄存器组相关联的操作状态来控制如何使用每个寄存器组的寄存器组。

14. 发明授权

US07734897B2 Allocation of memory access operations to memory access capable pipelines in a superscalar data processing apparatus and method having a plurality of execution threads 有权
标题翻译：在具有多个执行线程的超标量数据处理装置和方法中，将存储器访问操作分配给具有存储器访问能力的管线
公开(公告)号：US07734897B2
公开(公告)日：2010-06-08
申请号：US11312653
申请日：2005-12-21
申请人： David Hennah Mansell
发明人： David Hennah Mansell
IPC分类号： G06F15/76
CPC分类号： G06F9/3851 , G06F9/3822 , G06F9/3824 , G06F9/3885 , G06F9/3891 , G06F12/0846 , G06F12/0864
摘要： A superscalar data processing apparatus and method are provided for processing operations, the apparatus having a plurality of execution threads and each execution thread being operable to process a sequence of operations including at least one memory access operation. The superscalar data processing apparatus comprises a plurality of execution pipelines for executing the operations, and issue logic for allocating each operation to one of the execution pipelines for execution by that execution pipeline. At least two of the execution pipelines are memory access capable pipelines which can execute memory access operations, and each memory access capable pipeline is associated with a subset of the plurality of execution threads. The issue logic is arranged, for each execution thread, to allocate any memory access operations of that execution thread to an associated memory access capable pipeline. Such a system has been found to provide an effective balance between increasing the efficiency of operation of the superscalar data processing apparatus when employing multiple execution threads whilst also alleviating the need for complex hardware to handle hazard detection.
摘要翻译：提供了一种用于处理操作的超标量数据处理装置和方法，该装置具有多个执行线程，每个执行线程可操作以处理包括至少一个存储器访问操作的一系列操作。超标量数据处理装置包括用于执行操作的多个执行流水线，并发出用于将每个操作分配给一个执行流水线以供该执行流水线执行的逻辑。至少两个执行管线是能够执行存储器访问操作的能够存储器访问的管线，并且每个具有存储器访问能力的流水线与多个执行线程的子集相关联。为每个执行线程安排问题逻辑，以将该执行线程的任何存储器访问操作分配给相关的存储器访问能力管线。已经发现，这种系统在采用多个执行线程时提高超标量数据处理装置的操作效率之间的有效平衡，同时还减少了复杂硬件处理危险检测的需要。

15. 发明授权

US07661104B2 Task following between multiple operating systems 有权
标题翻译：多个操作系统之间的任务
公开(公告)号：US07661104B2
公开(公告)日：2010-02-09
申请号：US10714482
申请日：2003-11-17
申请人： Simon Charles Watt , Christopher Bentley Dornan , Luc Orion , Nicolas Chaussade , Lionel Belnet , Stephane Eric Sebastian Brochier , David Hennah Mansell , Dominic Hugo Symes
发明人： Simon Charles Watt , Christopher Bentley Dornan , Luc Orion , Nicolas Chaussade , Lionel Belnet , Stephane Eric Sebastian Brochier , David Hennah Mansell , Dominic Hugo Symes
IPC分类号： G06F9/455 , G06F9/46 , G06F3/00 , H04L29/06
CPC分类号： G06F9/4812 , G06F9/526
摘要： A processor may utilise two operating systems (Non-Secure, Secure) between which calls may be made. In order that a second operating system can track task switches made by a first operating system, each time a call is made to the second operating system, this call includes an identifier to enable discrimination between the task which was executing on the first operating system when that call was made. The identifier can be a call identifier and/or a target thread identifier and may include further parameters.
摘要翻译：处理器可以利用两个可以进行呼叫的操作系统（非安全的，安全的）。为了使第二操作系统能够跟踪由第一操作系统进行的任务切换，每次对第二操作系统进行呼叫时，该呼叫包括标识符，以便能够在第一操作系统上执行的任务之间进行区分，那个电话是做的。标识符可以是呼叫标识符和/或目标线程标识符，并且可以包括其他参数。

16. 发明申请

US20090313455A1 Instruction issue control wtihin a multithreaded processor 审中-公开
标题翻译：多线程处理器中的指令问题控制
公开(公告)号：US20090313455A1
公开(公告)日：2009-12-17
申请号：US11919210
申请日：2005-12-15
申请人： David Hennah Mansell , Stuart David Biles
发明人： David Hennah Mansell , Stuart David Biles
IPC分类号： G06F9/38
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/3851 , G06F9/3857
摘要： A multithreaded processor is provided with a saturating counter which serves to generate a thread preference signal to steer selection of which program thread operations are taken from for issue into the multiple processor pipelines. The counter is updated based upon the selections made for issue. The counter is a saturating counter and its sign bit may be used as a thread preference signal when discriminating between two threads. The update made to the count value can be weighted depending upon programmable priorities associated with the respective threads as well as a weighting based upon the time taken to execute the type of operation selected.
摘要翻译：多线程处理器设置有饱和计数器，其用于产生线程偏好信号以引导选择哪些程序线程操作被从多个处理器管线中发出。计数器根据对问题的选择进行更新。计数器是饱和计数器，并且当识别两个线程时，其符号位可以用作线程偏好信号。对计数值进行的更新可以根据与相应线程相关联的可编程优先级加权，以及基于执行所选择的操作类型所花费的时间的加权。

17. 发明授权

US07529916B2 Data processing apparatus and method for controlling access to registers 有权
标题翻译：用于控制对寄存器的访问的数据处理装置和方法
公开(公告)号：US07529916B2
公开(公告)日：2009-05-05
申请号：US11504780
申请日：2006-08-16
申请人： Daniel Kershaw , James Ian McNiven , Daniel Luke Kefford , David Hennah Mansell
发明人： Daniel Kershaw , James Ian McNiven , Daniel Luke Kefford , David Hennah Mansell
IPC分类号： G06F9/00
CPC分类号： G06F9/45533 , G06F9/30101 , G06F9/30181 , G06F9/30189 , G06F9/462 , G06F9/468 , G06F9/4812 , G06F21/74
摘要： A data processing apparatus and method are provided for controlling access to registers. The data processing apparatus comprises a processing unit for performing data processing operations on data values, the processing unit having a plurality of modes of operation. A plurality of registers are provided for storing data values for access by the processing unit, with a subset of those registers being mode specific registers. Each mode specific register is used by the processing unit when operating in an associated mode of operation. The processing unit is switchable between a plurality of contexts, the data values stored in the plurality of registers being dependent on a current context of the processing unit. The processing unit performs a switch operation to switch from the current context to a new context, during which the data values in the registers are updated having regard to the new context. A control register is provided which, for at least one mode of operation having at least one mode specific register associated therewith, has an access field which is programmable by the processing unit when operating in a predetermined mode of operation. When the access field is set, the processing unit is selectively denied access to the associated at least one mode specific register, whereby updating of the data values in the associated at least one mode specific register is avoided during the switch operation. This significantly increases the speed of the switch operation.
摘要翻译：提供了一种用于控制对寄存器的访问的数据处理装置和方法。数据处理装置包括用于对数据值执行数据处理操作的处理单元，所述处理单元具有多种操作模式。提供多个寄存器用于存储用于由处理单元访问的数据值，其中这些寄存器的子集是模式特定寄存器。当在相关联的操作模式下操作时，处理单元使用每个模式特定寄存器。处理单元可在多个上下文之间切换，存储在多个寄存器中的数据值取决于处理单元的当前上下文。处理单元执行切换操作以从当前上下文切换到新的上下文，在此期间，考虑到新的上下文，更新寄存器中的数据值。提供控制寄存器，对于具有与其相关联的至少一个模式特定寄存器的至少一种操作模式，具有在以预定操作模式操作时由处理单元可编程的访问字段。当访问字段被设置时，处理单元被选择性地拒绝对相关联的至少一个模式特定寄存器的访问，由此在切换操作期间避免在相关联的至少一个模式特定寄存器中更新数据值。这显着提高了开关操作的速度。

18. 发明申请

US20090094439A1 Data processing apparatus and method employing multiple register sets 有权
标题翻译：采用多个寄存器组的数据处理装置和方法
公开(公告)号：US20090094439A1
公开(公告)日：2009-04-09
申请号：US11919757
申请日：2005-05-11
申请人： David Hennah Mansell , Stuart David Biles , David Michael Gilday , Danel Kershaw
发明人： David Hennah Mansell , Stuart David Biles , David Michael Gilday , Danel Kershaw
IPC分类号： G06F9/38 , G06F9/30 , G06F9/318
CPC分类号： G06F9/30123 , G06F9/3012 , G06F9/3851
摘要： A data processing apparatus and method employing multiple register sets is disclosed. The data processing apparatus has processing logic for performing data processing operations and a register bank for storing data associated with the processing logic. The register bank has at least one register group, each register group having a plurality of register sets. The processing logic has an operating state associated with each register group defining how that register group is used, a first operating state being a state in which each register set in the register group is used to support an independent execution thread of the processing logic, and a second operating state being a state in which the register sets of the register group are collectively used to support a single execution thread of the processing logic. Control logic is provided to control how the register sets of each register group are used dependent on the operating state associated with that register group. This has been found to provide a particularly efficient use of the registers within the data processing apparatus.
摘要翻译：公开了一种采用多个寄存器组的数据处理装置和方法。数据处理装置具有用于执行数据处理操作的处理逻辑和用于存储与处理逻辑相关联的数据的寄存器组。寄存器组具有至少一个寄存器组，每个寄存器组具有多个寄存器组。处理逻辑具有与定义如何使用该寄存器组的每个寄存器组相关联的操作状态，第一操作状态是其中在寄存器组中设置的每个寄存器用于支持处理逻辑的独立执行线程的状态，以及第二操作状态是将寄存器组的寄存器组集中用于支持处理逻辑的单个执行线程的状态。提供控制逻辑以根据与该寄存器组相关联的操作状态来控制如何使用每个寄存器组的寄存器组。已经发现这提供了数据处理装置内寄存器的特别有效的用途。

19. 发明授权

US07249270B2 Method and apparatus for placing at least one processor into a power saving mode when another processor has access to a shared resource and exiting the power saving mode upon notification that the shared resource is no longer required by the other processor 有权
标题翻译：当另一个处理器可以访问共享资源并且在通知另一个处理器不再需要共享资源时退出功率节省模式时，将至少一个处理器置于省电模式的方法和装置
公开(公告)号：US07249270B2
公开(公告)日：2007-07-24
申请号：US11044261
申请日：2005-01-28
申请人： David Hennah Mansell , Richard Roy Grisenthwaite , Harry Samuel Thomas Fearnhamm , Jeremy Piers Davies
发明人： David Hennah Mansell , Richard Roy Grisenthwaite , Harry Samuel Thomas Fearnhamm , Jeremy Piers Davies
IPC分类号： G06F1/32 , G06F12/00
CPC分类号： G06F13/24 , G06F1/3228
摘要： The present invention provides a data processing apparatus and method of controlling access to a shared resource. The data processing apparatus has a plurality of processors operable to perform respective data processing operations requiring access to the shared resource, and a path is provided interconnecting the plurality of processors. An access control mechanism is operable to control access to the shared resource by the plurality of processors, each processor being operable to enter a power saving mode if access to the shared resource is required but the access control mechanism is preventing access to the shared resource by that processor. Further, each processor is operable, when that processor has access to the shared resource, to issue a notification on the path when access to the shared resource is no longer required by that processor. A processor in the power saving mode is arranged, upon receipt of that notification, to exit the power saving mode and to seek access to the shared resource. This approach has been found to result in significant power savings.
摘要翻译：本发明提供一种控制对共享资源的访问的数据处理装置和方法。数据处理装置具有可操作以执行需要访问共享资源的相应数据处理操作的多个处理器，并且提供互连多个处理器的路径。访问控制机制可操作以控制多个处理器对共享资源的访问，如果需要对共享资源的访问，则每个处理器可操作以进入省电模式，但是访问控制机制阻止对共享资源的访问那个处理器。此外，当处理器具有对共享资源的访问时，每个处理器可操作地在该处理器不再需要对共享资源的访问时在路径上发布通知。处于省电模式的处理器在接收到该通知时被布置为退出省电模式并寻求对共享资源的访问。已经发现这种方法导致显着的功率节省。

20. 发明授权

US07185159B2 Technique for accessing memory in a data processing apparatus 有权
标题翻译：用于访问数据处理设备中的存储器的技术
公开(公告)号：US07185159B2
公开(公告)日：2007-02-27
申请号：US10714520
申请日：2003-11-17
申请人： Lionel Beinet , David Hennah Mansell , Simon Charles Watt
发明人： Lionel Beinet , David Hennah Mansell , Simon Charles Watt
IPC分类号： G06F12/00
CPC分类号： G06F21/85 , G06F12/1491 , G06F21/629 , G06F21/74 , G06F2221/2105 , G06F2221/2141 , G06F2221/2149
摘要： The present invention provides a data processing apparatus and method for accessing memory. The data processing apparatus has a secure domain and a non-secure domain, in the secure domain the data processing apparatus having access to secure data which is not accessible in the non-secure domain. The data processing apparatus comprises a device coupled via a device bus with the memory, the device being operable, when an item of data in the memory is required by the device, to issue onto the device bus a memory access request pertaining to either the secure domain or the non-secure domain. The memory is operable to store data required by the device, and contains secure memory for storing secure data and non-secure memory for storing non-secure data. In accordance with the invention, the memory access request as issued by the device includes a domain signal identifying whether the memory access request pertains to either the secure domain or the non-secure domain. The presence of this domain signal issued as part of the memory access request enables checking to be performed to ensure that secure data within the secure memory is not accessed by the device when the memory access request pertains to the non-secure domain.
摘要翻译：本发明提供一种访问存储器的数据处理装置和方法。数据处理装置具有安全域和非安全域，在安全域中，数据处理装置具有对非安全域中不可访问的安全数据的访问。数据处理设备包括经由设备总线与存储器耦合的设备，当设备需要存储器中的数据项时，该设备可操作地向设备总线发出与安全性相关的存储器访问请求域或非安全域。存储器可操作以存储设备所需的数据，并且包含用于存储安全数据的安全存储器和用于存储非安全数据的非安全存储器。根据本发明，由设备发布的存储器访问请求包括识别存储器访问请求是否属于安全域或非安全域的域信号。作为存储器访问请求的一部分而发布的该域信号的存在使得能够执行检查，以便当存储器访问请求与非安全域相关时，确保安全存储器内的安全数据不被设备访问。

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