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11. 发明授权

US5753040A Method for the growth of epitaxial metal-insulator-metal-semiconductor structures 失效
标题翻译：外延金属 - 绝缘体 - 金属 - 半导体结构的生长方法
公开(公告)号：US5753040A
公开(公告)日：1998-05-19
申请号：US474618
申请日：1995-06-07
申请人： Chih-Chen Cho
发明人： Chih-Chen Cho
IPC分类号： H01L21/28 , H01L21/285 , H01L21/314 , H01L21/3205 , H01L29/51 , C30B23/08
CPC分类号： H01L21/28194 , H01L21/28512 , H01L21/314 , H01L21/32051 , H01L29/51
摘要： In one form of the invention, a method for the growth of an epitaxial insulator-metal structure on a semiconductor surface comprising the steps of maintaining the semiconductor surface at a pressure below approximately 1.times.10.sup.-7 mbar, maintaining the semiconductor surface at a substantially fixed first temperature between approximately 25.degree. C. and 400.degree. C., depositing an epitaxial metal layer on the semiconductor surface, adjusting the semiconductor surface to a substantially fixed second temperature between approximately 25.degree. C. and 200.degree. C., starting a deposition of epitaxial CaF.sub.2 on the first metal layer, ramping the second temperature to a third substantially fixed temperature between 200.degree. C. and 500.degree. C. over a time period, maintaining the third temperature until the epitaxial CaF.sub.2 has deposited to a desired thickness, and stopping the deposition of epitaxial CaF.sub.2 on the first metal layer. Other devices, systems and methods are also disclosed.
摘要翻译：在本发明的一种形式中，一种用于在半导体表面上生长外延绝缘体 - 金属结构的方法包括以下步骤：将半导体表面保持在低于约1×10-7毫巴的压力，将半导体表面保持在基本固定的第一在约25℃至400℃之间的温度下，在半导体表面上沉积外延金属层，将半导体表面调节至约25℃至200℃之间的基本固定的第二温度，开始沉积外延 CaF2在第一金属层上，在一段时间内将第二温度升至第二温度至200℃至500℃之间的第三基本上固定的温度，保持第三温度，直到外延CaF 2沉积到期望的厚度，并停止在第一金属层上沉积外延CaF 2。还披露了其他设备，系统和方法。

12. 发明授权

US5723872A Mixed barrier resonant tunneling 失效
标题翻译：混合屏障共振隧穿
公开(公告)号：US5723872A
公开(公告)日：1998-03-03
申请号：US290269
申请日：1994-08-15
申请人： Alan C. Seabaugh , Chih-Chen Cho
发明人： Alan C. Seabaugh , Chih-Chen Cho
IPC分类号： H01L29/88 , H01L29/06 , H01L29/24
CPC分类号： B82Y10/00 , H01L29/882
摘要： A resonant tunneling diode (400) made of a quantum well (406) with tunneling barriers (404, 408) made of two different materials such as calcium fluoride (408) and silicon dioxide (404). The calcium fluoride provides lattice match between the emitter (410) and the quantum well (406). Further resonant tunneling diodes with silicon lattice match barriers may be made of III-V compounds containing nitrogen.
摘要翻译：由量子阱（406）制成的谐振隧道二极管（400），其具有由诸如氟化钙（408）和二氧化硅（404）的两种不同材料制成的隧道势垒（404,408）。氟化钙在发射极（410）和量子阱（406）之间提供晶格匹配。具有硅晶格匹配屏障的其它谐振隧穿二极管可以由含有氮的III-V化合物制成。

13. 发明授权

US5661344A Porous dielectric material with a passivation layer for electronics applications 失效
标题翻译：多孔电介质材料，具有电子应用的钝化层
公开(公告)号：US5661344A
公开(公告)日：1997-08-26
申请号：US476164
申请日：1995-06-07
申请人： Robert H. Havemann , Bruce E. Gnade , Chih-Chen Cho
发明人： Robert H. Havemann , Bruce E. Gnade , Chih-Chen Cho
IPC分类号： H01L21/316 , H01L21/768 , H01L23/522 , H01L23/532 , H01L51/00
CPC分类号： H01L21/02216 , H01L21/02126 , H01L21/02203 , H01L21/02282 , H01L21/02304 , H01L21/02337 , H01L21/02343 , H01L21/02359 , H01L21/02362 , H01L21/31695 , H01L21/76802 , H01L21/7682 , H01L21/76829 , H01L21/76831 , H01L23/5222 , H01L23/53223 , H01L2221/1047 , H01L2924/0002
摘要： A semiconductor device and process for making the same are disclosed which use porous dielectric materials to reduce capacitance between conductors, while allowing conventional photolithography and metal techniques and materials to be used in fabrication. In one structure, patterned conductors 18 are provided on an interlayer dielectric 10, with a substrate encapsulation layer 31 deposited conformally over this structure. A layer of porous dielectric material 22 (e.g. dried SiO.sub.2 gel) is then deposited to substantially fill the gaps between and also cover the conductors. A substantially solid cap layer 14 of a material such as SiO.sub.2 is then deposited, followed by a photolithography step to define via locations. Vias are etched through the cap layer, and then through the porous dielectric. A via passivating layer 30 is conformally deposited and then anisotropically etched to clear the bottom of the vias while leaving a passivating liner in the via, preventing the via metal from directly contacting the porous material. A second application of these steps may be used to form a second, overlying structure of patterned conductors 38, encapsulating layer 36, porous dielectric layer 40, and cap layer 42.
摘要翻译：公开了一种半导体器件及其制造方法，其使用多孔介电材料来减小导体之间的电容，同时允许常规光刻和金属技术和材料用于制造。在一种结构中，图案化导体18设置在层间电介质10上，基底封装层31保形地沉积在该结构上。然后沉积一层多孔电介质材料22（例如干燥的SiO 2凝胶）以基本上填充导体之间的间隙并且还覆盖导体。然后沉积诸如SiO 2的材料的基本上固体的盖层14，然后沉积光刻步骤以限定通孔位置。通孔通过盖层蚀刻，然后通过多孔电介质。通孔钝化层30被共形沉积，然后各向异性蚀刻以清除通孔的底部，同时在通孔中留下钝化衬垫，防止通孔金属直接接触多孔材料。可以使用这些步骤的第二应用来形成图案化导体38，封装层36，多孔介电层40和盖层42的第二覆盖结构。

14. 发明授权

US5656848A High thermal resistance backfill material for hybrid UFPA's 失效
标题翻译：用于混合UFPA的高耐热回填材料
公开(公告)号：US5656848A
公开(公告)日：1997-08-12
申请号：US477004
申请日：1995-06-07
申请人： Howard R. Beratan , Chih-Chen Cho
发明人： Howard R. Beratan , Chih-Chen Cho
IPC分类号： G01J5/20 , G01J5/34 , H01L23/532 , H01L27/146 , H01L31/058 , H01L31/09 , H01L31/101
CPC分类号： G01J5/20 , G01J5/34 , H01L23/5329 , H01L27/14609 , H01L27/14623 , H01L27/1465 , H01L27/1469 , H01L2924/0002
摘要： A porous film 64 is used to thermally insulate sensing integrated circuitry 44 from pixels 34 of an uncooled IR detector hybrid system 30. The porous film 64 is preferably a silicon-dioxide xerogel. A protective film 65 may be deposited on the porous film 64.
摘要翻译：多孔膜64用于将感测集成电路44与未经IR的IR检测器混合系统30的像素34热绝缘。多孔膜64优选为二氧化硅干凝胶。保护膜65可以沉积在多孔膜64上。

15. 发明授权

US5656555A Modified hydrogen silsesquioxane spin-on glass 失效
标题翻译：改性氢倍半硅氧烷旋涂玻璃
公开(公告)号：US5656555A
公开(公告)日：1997-08-12
申请号：US390181
申请日：1995-02-17
申请人： Chih-Chen Cho
发明人： Chih-Chen Cho
IPC分类号： C09D183/05 , C09D183/04 , H01L21/312 , H01L21/316
CPC分类号： H01L21/02134 , H01L21/02282 , H01L21/02337 , H01L21/3124
摘要： A modified hydrogen silsesquioxane (HSQ) precursor is disclosed, along with methods for depositing such a precursor on a semiconductor substrate and a semiconductor device having a dielectric thin film deposited from such a precursor. The method comprises coating a semiconductor substrate 10, which typically comprises conductors 12, with a film of a modified HSQ film precursor. The HSQ film precursor comprises a hydrogen silsesquioxane resin and a modifying agent, preferably selected from the group consisting of alkyl alkoxysilanes, fluorinated alkyl alkoxysilanes, and combinations thereof. The method further comprises curing film 14, wherein the inclusion of the modifying agent inhibits oxidation and/or water absorption by the film during and/or after curing. It is believed that the modifying agent modifies film surface 16 to produce this effect. Films produced according to the present invention apparently have repeatable dielectric properties for drying and curing conditions which produced widely varying properties for unmodified films.
摘要翻译：公开了改进的氢倍半硅氧烷（HSQ）前体，以及在半导体衬底上沉积这种前体的方法以及具有由这种前体沉积的电介质薄膜的半导体器件。该方法包括将通常包含导体12的半导体衬底10与改性的HSQ膜前体的膜一起涂覆。 HSQ膜前体包含氢倍半硅氧烷树脂和改性剂，优选选自烷基烷氧基硅烷，氟化烷基烷氧基硅烷及其组合。该方法还包括固化膜14，其中包含改性剂在固化期间和/或固化后抑制膜的氧化和/或吸水。据信，改性剂改变膜表面16以产生这种效果。根据本发明生产的膜显然具有可重复的介电性能，用于干燥和固化条件，其产生对未改性膜的广泛变化的性质。

16. 发明授权

US5627082A High thermal resistance backfill material for hybrid UFPA's 失效
公开(公告)号：US5627082A
公开(公告)日：1997-05-06
申请号：US412817
申请日：1995-03-29
申请人： Howard R. Beratan , Chih-Chen Cho
发明人： Howard R. Beratan , Chih-Chen Cho
IPC分类号： G01J5/20 , G01J5/34 , H01L23/532 , H01L27/146 , H01L31/00 , H01L31/15
CPC分类号： G01J5/20 , G01J5/34 , H01L23/5329 , H01L27/14609 , H01L27/14623 , H01L27/1465 , H01L27/1469 , H01L2924/0002
摘要： A porous film 64 is used to thermally insulate sensing integrated circuitry 44 from pixels 34 of an uncooled IR detector hybrid system 30. The porous film 64 is preferably a silicon-dioxide xerogel. A protective film 65 may be deposited on the porous film 64.

17. 发明授权

US5569058A Low density, high porosity material as gate dielectric for field emission device 失效
公开(公告)号：US5569058A
公开(公告)日：1996-10-29
申请号：US461230
申请日：1995-06-05
申请人： Bruce Gnade , Chih-Chen Cho , Jules D. Levine
发明人： Bruce Gnade , Chih-Chen Cho , Jules D. Levine
IPC分类号： H01J1/304 , H01J1/30 , H01J9/18
CPC分类号： H01J1/3042 , H01J2201/319 , H01J2329/00
摘要： A porous dielectric material such as silica-based aerogel is used as the dielectric layer 48 between the gate and the cathode on the emitter plate 12 of a field emission device. Aerogel, which can have a relative dielectric constant as low as 1.03, is deposited over the resistive layer 44 of the emitter plate 12. Metal layer 49, functioning as the gate electrode, is subsequently deposited over the aerogel layer 48. The use of aerogel as a gate dielectric reduces power consumption. In a disclosed embodiment, aerogel layer 48 is comprised of sublayers 48a, 48b, and 48c of aerogels of differing densities, thereby providing better adhesion of the aerogel gate dielectric to both the resistive layer 44 and metal layer 49. Methods of fabricating the aerogel gate dielectric are disclosed.

18. 发明授权

US5561318A Porous composites as a low dielectric constant material for electronics applications 失效
标题翻译：多孔复合材料作为用于电子应用的低介电常数材料
公开(公告)号：US5561318A
公开(公告)日：1996-10-01
申请号：US477029
申请日：1995-06-07
申请人： Bruce E. Gnade , Chih-Chen Cho , Douglas M. Smith
发明人： Bruce E. Gnade , Chih-Chen Cho , Douglas M. Smith
IPC分类号： C04B38/00 , H01L21/312 , H01L21/314 , H01L21/316 , H01L21/768 , H01L23/522 , H01L23/532 , H01L23/58
CPC分类号： H01L21/7682 , H01L21/02126 , H01L21/02203 , H01L21/02216 , H01L21/02282 , H01L21/02337 , H01L21/02343 , H01L21/02359 , H01L21/02362 , H01L21/31695 , H01L21/76835 , H01L23/5222 , H01L23/5329 , H01L21/3121 , H01L2221/1047 , H01L2924/0002
摘要： This invention provides a process for making a semiconductor device with reduced capacitance between adjacent conductors. This process can include applying and gelling one or more solutions between and over conductors 24 and drying the wet gel to create at least porous dielectric sublayers 28 and 29. By varying the composition of the solutions, gelling conditions, drying temperature, composition of the solvents in the wet gel, or a combination of these approaches, the porosity of the sublayers may be tailored individually. A non-porous dielectric layer 30 may be formed over porous layer 28, which may complete an interlayer dielectric. A novel process for creating the porous dielectric layer is disclosed, which can be completed at vacuum or ambient pressures, yet results in porosity, pore size, and shrinkage of the dielectric during drying comparable to that previously attainable only by drying gels at supercritical pressure.
摘要翻译：本发明提供一种在相邻导体之间制造具有降低的电容的半导体器件的方法。该方法可以包括在导体24之间和之上施加和凝胶化一种或多种溶液并干燥湿凝胶以产生至少多孔介电子层28和29.通过改变溶液的组成，胶凝条件，干燥温度，溶剂的组成在湿凝胶中，或这些方法的组合，子层的孔隙率可以单独定制。无孔介电层30可以形成在多孔层28之上，多孔层28可以完成层间电介质。公开了一种用于产生多孔介电层的新方法，其可以在真空或环境压力下完成，但是在干燥期间导致电介质的孔隙率，孔径和收缩相当于仅通过在超临界压力下干燥凝胶可获得的电介质层。

19. 发明授权

US5529640A Epitaxial metal-insulator-metal-semiconductor structures 失效
标题翻译：外延金属 - 绝缘体 - 金属 - 半导体结构
公开(公告)号：US5529640A
公开(公告)日：1996-06-25
申请号：US302302
申请日：1994-09-08
申请人： Chih-Chen Cho
发明人： Chih-Chen Cho
IPC分类号： H01L21/28 , H01L21/285 , H01L21/314 , H01L21/3205 , H01L29/51 , H01L29/06
CPC分类号： H01L21/28194 , H01L21/28512 , H01L21/314 , H01L21/32051 , H01L29/51
摘要： In one form of the invention, a method for the growth of an epitaxial insulator-metal structure on a semiconductor surface comprising the steps of maintaining the semiconductor surface at a pressure below approximately 1.times.10.sup.-7 mbar, maintaining the semiconductor surface at a substantially fixed first temperature between approximately 25.degree. C. and 400.degree. C., depositing an epitaxial metal layer on the semiconductor surface, adjusting the semiconductor surface to a substantially fixed second temperature between approximately 25.degree. C. and 200.degree. C., starting a deposition of epitaxial CaF.sub.2 on the first metal layer, ramping the second temperature to a third substantially fixed temperature between 200.degree. C. and 500.degree. C. over a time period, maintaining the third temperature until the epitaxial CaF.sub.2 has deposited to a desired thickness, and stopping the deposition of epitaxial CaF.sub.2 on the first metal layer.
摘要翻译：在本发明的一种形式中，一种用于在半导体表面上生长外延绝缘体 - 金属结构的方法包括以下步骤：将半导体表面保持在低于约1×10-7毫巴的压力，将半导体表面保持在基本固定的第一在约25℃至400℃之间的温度下，在半导体表面上沉积外延金属层，将半导体表面调节至约25℃至200℃之间的基本固定的第二温度，开始沉积外延 CaF2在第一金属层上，在一段时间内将第二温度升至第二温度至200℃至500℃之间的第三基本上固定的温度，保持第三温度，直到外延CaF 2沉积到期望的厚度，并停止在第一金属层上沉积外延CaF 2。

20. 发明授权

US5407860A Method of forming air gap dielectric spaces between semiconductor leads 失效
标题翻译：在半导体引线之间形成气隙电介质空间的方法
公开(公告)号：US5407860A
公开(公告)日：1995-04-18
申请号：US250064
申请日：1994-05-27
申请人： Richard A. Stoltz , Howard Tigelaar , Chih-Chen Cho
发明人： Richard A. Stoltz , Howard Tigelaar , Chih-Chen Cho
IPC分类号： H01L21/768 , H01L21/44
CPC分类号： H01L21/7682 , H01L21/76834
摘要： This is a device and method of forming air gaps in between metal leads comprising. The method comprising: forming the metal leads 51-53 on an insulating layer 50; depositing a nonwetting material layer 56 on the metal leads 51-53 and the insulating layer 50; anisotropically etching the nonwetting material 56 to remove the nonwetting material 56 from open areas and leaving the nonwetting material on side walls of the metal leads 51-53; and depositing a dielectric layer 60 on top of the metal leads 51-53, and the insulating layer 50, whereby the air gaps 58 are produced in between the metal leads 51-53 below the dielectric layer 60. The method may include anisotropically etching at an angle, not vertical, whereby the etching allows removal of the nonwetting material from exterior side walls of the metal leads. The method may also include leaving the nonwetting material layer in between the metal leads. The deposition of the dielectric layer may utilize plasma deposition and spin on techniques.
摘要翻译：这是在金属引线之间形成气隙的装置和方法，包括。该方法包括：在绝缘层50上形成金属引线51-53; 在金属引线51-53和绝缘层50上沉积非润湿材料层56; 各向异性地蚀刻不润湿材料56以从开放区域除去非润湿材料56，并将非润湿材料留在金属引线51-53的侧壁上; 以及在金属引线51-53和绝缘层50的顶部上沉积电介质层60，由此在电介质层60下方的金属引线51-53之间产生气隙58.该方法可以包括各向异性蚀刻角度不垂直，由此蚀刻允许从金属引线的外侧壁去除非润湿材料。该方法还可以包括将非润湿材料层留在金属引线之间。电介质层的沉积可以利用等离子体沉积和旋转技术。

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