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11. 发明申请

WO2013154574A1 CONVERSION OF STRAIN-INDUCING BUFFER TO ELECTRICAL INSULATOR 审中-公开
标题翻译：应变诱导缓冲器对电绝缘子的转换
公开(公告)号：WO2013154574A1
公开(公告)日：2013-10-17
申请号：PCT/US2012/033472
申请日：2012-04-13
申请人： INTEL CORPORATION , CAPPELLANI, Annalisa , LE, Van H. , GLASS, Glenn A. , KUHN, Kelin J. , CEA, Stephen M.
发明人： CAPPELLANI, Annalisa , LE, Van H. , GLASS, Glenn A. , KUHN, Kelin J. , CEA, Stephen M.
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/66795 , H01L21/02233 , H01L21/02236 , H01L21/02238 , H01L21/02241 , H01L21/02255 , H01L21/02304 , H01L21/02439 , H01L21/0245 , H01L21/02455 , H01L21/02488 , H01L21/02532 , H01L21/306 , H01L21/76 , H01L21/7624 , H01L21/76283 , H01L29/0603 , H01L29/0642 , H01L29/0653 , H01L29/0657 , H01L29/1054 , H01L29/7378 , H01L29/785 , H01L33/12 , H05K1/18
摘要： Techniques are disclosed for converting a strain-inducing semiconductor buffer layer into an electrical insulator at one or more locations of the buffer layer, thereby allowing an above device layer to have a number of benefits, which in some embodiments include those that arise from being grown on a strain-inducing buffer and having a buried electrical insulator layer. For instance, having a buried electrical insulator layer (initially used as a strain-inducing buffer during fabrication of the above active device layer) between the Fin and substrate of a non-planar integrated transistor circuit may simultaneously enable a low-doped Fin with high mobility, desirable device electrostatics and elimination or otherwise reduction of substrate junction leakage. Also, the presence of such an electrical insulator under the source and drain regions may further significantly reduce junction leakage. In some embodiments, substantially the entire buffer layer is converted to an electrical insulator.
摘要翻译：公开了用于将应变诱导半导体缓冲层转变成缓冲层的一个或多个位置处的电绝缘体的技术，从而允许上述器件层具有许多益处，其在一些实施例中包括从生长出来的那些在应变诱导缓冲器上并具有埋入的电绝缘体层。例如，在非平面集成晶体管电路的Fin和衬底之间具有埋入的电绝缘体层（最初用作制造上述有源器件层期间的应变诱导缓冲器）可以同时使得具有高的低掺杂Fin 移动性，期望的器件静电，以及消除或以其他方式减少衬底结泄漏。此外，源极和漏极区域下的这种电绝缘体的存在可以进一步显着减少结漏电。在一些实施例中，基本上整个缓冲层被转换成电绝缘体。

12. 发明申请

WO2009079159A3 SYSTEMS AND METHODS TO INCREASE UNIAXIAL COMPRESSIVE STRESS IN TRI-GATE TRANSISTORS 审中-公开
公开(公告)号：WO2009079159A3
公开(公告)日：2009-06-25
申请号：PCT/US2008/084344
申请日：2008-11-21
申请人： INTEL CORPORATION , RAKSHIT, Titash , GILES, Martin D. , GHANI, Tahir , MURTHY, Anand , CEA, Stephen M.
发明人： RAKSHIT, Titash , GILES, Martin D. , GHANI, Tahir , MURTHY, Anand , CEA, Stephen M.
IPC分类号： H01L21/336 , H01L29/78
摘要： A transistor structure that increases uniaxial compressive stress on the channel region of a tri-gate transistor comprises at least two semiconductor bodies formed on a substrate, each semiconductor body having a pair of laterally opposite sidewalls and a top surface, a common source region formed on one end of the semiconductor bodies, wherein the common source region is coupled to all of the at least two semiconductor bodies, a common drain region formed on another end of the semiconductor bodies, wherein the common drain region is coupled to all of the at least two semiconductor bodies, and a common gate electrode formed over the at least two semiconductor bodies, wherein the common gate electrode provides a gate electrode for each of the at least two semiconductor bodies and wherein the common gate electrode has a pair of laterally opposite sidewalls that are substantially perpendicular to the sidewalls of the semiconductor bodies.

13. 发明申请

WO2009012053A3 ISOLATED TRI-GATE TRANSISTOR FABRICATED ON BULK SUBSTRATE 审中-公开
标题翻译：散装基板上制造的隔离式三栅极晶体管
公开(公告)号：WO2009012053A3
公开(公告)日：2009-03-12
申请号：PCT/US2008068855
申请日：2008-06-30
申请人： INTEL CORP , RIOS RAFAEL , KAVALIEROS JACK T , CEA STEPHEN M
发明人： RIOS RAFAEL , KAVALIEROS JACK T , CEA STEPHEN M
IPC分类号： H01L21/336 , H01L21/3205
CPC分类号： H01L29/66795 , H01L29/785
摘要： A method of forming an isolated tri-gate semiconductor body comprises patterning a bulk substrate to form a fin structure, depositing an insulating material around the fin structure, recessing the insulating material to expose a portion of the fin structure that will be used for the tri-gate semiconductor body, depositing a nitride cap over the exposed portion of the fin structure to protect the exposed portion of the fin structure, and carrying out a thermal oxidation process to oxidize an unprotected portion of the fin structure below the nitride cap. The oxidized portion of the fin isolates the semiconductor body that is being protected by the nitride cap. The nitride cap may then be removed. The thermal oxidation process may comprise annealing the substrate at a temperature between around 900°C and around 1100°C for a time duration between around 0.5 hours and around 3 hours.
摘要翻译：一种形成隔离的三栅极半导体主体的方法包括：图案化体衬底以形成鳍状结构;在鳍状结构周围沉积绝缘材料;使绝缘材料凹陷以暴露将用于三端口的鳍状结构的一部分在所述鳍结构的暴露部分上沉积氮化物帽以保护所述鳍结构的暴露部分，并且执行热氧化工艺以氧化所述氮化物帽下方的所述鳍结构的未受保护部分。鳍状物的氧化部分隔离被氮化物帽保护的半导体主体。然后可以去除氮化物帽。热氧化工艺可以包括在约900℃和约1100℃之间的温度下退火衬底约0.5小时至约3小时之间的持续时间。

14. 发明申请

WO2016204755A1 VERTICAL INTEGRATION SCHEME AND CIRCUIT ELEMENTS ARCHITECTURE FOR AREA SCALING OF SEMICONDUCTOR DEVICES 审中-公开
标题翻译：垂直整合方案和电路元件建筑物半导体器件的区域划分
公开(公告)号：WO2016204755A1
公开(公告)日：2016-12-22
申请号：PCT/US2015/036286
申请日：2015-06-17
申请人： INTEL CORPORATION , MEHANDRU, Rishabh , MORROW, Patrick , KUMAR, Ranjith , WEBER, Cory, E. , KIM, Seiyon , CEA, Stephen, M. , GHANI, Tahir
发明人： MEHANDRU, Rishabh , MORROW, Patrick , KUMAR, Ranjith , WEBER, Cory, E. , KIM, Seiyon , CEA, Stephen, M. , GHANI, Tahir
IPC分类号： H01L29/78 , H01L21/336 , H01L21/8238
CPC分类号： H01L29/66795 , H01L21/8221 , H01L21/823431 , H01L21/823821 , H01L21/845 , H01L27/0688 , H01L27/10826 , H01L27/1211 , H01L29/78 , H01L29/785
摘要： Vertical integration schemes and circuit elements architectures for area scaling of semiconductor devices are described. In an example, an inverter structure includes a semiconductor fin separated vertically into an upper region and a lower region. A first plurality of gate structures is included for controlling the upper region of the semiconductor fin. A second plurality of gate structures is included for controlling the lower region of the semiconductor fin. The second plurality of gate structures has a conductivity type opposite the conductivity type of the first plurality of gate structures.
摘要翻译：描述用于半导体器件的区域缩放的垂直集成方案和电路元件架构。在一个示例中，逆变器结构包括垂直分离成上部区域和下部区域的半导体鳍片。包括用于控制半导体鳍片的上部区域的第一多个栅极结构。包括第二多个栅极结构以控制半导体鳍片的下部区域。第二多个栅极结构具有与第一多个栅极结构的导电类型相反的导电类型。

15. 发明申请

WO2015094167A1 NMOS AND PMOS STRAINED DEVICES WITHOUT RELAXED SUBSTRATES 审中-公开
标题翻译：没有松散基板的NMOS和PMOS应变器件
公开(公告)号：WO2015094167A1
公开(公告)日：2015-06-25
申请号：PCT/US2013/075452
申请日：2013-12-16
申请人： INTEL CORPORATION , CEA, Stephen M. , KOTLYAR, Roza , KENNEL, Harold, W. , MURTHY, Anand, S. , GLASS, Glenn, A. , KUHN, Kelin, J. , GHANI, Tahir
发明人： CEA, Stephen M. , KOTLYAR, Roza , KENNEL, Harold, W. , MURTHY, Anand, S. , GLASS, Glenn, A. , KUHN, Kelin, J. , GHANI, Tahir
IPC分类号： H01L21/336
CPC分类号： H01L29/1054 , H01L21/823807 , H01L21/823821 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/045 , H01L29/161 , H01L29/165 , H01L29/66431 , H01L29/66818 , H01L29/7781 , H01L29/7782
摘要： The embodiments herein provide semiconductor devices and methods related to strained NMOS and PMOS devices without relaxed substrates, and systems incorporating such semiconductor devices and methods therefor.
摘要翻译：本文的实施例提供了与没有松弛衬底的应变NMOS和PMOS器件有关的半导体器件和方法，以及包含这种半导体器件的系统及其方法。

16. 发明申请

WO2013095650A1 NANOWIRE STRUCTURES HAVING NON-DISCRETE SOURCE AND DRAIN REGIONS 审中-公开
标题翻译：具有非离散源和排水区的纳米结构
公开(公告)号：WO2013095650A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067232
申请日：2011-12-23
申请人： INTEL CORPORATION , CEA, Stephen M. , CAPPELLANI, Annalisa , GILES, Martin D. , RIOS, Rafael , KIM, Seiyon , KUHN, Kelin J.
发明人： CEA, Stephen M. , CAPPELLANI, Annalisa , GILES, Martin D. , RIOS, Rafael , KIM, Seiyon , KUHN, Kelin J.
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/78618 , B82Y40/00 , H01L21/268 , H01L29/0673 , H01L29/0847 , H01L29/42356 , H01L29/42392 , H01L29/66477 , H01L29/66742 , H01L29/66787 , H01L29/66977 , H01L29/7839 , H01L29/7845 , H01L29/7848 , H01L29/78651 , H01L29/78684 , H01L29/78696
摘要： Nanowire structures having non-discrete source and drain regions are described. For example, a semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate. Each of the nanowires includes a discrete channel region disposed in the nanowire. A gate electrode stack surrounds the plurality of vertically stacked nanowires. A pair of non-discrete source and drain regions is disposed on either side of, and adjoining, the discrete channel regions of the plurality of vertically stacked nanowires.
摘要翻译：描述了具有非离散源极和漏极区域的纳米线结构。例如，半导体器件包括设置在衬底上方的多个垂直堆叠的纳米线。每个纳米线包括设置在纳米线中的离散通道区域。栅电极堆叠围绕多个垂直堆叠的纳米线。一对非离散源极和漏极区域设置在多个垂直堆叠的纳米线的离散沟道区域的两侧并邻接。

17. 发明申请

WO2013095646A1 CMOS NANOWIRE STRUCTURE 审中-公开
标题翻译： CMOS纳米结构
公开(公告)号：WO2013095646A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067225
申请日：2011-12-23
申请人： INTEL CORPORATION , KIM, Seiyon , KUHN, Kelin, J. , GHANI, Tahir , MURTHY, Anand, S. , CAPPELLANI, Annalisa , CEA, Stephen, M. , RIOS, Rafael , GLASS, Glenn, A.
发明人： KIM, Seiyon , KUHN, Kelin, J. , GHANI, Tahir , MURTHY, Anand, S. , CAPPELLANI, Annalisa , CEA, Stephen, M. , RIOS, Rafael , GLASS, Glenn, A.
IPC分类号： H01L21/8238
CPC分类号： H01L21/823821 , B82Y10/00 , H01L21/8238 , H01L21/823807 , H01L21/823828 , H01L21/84 , H01L21/845 , H01L27/092 , H01L27/0924 , H01L27/12 , H01L27/1203 , H01L27/1211 , H01L29/0673 , H01L29/0676 , H01L29/1033 , H01L29/42356 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/7853
摘要： Complimentary metal-oxide-semiconductor nanowire structures are described. For example, a semiconductor structure includes a first semiconductor device. The first semiconductor device includes a first nanowire disposed above a substrate. The first nanowire has a mid-point a first distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. A first gate electrode stack completely surrounds the discrete channel region of the first nanowire. The semiconductor structure also includes a second semiconductor device. The second semiconductor device includes a second nanowire disposed above the substrate. The second nanowire has a mid-point a second distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. The first distance is different from the second distance. A second gate electrode stack completely surrounds the discrete channel region of the second nanowire.
摘要翻译：描述了免费的金属氧化物半导体纳米线结构。例如，半导体结构包括第一半导体器件。第一半导体器件包括设置在衬底之上的第一纳米线。第一纳米线具有在衬底上方的第一距离的中点，并且包括在离散通道区域的任一侧上的离散沟道区域和源极和漏极区域。第一栅极电极堆叠完全包围第一纳米线的离散通道区域。半导体结构还包括第二半导体器件。第二半导体器件包括设置在衬底上方的第二纳米线。第二纳米线在衬底上方具有第二距离的中点，并且包括在离散通道区域的任一侧上的离散沟道区域和源极和漏极区域。第一距离与第二距离不同。第二栅极电极堆叠完全围绕第二纳米线的离散通道区域。

18. 发明申请

WO2012074872A3 SILICON AND SILICON GERMANIUM NANOWIRE STRUCTURES 审中-公开
标题翻译：硅和硅锗纳米结构
公开(公告)号：WO2012074872A3
公开(公告)日：2012-10-04
申请号：PCT/US2011062059
申请日：2011-11-23
申请人： INTEL CORP , KUHN KELIN J , KIM SEIYON , RIOS RAFAEL , CEA STEPHEN M , GILES MARTIN D , CAPPELLANI ANNALISA , RAKSHIT TITASH , CHANG PETER , RACHMADY WILLY
发明人： KUHN KELIN J , KIM SEIYON , RIOS RAFAEL , CEA STEPHEN M , GILES MARTIN D , CAPPELLANI ANNALISA , RAKSHIT TITASH , CHANG PETER , RACHMADY WILLY
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/0673 , B82Y10/00 , H01L21/76224 , H01L27/0922 , H01L27/1203 , H01L29/0676 , H01L29/1033 , H01L29/16 , H01L29/165 , H01L29/41733 , H01L29/42392 , H01L29/66439 , H01L29/66742 , H01L29/66795 , H01L29/775 , H01L29/7848 , H01L29/785 , H01L29/78618 , H01L29/78654 , H01L29/78684 , H01L29/78696
摘要： Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.
摘要翻译：描述形成微电子结构的方法。这些方法的实施例包括形成纳米线装置，其包括基板，该基板包括与间隔物相邻的源极/漏极结构，以及设置在间隔物之间的纳米线通道结构，其中纳米线通道结构在彼此之上垂直堆叠。

19. 发明申请

WO2012040075A3 NON-PLANAR DEVICE HAVING UNIAXIALLY STRAINED FIN AND METHOD OF MAKING SAME 审中-公开
标题翻译：具有非均匀应变FIN的非平面设备及其制造方法
公开(公告)号：WO2012040075A3
公开(公告)日：2012-06-07
申请号：PCT/US2011052084
申请日：2011-09-19
申请人： INTEL CORP , CEA STEPHEN M , KOTLYAR ROZA , KAVALIEROS JACK T , GILES MARTIN D , GHANI TAHIR , KUHN KELIN J , KUHN MARKUS , ZELICK NANCY M
发明人： CEA STEPHEN M , KOTLYAR ROZA , KAVALIEROS JACK T , GILES MARTIN D , GHANI TAHIR , KUHN KELIN J , KUHN MARKUS , ZELICK NANCY M
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7848 , H01L29/1054 , H01L29/66795 , H01L29/7849 , H01L29/785
摘要： A method and a device made according to the method. The method comprises providing a substrate including a first material, and providing a fin including a second material, the fin being disposed on the substrate and having a device active portion, the first material and the second material presenting a lattice mismatch between respective crystalline structures thereof. Providing the fin includes providing a biaxially strained film including the second material on the substrate; and removing parts of the biaxially strained film to form a substantially uniaxially strained fin therefrom.
摘要翻译：根据该方法制造的方法和装置。该方法包括提供包括第一材料的基底，并且提供包括第二材料的翅片，所述翅片设置在所述基底上并且具有器件活性部分，所述第一材料和所述第二材料在其各自的结晶结构之间呈现晶格失配。提供散热片包括在基板上提供包括第二材料的双轴应变膜; 并除去双轴应变膜的部分以形成基本上单轴应变的翅片。

20. 发明申请

WO2011087605A2 WRAP-AROUND CONTACTS FOR FINFET AND TRI-GATE DEVICES 审中-公开
标题翻译： FINFET和三门设备的缠绕接头
公开(公告)号：WO2011087605A2
公开(公告)日：2011-07-21
申请号：PCT/US2010/058670
申请日：2010-12-02
申请人： INTEL CORPORATION , CEA, Stephen M. , MEHANDRU, Rishabh , SHIFREN, Lucian , KUHN, Kelin
发明人： CEA, Stephen M. , MEHANDRU, Rishabh , SHIFREN, Lucian , KUHN, Kelin
CPC分类号： H01L29/785 , H01L29/41791 , H01L29/66795 , H01L29/7848 , H01L2029/7858
摘要： A semiconductor device comprises a substrate and a semiconductor body formed on the substrate. The semiconductor body comprises a source region; and a drain region. The source region or the drain region, or combinations thereof, comprises a first side surface, a second side surface, and a top surface. The first side surface is opposite the second side surface, the top surface is opposite the bottom surface. The source region or the drain region, or combinations thereof, comprise a metal layer formed on the substantially all of the first side surface, substantially all of the second side surface, and the top surface.
摘要翻译：半导体器件包括形成在衬底上的衬底和半导体本体。半导体主体包括源极区域; 和漏区。源区或漏区，或其组合包括第一侧表面，第二侧表面和顶表面。第一侧表面与第二侧表面相对，顶表面与底表面相对。源极区域或漏极区域或其组合包括形成在基本上所有第一侧表面上的基本上所有的第二侧表面和顶表面上的金属层。

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