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11. 发明申请

US20080237635A1 STRUCTURE AND METHOD FOR STRAINED TRANSISTOR DIRECTLY ON INSULATOR 有权
标题翻译：绝缘子上直线型应变晶体管的结构与方法
公开(公告)号：US20080237635A1
公开(公告)日：2008-10-02
申请号：US11694273
申请日：2007-03-30
申请人： Voon-Yew Thean , Bich-Yen Nguyen
发明人： Voon-Yew Thean , Bich-Yen Nguyen
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823878 , H01L27/1203 , H01L27/1207 , H01L29/7842
摘要： A semiconductor device (10) comprising a substrate (12) and an oxide layer (14) formed over the substrate is provided. The semiconductor device further includes a first semiconductor layer (16) having a first lattice constant formed directly over the oxide layer. The semiconductor device further includes a second semiconductor layer (26) having a second lattice constant formed directly over the first semiconductor layer, wherein the second lattice constant is different from the first lattice constant.
摘要翻译：提供一种半导体器件（10），其包括衬底（12）和形成在衬底上的氧化物层（14）。半导体器件还包括具有直接形成在氧化物层上的第一晶格常数的第一半导体层（16）。半导体器件还包括具有直接形成在第一半导体层上的第二晶格常数的第二半导体层（26），其中第二晶格常数不同于第一晶格常数。

12. 发明授权

US07419866B2 Process of forming an electronic device including a semiconductor island over an insulating layer 有权
标题翻译：在绝缘层上形成包括半导体岛的电子器件的工艺
公开(公告)号：US07419866B2
公开(公告)日：2008-09-02
申请号：US11375893
申请日：2006-03-15
申请人： Mariam G. Sadaka , Bich-Yen Nguyen , Voon-Yew Thean
发明人： Mariam G. Sadaka , Bich-Yen Nguyen , Voon-Yew Thean
IPC分类号： H01L21/8238
CPC分类号： H01L21/32 , H01L21/02238 , H01L21/02255 , H01L21/31662 , H01L21/84
摘要： A process of forming an electronic device can include forming a patterned oxidation-resistant layer over a semiconductor layer that overlies a substrate, and patterning the semiconductor layer to form a semiconductor island. The semiconductor island includes a first surface and a second surface opposite the first surface, and the first surface lies closer to the substrate, as compared to the second surface. The process can also include forming an oxidation-resistant material along a side of the semiconductor island or selectively depositing a semiconductor material along a side of the semiconductor island. The process can further include exposing the patterned oxidation-resistant layer and the semiconductor island to an oxygen-containing ambient, wherein a first portion of the semiconductor island along the first surface is oxidized during exposing the patterned oxidation-resistant layer, the semiconductor island, and the oxidation-resistant material to an oxygen-containing ambient.
摘要翻译：形成电子器件的方法可以包括在覆盖在衬底上的半导体层上形成图案化的抗氧化层，并且图案化半导体层以形成半导体岛。半导体岛包括与第一表面相对的第一表面和第二表面，并且第一表面与第二表面相比更靠近基底。该方法还可以包括沿着半导体岛的一侧形成耐氧化材料或者沿半导体岛的一侧选择性地沉积半导体材料。该方法还可以包括将图案化的抗氧化层和半导体岛暴露于含氧环境中，其中沿着第一表面的半导体岛的第一部分在曝光图案化的抗氧化层，半导体岛，并将抗氧化材料转化为含氧环境。

13. 发明授权

US07413970B2 Process of forming an electronic device including a semiconductor fin 有权
标题翻译：形成包括半导体鳍片的电子器件的工艺
公开(公告)号：US07413970B2
公开(公告)日：2008-08-19
申请号：US11375894
申请日：2006-03-15
申请人： Da Zhang , Bich-Yen Nguyen
发明人： Da Zhang , Bich-Yen Nguyen
IPC分类号： H01L29/06 , H01L21/3205
CPC分类号： H01L29/785 , H01L29/4908 , H01L29/66507 , H01L29/66795 , H01L29/78684
摘要： An electronic device can include a semiconductor fin overlying an insulating layer. The electronic device can also include a semiconductor layer overlying the semiconductor fin. The semiconductor layer can have a first portion and a second portion that are spaced-apart from each other. In one aspect, the electronic device can include a conductive member that lies between and spaced-apart from the first and second portions of the semiconductor layer. The electronic device can also include a metal-semiconductor layer overlying the semiconductor layer. In another aspect, the semiconductor layer can abut the semiconductor fin and include a dopant. In a further aspect, a process of forming the electronic device can include reacting a metal-containing layer and a semiconductor layer to form a metal-semiconductor layer. In another aspect, a process can include forming a semiconductor layer, including a dopant, abutting a wall surface of a semiconductor fin.
摘要翻译：电子器件可以包括覆盖绝缘层的半导体鳍片。电子器件还可以包括覆盖半导体鳍片的半导体层。半导体层可以具有彼此间隔开的第一部分和第二部分。在一个方面，电子设备可以包括位于半导体层的第一和第二部分之间并与之隔开的导电构件。电子器件还可以包括覆盖半导体层的金属 - 半导体层。在另一方面，半导体层可以邻接半导体鳍并包括掺杂剂。在另一方面，形成电子器件的方法可以包括使含金属层和半导体层反应以形成金属 - 半导体层。在另一方面，一种方法可以包括形成邻接半导体鳍片的壁表面的包括掺杂剂的半导体层。

14. 发明申请

US20080124858A1 SELECTIVE STRESS RELAXATION BY AMORPHIZING IMPLANT IN STRAINED SILICON ON INSULATOR INTEGRATED CIRCUIT 审中-公开
标题翻译：绝缘子集成电路中应变硅中的植入物的选择性应力放松
公开(公告)号：US20080124858A1
公开(公告)日：2008-05-29
申请号：US11462773
申请日：2006-08-07
申请人： Bich-Yen Nguyen , Voon-Yew Thean
发明人： Bich-Yen Nguyen , Voon-Yew Thean
IPC分类号： H01L21/8238
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823814
摘要： A semiconductor fabrication process includes forming an NMOS gate electrode overlying a biaxially strained NMOS active region and forming a PMOS gate electrode overlying a biaxially strained PMOS active region. Amorphous silicon is created in a PMOS source/drain region to reduce PMOS channel direction tensile stress. A PMOS source/drain implant is performed in the amorphous PMOS source/drain. Creating amorphous silicon in the PMOS source/drain may include implanting an electrically neutral species (e.g., Ge, Ga, or Xe). The wafer then may be annealed and a second PMOS amorphizing implant performed. PMOS halo, source/drain extension, and deep source/drain implants may then be performed. Following the first amorphizing implant, a sacrificial compressive stressor may be formed over the PMOS region, the wafer annealed to recrystallize the amorphous PMOS region, and the compressive stressor removed. NMOS source/drain implants may be performed without a preceding amorphizing implant or with a low energy amorphizing implant.
摘要翻译：半导体制造工艺包括形成覆盖双轴应变NMOS有源区的NMOS栅电极，并形成覆盖双轴应变PMOS有源区的PMOS栅电极。在PMOS源极/漏极区域中产生非晶硅以减少PMOS沟道方向的拉伸应力。在非晶PMOS源极/漏极中执行PMOS源极/漏极注入。在PMOS源极/漏极中产生非晶硅可以包括植入电中性物质（例如Ge，Ga或Xe）。然后可以对晶片进行退火，并执行第二个PMOS非晶化注入。然后可以执行PMOS光晕，源极/漏极延伸和深源/漏极注入。在第一非晶化植入物之后，可以在PMOS区域上形成牺牲压应力器，晶片退火以使非晶态PMOS区域重结晶，并且去除压应力。可以在没有前面的非晶化植入物或低能量非晶化植入物的情况下进行NMOS源极/漏极植入物。

15. 发明申请

US20080014688A1 SELECTIVE UNIAXIAL STRESS MODIFICATION FOR USE WITH STRAINED SILICON ON INSULATOR INTEGRATED CIRCUIT 有权
标题翻译：绝缘子集成电路上使用应变硅的选择性单相应力变形
公开(公告)号：US20080014688A1
公开(公告)日：2008-01-17
申请号：US11428953
申请日：2006-07-06
申请人： Voon-Yew Thean , Bich-Yen Nguyen , Da Zhang
发明人： Voon-Yew Thean , Bich-Yen Nguyen , Da Zhang
IPC分类号： H01L21/8234
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203 , H01L29/66628 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： A semiconductor fabrication process includes masking a first region, e.g., an NMOS region, of a semiconductor wafer, e.g., a biaxial, tensile strained silicon on insulator (SOI) wafer and creating recesses in source/drain regions of a second wafer region, e.g., a PMOS region. The wafer is then annealed in an ambient that promotes migration of silicon. The source/drain recesses are filled with source/drain structures, e.g., by epitaxial growth. The anneal ambient may include a hydrogen bearing species, e.g., H2 or GeH2, maintained at a temperature in the range of approximately 800 to 1000° C. The second region may be silicon and the source/drain structures may be silicon germanium. Creating the recesses may include creating shallow recesses with a first etch process, performing an amorphizing implant to create an amorphous layer, performing an inert ambient anneal to recrystallize the amorphous layer, and deepening the shallow recesses with a second etch process.
摘要翻译：半导体制造工艺包括掩蔽半导体晶片的第一区域（例如，NMOS区域），例如双轴拉伸应变绝缘体上硅（SOI）晶片，并在第二晶片区域的源/漏区域中产生凹陷，例如，PMOS区域。然后将晶片在促进硅迁移的环境中退火。源极/漏极凹槽用源极/漏极结构填充，例如通过外延生长。退火环境可以包括保持在约800至1000℃范围内的温度的含氢物质，例如H 2 H 2或GeH 2 H 2。第二区域可以是硅，并且源极/漏极结构可以是硅锗。创建凹槽可以包括用第一蚀刻工艺创建浅凹槽，执行非晶化注入以产生非晶层，执行惰性环境退火以使非晶层重结晶，以及用第二蚀刻工艺加深浅凹槽。

16. 发明申请

US20070262385A1 SELECTIVE UNIAXIAL STRESS RELAXATION BY LAYOUT OPTIMIZATION IN STRAINED SILICON ON INSULATOR INTEGRATED CIRCUIT 有权
标题翻译：绝缘子集成电路中应变硅中布线优化的选择性单相应力放松
公开(公告)号：US20070262385A1
公开(公告)日：2007-11-15
申请号：US11383113
申请日：2006-05-12
申请人： Bich-Yen Nguyen , Voon-Yew Thean
发明人： Bich-Yen Nguyen , Voon-Yew Thean
IPC分类号： H01L27/12 , H01L21/8238 , H01L27/01 , H01L31/0392
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/0207 , H01L29/1033 , H01L29/41758 , H01L29/41775 , H01L29/6659 , H01L29/7843 , H01L29/7848 , H01L29/78654
摘要： An integrated circuit includes NMOS and PMOS transistors. The NMOS has a strained channel having first and second stress values along first and second axes respectively. The PMOS has a strained channel having third and fourth stress values along the first and second axes. The first value stress differs from the third value and the second value differs from the fourth value. The NMOS and PMOS have a common length (L) and effective width (W), but differ in length of diffusion (SA) and/or width of source/drain (WS). The NMOS WS may exceed the PMOS WS. The NMOS may include multiple dielectric structures in the active layer underlying the gate. The SA of the PMOS may be less than the SA of the NMOS. The integrated circuit may include a tensile stressor of silicon nitride over the NMOS and a compressive stressor of silicon nitride over the PMOS.
摘要翻译：集成电路包括NMOS和PMOS晶体管。 NMOS具有分别具有沿着第一和第二轴的第一和第二应力值的应变通道。 PMOS具有沿第一和第二轴具有第三和第四应力值的应变通道。第一值应力与第三值不同，第二值与第四值不同。 NMOS和PMOS具有公共长度（L）和有效宽度（W），但扩散长度（SA）和/或源极/漏极（WS）的宽度不同。 NMOS WS可能超过PMOS WS。 NMOS可以包括位于栅极下方的有源层中的多个电介质结构。 PMOS的SA可以小于NMOS的SA。集成电路可以包括氮化硅在NMOS上的拉伸应力源和在PMOS上的氮化硅的压应力。

17. 发明申请

US20070241403A1 Integrated circuit with different channel materials for P and N channel transistors and method therefor 有权
标题翻译：用于P和N沟道晶体管的不同沟道材料的集成电路及其方法
公开(公告)号：US20070241403A1
公开(公告)日：2007-10-18
申请号：US11402395
申请日：2006-04-12
申请人： Voon-Yew Thean , Bich-Yen Nguyen , Mariam Sadaka , Victor Vartanian , Ted White
发明人： Voon-Yew Thean , Bich-Yen Nguyen , Mariam Sadaka , Victor Vartanian , Ted White
IPC分类号： H01L29/76 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823878 , H01L21/8258 , H01L27/1203
摘要： A substrate includes a first region and a second region. The first region comprises a III-nitride layer, and the second region comprises a first semiconductor layer. A first transistor (such as an n-type transistor) is formed in and on the III-nitride layer, and a second transistor (such as a p-type transistor) is formed in and on the first semiconductor layer. The III-nitride layer may be indium nitride. In the first region, the substrate may include a second semiconductor layer, a graded transition layer over the second semiconductor layer, and a buffer layer over the transition layer, where the III-nitride layer is over the buffer layer. In the second region, the substrate may include the second semiconductor layer and an insulating layer over the second semiconductor layer, where the first semiconductor layer is over the insulating layer.
摘要翻译：衬底包括第一区域和第二区域。第一区域包括III族氮化物层，第二区域包括第一半导体层。在III族氮化物层上形成第一晶体管（例如n型晶体管），并且在第一半导体层上形成第二晶体管（例如p型晶体管）。 III族氮化物层可以是氮化铟。在第一区域中，衬底可以包括第二半导体层，在第二半导体层上的渐变过渡层，以及过渡层上的缓冲层，其中III族氮化物层在缓冲层之上。在第二区域中，衬底可以包括第二半导体层和在第二半导体层上的绝缘层，其中第一半导体层在绝缘层之上。

18. 发明授权

US07282415B2 Method for making a semiconductor device with strain enhancement 有权
标题翻译：制造具有应变增强的半导体器件的方法
公开(公告)号：US07282415B2
公开(公告)日：2007-10-16
申请号：US11092291
申请日：2005-03-29
申请人： Da Zhang , Bich-Yen Nguyen , Voon-Yew Thean , Yasuhito Shiho , Veer Dhandapani
发明人： Da Zhang , Bich-Yen Nguyen , Voon-Yew Thean , Yasuhito Shiho , Veer Dhandapani
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L29/165 , H01L29/66545 , H01L29/66628 , H01L29/66636
摘要： A semiconductor device with strain enhancement is formed by providing a semiconductor substrate and an overlying control electrode having a sidewall. An insulating layer is formed adjacent the sidewall of the control electrode. The semiconductor substrate and the control electrode are implanted to form first and second doped current electrode regions, a portion of each of the first and second doped current electrode regions being driven to underlie both the insulating layer and the control electrode in a channel region of the semiconductor device. The first and second doped current electrode regions are removed from the semiconductor substrate except for underneath the control electrode and the insulating layer to respectively form first and second trenches. An insitu doped material containing a different lattice constant relative to the semiconductor substrate is formed within the first and second trenches to function as first and second current electrodes of the semiconductor device.
摘要翻译：通过提供半导体衬底和具有侧壁的上覆控制电极来形成具有应变增强的半导体器件。在控制电极的侧壁附近形成绝缘层。注入半导体衬底和控制电极以形成第一和第二掺杂电流电极区域，第一和第二掺杂电流电极区域中的每一个的一部分被驱动以在第一和第二掺杂电流电极区域的沟道区域中的绝缘层和控制电极之下半导体器件。第一和第二掺杂电流电极区域除了在控制电极和绝缘层之下除去分别形成第一和第二沟槽的半导体衬底外。在第一和第二沟槽内形成有相对于半导体衬底具有不同晶格常数的原位掺杂材料，用作半导体器件的第一和第二电流电极。

19. 发明申请

US20070238250A1 Semiconductor fabrication process using etch stop layer to optimize formation of source/drain stressor 失效
标题翻译：使用蚀刻停止层的半导体制造工艺来优化源极/漏极应力源的形成
公开(公告)号：US20070238250A1
公开(公告)日：2007-10-11
申请号：US11393340
申请日：2006-03-30
申请人： Da Zhang , Ted White , Bich-Yen Nguyen
发明人： Da Zhang , Ted White , Bich-Yen Nguyen
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L21/76254 , H01L21/76283 , H01L29/66772 , H01L29/78684
摘要： A semiconductor fabrication process includes forming an etch stop layer (ESL) overlying a buried oxide (BOX) layer and an active semiconductor layer overlying the ESL. A gate electrode is formed overlying the active semiconductor layer. Source/drain regions of the active semiconductor layer are etched to expose the ESL. Source/drain stressors are formed on the ESL where the source/drain stressors strain the transistor channel. Forming the ESL may include epitaxially growing a silicon germanium ESL having a thickness of approximately 30 nm or less. Preferably a ratio of the active semiconductor layer etch rate to the ESL etch rate exceeds 10:1. A wet etch using a solution of NH4OH:H2O heated to a temperature of approximately 75° C. may be used to etch the source/drain regions. The ESL may be silicon germanium having a first percentage of germanium. The source/drain stressors may be silicon germanium having a second percentage of germanium for P-type transistors, and they may be silicon carbon for N-type transistors.
摘要翻译：半导体制造工艺包括形成覆盖掩埋氧化物（BOX）层和覆盖ESL的有源半导体层的蚀刻停止层（ESL）。形成覆盖有源半导体层的栅电极。蚀刻有源半导体层的源极/漏极区域以露出ESL。源极/漏极应力源在ESL上形成，其源极/漏极应力应变应变晶体管沟道。形成ESL可以包括外延生长厚度为约30nm或更小的硅锗ESL。优选地，有源半导体层蚀刻速率与ESL蚀刻速率的比率超过10:1。使用加热到约75℃温度的NH 4 OH：H 2 O 2的溶液进行湿蚀刻可以用于蚀刻源/漏区。 ESL可以是具有第一百分比的锗的硅锗。源极/漏极应力源可以是对于P型晶体管具有第二百分比的锗的硅锗，并且它们可以是N型晶体管的硅碳。

20. 发明申请

US20070238233A1 Method of making a multiple crystal orientation semiconductor device 有权
标题翻译：制造多晶体取向半导体器件的方法
公开(公告)号：US20070238233A1
公开(公告)日：2007-10-11
申请号：US11393563
申请日：2006-03-30
申请人： Mariam Sadaka , Bich-Yen Nguyen , Ted White
发明人： Mariam Sadaka , Bich-Yen Nguyen , Ted White
IPC分类号： H01L21/337
CPC分类号： H01L21/84 , H01L21/823412 , H01L21/823481 , H01L21/823807 , H01L21/823878 , H01L27/1203 , H01L27/1207
摘要： A method of having transistors formed in enhanced performance crystal orientations begins with a wafer having a semiconductor substrate (12,52) of a first surface orientation, a thin etch stop layer (14,54) on the semiconductor substrate, a buried oxide layer (16,56) on the thin etch stop layer, and a semiconductor layer (18,58) of a second surface orientation on the buried oxide layer. An etch penetrates to the thin etch stop layer. Another etch, which is chosen to minimize the damage to the underlying semiconductor substrate, exposes a portion of the semiconductor substrate. An epitaxial semiconductor (28,66) is then grown from the exposed portion of the semiconductor substrate to form a semiconductor region having the first surface orientation and having few, if any, defects. The epitaxially grown semiconductor region is then used for enhancing one type of transistor while the semiconductor layer of the second surface orientation is used for enhancing a different type of transistor.
摘要翻译：以增强的性能晶体取向形成的晶体管的方法从具有第一表面取向的半导体衬底（12,52），半导体衬底上的薄蚀刻停止层（14,54），掩埋氧化物层（ 16,56）和在所述掩埋氧化物层上的第二表面取向的半导体层（18,58）。蚀刻渗透到薄的蚀刻停止层。被选择以最小化对下面的半导体衬底的损害的另一蚀刻暴露了半导体衬底的一部分。然后从半导体衬底的暴露部分生长外延半导体（28,66）以形成具有第一表面取向并且具有很少（如果有的话）缺陷的半导体区域。然后外延生长的半导体区域用于增强一种类型的晶体管，而第二表面取向的半导体层用于增强不同类型的晶体管。

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