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11. 发明授权

US6057064A Double-alternating phase-shifting mask 失效
标题翻译：双交替相移掩模
公开(公告)号：US6057064A
公开(公告)日：2000-05-02
申请号：US083209
申请日：1998-05-21
申请人： Benjamin Szu-Min Lin
发明人： Benjamin Szu-Min Lin
IPC分类号： G03F1/00 , G03F1/26 , G03F1/30 , G03F1/32 , G03F9/00
CPC分类号： G03F1/32 , G03F1/26 , G03F1/30 , G03F1/36
摘要： A double-alternating phase-shifting mask (PSM) is provided for use in photolithography for pattern definition of contact holes in semiconductor fabrication, which can eliminate the side-lobe effect that would otherwise cause ghost lines in the resulted pattern definition. The double-alternating PSM comprises a quartz substrate and a masked area formed on said quartz substrate with the unmasked areas being defined as contact hole patterns. The masked area includes a first shifter layer formed over said quartz substrate and a second shifter layers formed over said quartz substrate at those positions each substantially in the geometric center of each group of neighboring contact hole patterns.
摘要翻译：提供双交变相移掩模（PSM）用于光刻中用于半导体制造中的接触孔的图案定义，这可以消除否则将导致所导致的图案定义中的重影线的旁瓣效应。双交替PSM包括石英衬底和形成在所述石英衬底上的掩模区域，未掩蔽区域被定义为接触孔图案。掩蔽区域包括形成在所述石英基板上的第一移位层和在基本上在每组相邻接触孔图案的几何中心处的那些位置处形成在所述石英基板上的第二移位层。

12. 发明授权

US6042996A Method of fabricating a dual damascene structure 失效
标题翻译：制造双镶嵌结构的方法
公开(公告)号：US6042996A
公开(公告)日：2000-03-28
申请号：US59071
申请日：1998-04-13
申请人： Benjamin Szu-Min Lin , Fang-Ching Chao
发明人： Benjamin Szu-Min Lin , Fang-Ching Chao
IPC分类号： G03F1/00 , H01L21/027 , H01L21/311 , H01L21/768 , G03F7/00
CPC分类号： H01L21/0274 , H01L21/31144 , H01L21/76807 , H01L2221/1021
摘要： A method of fabricating a dual damascene structure is provided comprising forming a photoresist layer on a dielectric layer. A mask including a region that light completely passes over, a region that light partially passes over and a dense region is used for exposure. A development step is carried out to remove the photoresist layer under the region that light completely passes over, to partially remove the photoresist layer under the region that light partially passes over and to leave the photoresist layer under the dense region. The photoresist layer remaining from the forgoing step and the dielectric layer are partially removed to form a via and a trench in the dielectric layer. The via and the trench are filled with metal to form a dual damascene structure.
摘要翻译：提供一种制造双镶嵌结构的方法，包括在电介质层上形成光致抗蚀剂层。包括光完全通过的区域，光部分通过的区域和致密区域的掩模用于曝光。进行显影步骤以在光完全通过的区域下去除光致抗蚀剂层，以在光部分通过的区域部分去除光致抗蚀剂层，并将光致抗蚀剂层留在致密区域下方。从前述步骤残留的光致抗蚀剂层和电介质层被部分去除以在电介质层中形成通孔和沟槽。通孔和沟槽用金属填充以形成双镶嵌结构。

13. 发明授权

US5989997A Method for forming dual damascene structure 失效
标题翻译：形成双镶嵌结构的方法
公开(公告)号：US5989997A
公开(公告)日：1999-11-23
申请号：US61659
申请日：1998-04-17
申请人： Benjamin Szu-Min Lin , Jason Jenq
发明人： Benjamin Szu-Min Lin , Jason Jenq
IPC分类号： H01L21/768 , H01L21/314
CPC分类号： H01L21/76808 , Y10S438/948
摘要： A method for forming dual damascene metallic structure that utilizes the formation of a protective photoresist layer at the bottom of a vertical window to prevent damages to a device region in the substrate when subsequent etching operation is carried out to form a horizontal trench pattern. The protective photoresist layer at the bottom of the vertical window is formed by irradiating the photoresist layer with a dose of radiation having energy level insufficient to chemically dissociate the photoactive molecules of the photoresist layer near the bottom of the vertical window.
摘要翻译：一种用于形成双镶嵌金属结构的方法，其利用在垂直窗口的底部形成保护光致抗蚀剂层，以防止当进行后续蚀刻操作以形成水平沟槽图案时对基板中的器件区域的损坏。垂直窗口底部的保护光致抗蚀剂层是通过用能量水平不足以化学解离靠近垂直窗口底部的光致抗蚀剂层的光活性分子的辐射照射光致抗蚀剂层而形成的。

14. 发明授权

US5904533A Metal salicide-CMP-metal salicide semiconductor process 失效
标题翻译：金属硅化物CMP-金属硅化物半导体工艺
公开(公告)号：US5904533A
公开(公告)日：1999-05-18
申请号：US805419
申请日：1997-02-25
申请人： Benjamin Szu-Min Lin
发明人： Benjamin Szu-Min Lin
IPC分类号： H01L21/28 , H01L21/3105 , H01L21/321 , H01L21/336
CPC分类号： H01L21/31053 , H01L21/28052
摘要： A metal salicide-CMP-metal salicide semiconductor process, suitable for a semiconductor substrate on which gates, sources (drains), spacers, and field oxides are formed. A first metal layer is formed on gates, sources (drains), spacers, and field oxides. A first high-temperature process is executed to form a first metal salicide layer on gates and sources (drains). A first wet etching is then performed. A first dielectric layer is formed over the semiconductor substrate wherein the horizontal line of the first dielectric layer is above the first metal salicide layer located on gates. A first chemical mechanical polishing (CMP) is then executed until the first metal salicide layer on gates is reached. A second metal layer is formed on the first dielectric layer and on the first metal salicide layer that is located on gates. A second high-temperature process is executed in order to form a thicker second metal salicide layer on the gates. A second wet etching is then performed. A second dielectric layer is formed over the semiconductor substrate. A second chemical mechanical polishing (CMP) is then executed. Finally, shallow contact windows and deep contact windows on gates and sources (drains) respectively are formed.
摘要翻译：金属硅化物CMP-金属硅化物半导体工艺，适用于其上形成栅极，源极（漏极），间隔物和场氧化物的半导体衬底。在栅极，源极（漏极），间隔物和场氧化物上形成第一金属层。执行第一高温处理以在门和源（排水管）上形成第一金属硅化物层。然后执行第一湿法蚀刻。第一电介质层形成在半导体衬底上，其中第一介电层的水平线位于位于栅极上的第一金属硅化物层的上方。然后执行第一化学机械抛光（CMP），直到达到门上的第一金属自对准硅化物层。第二金属层形成在位于栅极上的第一介电层和第一金属硅化物层上。执行第二高温处理以在门上形成较厚的第二金属硅化物层。然后进行第二次湿蚀刻。在半导体衬底上方形成第二电介质层。然后执行第二化学机械抛光（CMP）。最后，形成了分别在门和源（排水管）上的浅接触窗和深接触窗。

15. 发明授权

US5888865A Method for manufacturing dram capacitor 失效
标题翻译：制造电容器的方法
公开(公告)号：US5888865A
公开(公告)日：1999-03-30
申请号：US55686
申请日：1998-04-06
申请人： Benjamin Szu-Min Lin
发明人： Benjamin Szu-Min Lin
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817
摘要： A method for manufacturing a DRAM capacitor whose lower electrode has a greater surface area, and is thereby able to increase the capacitance of the capacitor. The method comprises the steps of providing a substrate with a target conductive region and then depositing a first dielectric layer, an etching stop layer and a second dielectric layer sequentially over the target conductive region and the substrate. Next, a deep opening leading to the target conductive region is etched through the various layers, and a first conductive material is deposited to fill the deep opening completely. Thereafter, the second dielectric layer is patterned and etched to form a shallow opening exposing a portion of the first conductive layer and the etching stop layer. Then, a second conductive material is deposited into the exposed first conductive layer and etching stop layer. Finally, the second dielectric layer is removed, and then another dielectric layer and a third conductive layer are sequentially formed over the second conductive layer and the first conductive layer to complete the fabrication of the capacitor. In addition to increasing the surface area of the lower electrode, the capacitor of this invention has a small overall height measuring from the conductive layer to the substrate.
摘要翻译：一种用于制造DRAM电容器的方法，其下电极具有较大的表面积，从而能够增加电容器的电容。该方法包括以下步骤：提供具有目标导电区域的衬底，然后在目标导电区域和衬底上依次沉积第一介电层，蚀刻停止层和第二介电层。接下来，通过各层蚀刻通向目标导电区域的深开口，并且沉积第一导电材料以完全填充深开口。此后，对第二电介质层进行图案化和蚀刻以形成露出第一导电层和蚀刻停止层的一部分的浅开口。然后，将第二导电材料沉积到暴露的第一导电层和蚀刻停止层中。最后，去除第二电介质层，然后在第二导电层和第一导电层上依次形成另一电介质层和第三导电层，以完成电容器的制造。除了增加下电极的表面积之外，本发明的电容器具有从导电层到衬底测量的小的总体高度。

16. 发明申请

US20100321656A1 TRANSMISSION MASK WITH DIFFERENTIAL ATTENUATION TO IMPROVE ISO-DENSE PROXIMITY 有权
标题翻译：具有差异衰减的传输面板，以提高ISO感光度接近
公开(公告)号：US20100321656A1
公开(公告)日：2010-12-23
申请号：US12868257
申请日：2010-08-25
申请人： Hang Yip Liu , Sebastian Schmidt , Benjamin Szu-Min Lin
发明人： Hang Yip Liu , Sebastian Schmidt , Benjamin Szu-Min Lin
IPC分类号： G03B27/42 , G03F1/00
CPC分类号： G03F1/36 , G03F1/50 , G03F7/70283
摘要： A system and method to compensate for the proximity effects in the imaging of patterns in a photolithography process. A light exposure of a photoresist layer is effectuated in predetermined patterns through an exposure mask having light-transmissive openings in correspondence to the predetermined patterns. The exposure mask has areas densely populated with the light-transmissive openings and areas sparsely populated with the light-transmissive openings. Light is attenuated through the densely populated light-transmissive openings by a different amount than through the sparsely populated light-transmissive openings.
摘要翻译：一种用于补偿光刻工艺中图案成像中的邻近效应的系统和方法。通过具有对应于预定图案的透光开口的曝光掩模，以预定图案实现光致抗蚀剂层的曝光。曝光掩模具有由透光开口和由透光开口稀疏地填充的区域密集地区域。光通过密集居住的透光开口被衰减不同于通过疏散人口的透光开口的量。

17. 发明申请

US20080055597A1 METHOD FOR CHARACTERIZING LINE WIDTH ROUGHNESS (LWR) OF PRINTED FEATURES 审中-公开
标题翻译：用于表征印刷特征的线宽度粗糙度（LWR）的方法
公开(公告)号：US20080055597A1
公开(公告)日：2008-03-06
申请号：US11467930
申请日：2006-08-29
申请人： Jie-Wei Sun , Wen-Kai Hung , Benjamin Szu-Min Lin
发明人： Jie-Wei Sun , Wen-Kai Hung , Benjamin Szu-Min Lin
IPC分类号： G01J4/00 , G01B11/14
CPC分类号： G01B11/24 , G01N21/211 , G01N21/956 , G01N2021/213
摘要： A method for characterizing line width roughness of printed features is provided. A wafer having thereon a plurality of gratings formed within a test key region is prepared. The wafer is transferred to a spectroscopic ellipsometry tool having a light source, a detector and a computer. A polarized light beam emanated from the light source is directed onto the gratings. Spectrum data of reflected light is measured and recorded. The spectrum data is compared to a library linked to the computer in real time. The library contains a plurality of contact-hole model based spectra created by incorporating parameter values that describes the line width roughness. The spectrum data is matched with the contact-hole model based spectra, thereby determining the parameter values.
摘要翻译：提供了一种表征印刷特征线宽粗糙度的方法。制备其上具有形成在测试键区域内的多个光栅的晶片。将晶片转移到具有光源，检测器和计算机的分光椭圆仪。从光源发出的偏振光束被引导到光栅上。测量和记录反射光的光谱数据。将频谱数据与实时连接到计算机的库进行比较。该库包含通过引入描述线宽粗糙度的参数值而创建的多个基于接触孔模型的光谱。光谱数据与基于接触孔模型的光谱匹配，从而确定参数值。

18. 发明授权

US06866967B2 Structure of phase shifting mask 有权
标题翻译：相移掩模的结构
公开(公告)号：US06866967B2
公开(公告)日：2005-03-15
申请号：US10190197
申请日：2002-07-03
申请人： Benjamin Szu-Min Lin
发明人： Benjamin Szu-Min Lin
IPC分类号： G03F1/00 , G03F1/32 , G03F1/36 , G03F9/00
CPC分类号： G03F1/32
摘要： A phase shifting mask is disclosed in this present invention. The above-mentioned phase shifting mask comprises a quartz layer and a plurality of transmission adjustor layer onto the quartz layer. By employing the above-mentioned phase shifting mask, the material of the transmission adjustors has not to be changed with the light source. Furthermore, the contrast of the phase shifting mask of this invention is better than the contrast of the binary mask and the half-tone mask in the prior art. Therefore, this invention provides a more efficient mask, and the phase shifting mask according to this present invention can improve the resolution in photolithography.
摘要翻译：在本发明中公开了一种相移掩模。上述相移掩模包括石英层和在石英层上的多个透射调节层。通过采用上述相移掩模，传输调节器的材料不会随着光源而改变。此外，本发明的相移掩模的对比度优于现有技术中二进制掩模和半色调掩模的对比度。因此，本发明提供了更有效的掩模，根据本发明的相移掩模可以提高光刻中的分辨率。

19. 发明授权

US06296974B1 Method of forming a multi-layer photo mask 失效
标题翻译：形成多层光罩的方法
公开(公告)号：US06296974B1
公开(公告)日：2001-10-02
申请号：US09391321
申请日：1999-09-08
申请人： Benjamin Szu-Min Lin
发明人： Benjamin Szu-Min Lin
IPC分类号： G03P900
CPC分类号： G03F7/0035 , G03F1/58
摘要： This invention provides a method of forming a multi-layer photo mask on a photo mask substrate. A first transparent layer comprising at least one vertical side wall is formed on at least one predetermined area of the photo mask substrate. A first opaque spacer is formed around the vertical side wall of the first transparent layer, and the top side of the first spacer is approximately leveled off with the upper surface of the first transparent layer. An external transparent layer is formed on the photo mask substrate and outside the predetermined area, and the upper surface of the external transparent layer is leveled off with that of the first transparent layer. So the first transparent layer and the external transparent layer form a first photo mask layer. A second transparent layer comprising at least one vertical side wall is formed on at least one predetermined area of the first photo mask layer. A second opaque spacer is formed around the vertical side wall of the second transparent layer, and the top side of the second spacer is approximately leveled off with the upper surface of the second transparent layer.
摘要翻译：本发明提供了在光掩模基板上形成多层光掩膜的方法。包括至少一个垂直侧壁的第一透明层形成在光掩模基板的至少一个预定区域上。在第一透明层的垂直侧壁周围形成第一不透明间隔物，并且第一间隔物的顶侧与第一透明层的上表面几乎平齐。在光掩模基板上形成外部透明层，在规定区域外形成外部透明层，外部透明层的上表面与第一透明层的上表面平齐。因此，第一透明层和外部透明层形成第一光掩模层。包括至少一个垂直侧壁的第二透明层形成在第一光掩模层的至少一个预定区域上。在第二透明层的垂直侧壁周围形成第二不透明间隔物，并且第二间隔物的顶侧与第二透明层的上表面大致平齐。

20. 发明授权

US06187669B1 Method of forming a node contact of a DRAM's memory cell 失效
标题翻译：形成DRAM存储单元的节点接触的方法
公开(公告)号：US06187669B1
公开(公告)日：2001-02-13
申请号：US09391326
申请日：1999-09-08
申请人： Jung-Chao Chiou , Benjamin Szu-Min Lin
发明人： Jung-Chao Chiou , Benjamin Szu-Min Lin
IPC分类号： H01L214763
CPC分类号： H01L27/10855 , H01L21/76897 , H01L27/0207 , H01L27/10885
摘要： This invention provides a method of forming a node contact with self-alignment on a semiconductor wafer. The wafer comprises a substrate, a dielectric layer, and a first and a second bit lines. A first side wall of the first bit line is adjacent to a second side wall of the second bit line and comprises a first region and two second regions adjacent to the first region. The distance between the first region and the second side wall is greater than a predetermined value and the distance between the two second regions and the second side wall is less than the predetermined value. A second insulating layer is formed on the dielectric layer and two bit lines to form a groove over the gap between the first region and the second side wall. A first anisotropic etching is performed to extend the bottom of the groove down to the dielectric layer. The remaining second insulating layer around the groove forms a spacer, and the remaining second insulating layer in the gaps between the two second regions and the second side wall still completely covers the surface of the two gaps. A second anisotropic etching process is performed to remove the dielectric layer at the bottom of the groove in a vertical direction down to the substrate so as to form the node contact.
摘要翻译：本发明提供一种在半导体晶片上形成具有自对准的节点接触的方法。晶片包括衬底，电介质层以及第一和第二位线。第一位线的第一侧壁与第二位线的第二侧壁相邻并且包括与第一区域相邻的第一区域和两个第二区域。第一区域和第二侧壁之间的距离大于预定值，并且两个第二区域和第二侧壁之间的距离小于预定值。第二绝缘层形成在电介质层和两个位线之间以在第一区域和第二侧壁之间的间隙上形成沟槽。执行第一各向异性蚀刻以将凹槽的底部向下延伸到电介质层。围绕凹槽的剩余的第二绝缘层形成间隔物，并且在两个第二区域和第二侧壁之间的间隙中的剩余的第二绝缘层仍完全覆盖两个间隙的表面。进行第二种各向异性蚀刻工艺以在垂直方向上去除凹槽底部的电介质层，以便形成节点接触。

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