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11. 发明申请

US20090268373A1 METHOD OF MANUFACTURING CAPACITOR FOR INCORPORATION IN WIRING BOARD, CAPACITOR FOR INCORPORATION IN WIRING BOARD, AND WIRING BOARD 有权
标题翻译：制造电容器的方法，用于在接线板中加入电容器，用于配线的电容器和接线板
公开(公告)号：US20090268373A1
公开(公告)日：2009-10-29
申请号：US12497198
申请日：2009-07-02
申请人： Motohiko SATO , Kazuhiro HAYASHI , Akifumi TOSA , Kenji MURAKAMI , Tomohide YAMADA , Motonobu KURAHASHI
发明人： Motohiko SATO , Kazuhiro HAYASHI , Akifumi TOSA , Kenji MURAKAMI , Tomohide YAMADA , Motonobu KURAHASHI
IPC分类号： H01G4/228 , H01G7/00
CPC分类号： H01G4/232 , H01G4/012 , H01G4/30 , H01L2924/3511 , H05K1/0231 , H05K1/112 , H05K1/185 , H05K3/4602 , H05K2201/10674 , H05K2201/10712 , Y10T29/435
摘要： A capacitor comprising: a plurality of laminated dielectric layers; a plurality of inner electrode layers each disposed between mutually adjacent ones of the dielectric layers; and dummy electrode layers respectively disposed between the dielectric layers, disposed on sides closer to outer peripheral sides of the dielectric layers than to the inner electrode layers and disposed apart from the inner electrode layers.
摘要翻译：一种电容器，包括：多个叠层电介质层; 多个内部电极层，各自设置在相互相邻的电介质层之间; 以及分别设置在电介质层之间的虚设电极层，其设置在比内部电极层更靠近电介质层的外周侧的一侧并且与内部电极层分离。

12. 发明申请

US20090255719A1 WIRING BOARD AND CERAMIC CHIP TO BE EMBEDDED 有权
标题翻译：接线板和陶瓷芯片嵌入
公开(公告)号：US20090255719A1
公开(公告)日：2009-10-15
申请号：US12475648
申请日：2009-06-01
申请人： Hiroshi Yamamoto , Toshitake Seki , Shinji Yuri , Masaki Muramatsu , Motohiko Sato , Akifumi Tosa
发明人： Hiroshi Yamamoto , Toshitake Seki , Shinji Yuri , Masaki Muramatsu , Motohiko Sato , Akifumi Tosa
IPC分类号： H05K1/16 , H01G4/12
CPC分类号： H01L21/6835 , H01G4/236 , H01G4/30 , H01L21/568 , H01L23/49822 , H01L2221/68345 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/16235 , H01L2224/16237 , H01L2924/00014 , H01L2924/01019 , H01L2924/01078 , H01L2924/09701 , H01L2924/15311 , H01L2924/19041 , H01L2924/30105 , H05K1/0231 , H05K1/112 , H05K1/185 , H05K3/4602 , H05K2201/096 , H05K2201/10674 , H05K2201/10712 , H01L2224/05599
摘要： A wiring board includes a substrate core and a ceramic chip to be embedded therein. The substrate core has a housing opening portion opening at a core main surface. The ceramic chip is accommodated in the housing opening portion so that the core main surface and a chip first main surface face the same way. The ceramic chip includes a plurality of second terminal electrodes comprised of a metallized layer and formed on the chip second main surface so as to protrude therefrom. A projecting portion, disposed on the second main surface side so as to surround a plurality of the second terminal electrodes, is formed on the chip second main surface so as to protrude therefrom.
摘要翻译：布线基板包括嵌入其中的基板芯和陶瓷芯片。基板芯具有在芯主表面处开口的壳体开口部。陶瓷芯片容纳在壳体开口部分中，使得芯主表面和芯片第一主表面相同。陶瓷芯片包括多个由金属化层构成的第二端子电极，并且形成在芯片第二主表面上以从其突出。在芯片第二主表面上形成有从第二主表面侧配置成包围多个第二端子电极的突出部，从而突出。

13. 发明授权

US07557440B2 Wiring board and ceramic chip to be embedded 有权
标题翻译：接线板和陶瓷芯片要嵌入
公开(公告)号：US07557440B2
公开(公告)日：2009-07-07
申请号：US11508968
申请日：2006-08-24
申请人： Hiroshi Yamamoto , Toshitake Seki , Shinji Yuri , Masaki Muramatsu , Motohiko Sato , Akifumi Tosa
发明人： Hiroshi Yamamoto , Toshitake Seki , Shinji Yuri , Masaki Muramatsu , Motohiko Sato , Akifumi Tosa
IPC分类号： H01L23/053
CPC分类号： H01L21/6835 , H01G4/236 , H01G4/30 , H01L21/568 , H01L23/49822 , H01L2221/68345 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/16235 , H01L2224/16237 , H01L2924/00014 , H01L2924/01019 , H01L2924/01078 , H01L2924/09701 , H01L2924/15311 , H01L2924/19041 , H01L2924/30105 , H05K1/0231 , H05K1/112 , H05K1/185 , H05K3/4602 , H05K2201/096 , H05K2201/10674 , H05K2201/10712 , H01L2224/05599
摘要： A wiring board includes a substrate core and a ceramic chip to be embedded therein. The substrate core has a housing opening portion opening at a core main surface. The ceramic chip is accommodated in the housing opening portion so that the core main surface and a chip first main surface face the same way. The ceramic chip includes a plurality of second terminal electrodes comprised of a metallized layer and formed on the chip second main surface so as to protrude therefrom. A projecting portion, disposed on the second main surface side so as to surround a plurality of the second terminal electrodes, is formed on the chip second main surface so as to protrude therefrom.
摘要翻译：布线基板包括嵌入其中的基板芯和陶瓷芯片。基板芯具有在芯主表面处开口的壳体开口部。陶瓷芯片容纳在壳体开口部分中，使得芯主表面和芯片第一主表面相同。陶瓷芯片包括多个由金属化层构成的第二端子电极，并且形成在芯片第二主表面上以从其突出。在芯片第二主表面上形成有从第二主表面侧配置成包围多个第二端子电极的突出部，从而突出。

14. 发明授权

US07233480B2 Capacitor and method for manufacturing the same 有权
标题翻译：电容器及其制造方法
公开(公告)号：US07233480B2
公开(公告)日：2007-06-19
申请号：US11475891
申请日：2006-06-28
申请人： Kazuhiro Hayashi , Akifumi Tosa , Motohiko Sato , Jun Otsuka , Manabu Sato
发明人： Kazuhiro Hayashi , Akifumi Tosa , Motohiko Sato , Jun Otsuka , Manabu Sato
IPC分类号： H01G4/228
CPC分类号： H01G4/30 , H01G4/12
摘要： A laminated ceramic capacitor (10) divided into a first laminate (11), a second laminate (12), a third laminate (13), and a fourth laminate (14). The first laminate (11) includes a ceramic layer (15) serving as a dielectric layer. The ceramic layer (15) is thicker than a ceramic layer (17) sandwiched between internal electrodes (16a) in the second laminate (12) or the fourth laminate (14), and thinner than 20 times the thickness of the ceramic layer (17). The third laminate (13) includes dielectric layers, which serve as the ceramic layers (17), and has a thickness of 5% of the total thickness of the second laminate (12) and the fourth laminate (14). Accordingly, the third laminate (13) achieves the function of absorbing an electrode-induced thickness differential. Also, by means of regulating the thickness of the first laminate (11), portions of via electrodes (18) that extend without being electrically connected to the internal electrodes (16b) can be shortened.
摘要翻译：分为第一层压体（11），第二层压板（12），第三层压板（13）和第四层压板（14）的层压陶瓷电容器（10）。第一层压体（11）包括用作电介质层的陶瓷层（15）。陶瓷层（15）比夹在第二层叠体（12）或第四层叠体（14）的内部电极（16a）之间的陶瓷层（17）厚，比陶瓷层（15）的厚度薄 17）。第三层压体（13）包括作为陶瓷层（17）的电介质层，其厚度为第二层叠体（12）和第四层叠体（14）的总厚度的5％。因此，第三层压体（13）实现吸收电极引起的厚度差的功能。此外，通过调整第一层压体（11）的厚度，能够缩短在不与内部电极（16b）电连接的情况下延伸的通孔电极（18）的部分。

15. 发明申请

US20070047175A1 Method of manufacturing capacitor for incorporation in wiring board, capacitor for incorporation in wiring board, and wiring board 有权
标题翻译：制造用于配线基板的电容器的制造方法，配线基板的电容器以及配线基板
公开(公告)号：US20070047175A1
公开(公告)日：2007-03-01
申请号：US11512247
申请日：2006-08-30
申请人： Motohiko Sato , Kazuhiro Hayashi , Akifumi Tosa , Kenji Murakami , Tomohide Yamada , Motonobu Kurahashi
发明人： Motohiko Sato , Kazuhiro Hayashi , Akifumi Tosa , Kenji Murakami , Tomohide Yamada , Motonobu Kurahashi
IPC分类号： H01G4/005
CPC分类号： H01G4/232 , H01G4/012 , H01G4/30 , H01L2924/3511 , H05K1/0231 , H05K1/112 , H05K1/185 , H05K3/4602 , H05K2201/10674 , H05K2201/10712 , Y10T29/435
摘要： A capacitor comprising: a plurality of laminated dielectric layers; a plurality of inner electrode layers each disposed between mutually adjacent ones of the dielectric layers; and dummy electrode layers respectively disposed between the dielectric layers, disposed on sides closer to outer peripheral sides of the dielectric layers than to the inner electrode layers and disposed apart from the inner electrode layers.
摘要翻译：一种电容器，包括：多个叠层电介质层; 多个内部电极层，各自设置在相互相邻的电介质层之间; 以及分别设置在电介质层之间的虚设电极层，其设置在比内部电极层更靠近电介质层的外周侧的一侧并且与内部电极层分离。

16. 发明授权

US07105070B2 Method for producing ceramic substrate, and ceramic substrate 有权
标题翻译：陶瓷基板和陶瓷基板的制造方法
公开(公告)号：US07105070B2
公开(公告)日：2006-09-12
申请号：US10935164
申请日：2004-09-08
申请人： Akifumi Tosa , Jun Otsuka , Manabu Sato , Hisahito Kashima
发明人： Akifumi Tosa , Jun Otsuka , Manabu Sato , Hisahito Kashima
IPC分类号： B32B37/06 , B32B38/10 , C03B29/00 , H05K3/26 , H05K3/46
CPC分类号： B32B18/00 , C03C14/004 , C03C2214/20 , C04B2235/6567 , C04B2235/9615 , C04B2237/341 , C04B2237/343 , C04B2237/346 , C04B2237/56 , C04B2237/562 , C04B2237/565 , C04B2237/568 , C04B2237/66 , C04B2237/68 , C04B2237/702 , C04B2237/704 , H01G4/30 , H01L21/481 , H01L21/4857 , H05K1/0306 , H05K3/246 , H05K3/4611 , H05K3/4629 , H05K2201/0347 , H05K2201/09881 , H05K2203/308
摘要： A method for producing a ceramic substrate which employs a cofiring process using restraint sheets in which a second ceramic green sheet 7 is laminated on a green ceramic substrate 30 so as to cover surface conductors 32 of the green ceramic substrate 30, the second ceramic green sheet 7 subsequently being integrated with the green ceramic substrate 30. Restraint sheets 9, which are not sintered at a sintering temperature at which the green ceramic substrate 30 is sintered, are laminated on corresponding opposite sides of the green ceramic substrate 30 so as to restrain the green ceramic substrate 30 together with the second ceramic green sheet 7. The second ceramic green sheet 7 and the green ceramic substrate 30 are fired at a temperature at which the second ceramic green sheet 7 and the green ceramic substrate 30 are integrally sintered, whereas the restraint sheets 9 are not sintered, to thereby yield a ceramic substrate 40. The restraint sheets 9 and a ceramic covering layer 7a which covers the surface conductors 32 are removed, to thereby expose the surface conductor layer 32. A plating layer 31 is formed on the surface conductor layer 32.
摘要翻译：一种陶瓷基板的制造方法，其使用使用在生陶瓷基板30上层叠有第二陶瓷生片7以将陶瓷基板30的表面导体32覆盖的第二陶瓷生片的约束片， 7随后与绿色陶瓷基板30集成。在烧结生坯陶瓷基板30的烧结温度下没有烧结的约束片9层叠在生陶瓷基板30的对应的相对侧，以便与第二陶瓷生片一起抑制生陶瓷基板30 7。第二陶瓷生片7和生陶瓷基片30在第二陶瓷生片7和生陶瓷基片30一体烧结的温度下烧制，而约束片9不烧结，从而产生陶瓷基片 40。去除约束片9和覆盖表面导体32的陶瓷覆盖层7a，从而露出表面导体层32。在表面导体层32上形成镀层31。

17. 发明授权

US6117806A Dielectric material, a method for producing the same and a dielectric resonator device comprising same 失效
标题翻译：电介质材料，其制造方法和包括该介电材料的介质谐振器装置
公开(公告)号：US6117806A
公开(公告)日：2000-09-12
申请号：US957627
申请日：1997-10-24
申请人： Hitoshi Yokoi , Akifumi Tosa , Kazushige Ohbayashi
发明人： Hitoshi Yokoi , Akifumi Tosa , Kazushige Ohbayashi
IPC分类号： C04B35/495 , H01P7/10
CPC分类号： C04B35/495 , H01P7/10
摘要： Dielectric materials are disclosed that are based on BaO--ZnO--Ta.sub.2 O.sub.5 represented by the formula Ba(Zn.sub.1/3 Ta.sub.2/3)O.sub.3. Ba has been partly replaced by K and either Zn or Ta has been replaced by at least one element selected from Mg, Zr, Ga, Ni, Nb, Sn. The dielectric materials have a relatively high permittivity, a small absolute value of the temperature coefficient of resonance frequency, and a high unloaded quality factor. A method for producing the dielectric materials is also disclosed which includes mixing given amounts of starting materials, such as, for example, BaCO.sub.3, ZnO, Ta.sub.2 O.sub.5, K.sub.2 CO.sub.3, MgCO.sub.3, SnO.sub.2 or ZrO.sub.2, compacting the mixture to produce a compact, sintering the compact in an oxidizing atmosphere such as, for example, air, at 1,400 and 1,600.degree. C., more preferably at 1,550 to 1,600.degree. C. for 2 hours, and then heating the sintered compact at a temperature lower than the sintering temperature by from 50 to 250.degree. C., e.g., by 100.degree. C., for at least 12 hours, preferably for 24 hours. A dielectric resonator comprising the dielectric material of the present invention is also disclosed.
摘要翻译：公开了基于由式Ba（Zn + E，fra 1/3 + EE Ta + E，fra 2/3 + EE）O 3表示的BaO-ZnO-Ta 2 O 5的介电材料。 Ba部分被K替代，并且Zn或Ta已经被选自Mg，Zr，Ga，Ni，Nb，Sn中的至少一种元素代替。电介质材料具有相对高的介电常数，谐振频率的温度系数的绝对值小，以及高的卸载品质因数。还公开了一种用于制造电介质材料的方法，其包括混合给定量的起始材料，例如BaCO 3，ZnO，Ta 2 O 5，K 2 CO 3，MgCO 3，SnO 2或ZrO 2，将该混合物压实成压坯，在氧化气氛例如空气中，在1,400和1600℃，更优选在1,550至1600℃下进行2小时，然后在低于烧结温度的温度下将烧结体加热50 至250℃，例如100℃，至少12小时，优选24小时。还公开了包括本发明的介电材料的介质谐振器。

18. 发明授权

US07778010B2 Method of manufacturing capacitor for incorporation in wiring board, capacitor for incorporation in wiring board, and wiring board 有权
标题翻译：制造用于配线基板的电容器的制造方法，配线基板的电容器以及配线基板
公开(公告)号：US07778010B2
公开(公告)日：2010-08-17
申请号：US12497198
申请日：2009-07-02
申请人： Motohiko Sato , Kazuhiro Hayashi , Akifumi Tosa , Kenji Murakami , Tomohide Yamada , Motonobu Kurahashi
发明人： Motohiko Sato , Kazuhiro Hayashi , Akifumi Tosa , Kenji Murakami , Tomohide Yamada , Motonobu Kurahashi
IPC分类号： H01G4/228
CPC分类号： H01G4/232 , H01G4/012 , H01G4/30 , H01L2924/3511 , H05K1/0231 , H05K1/112 , H05K1/185 , H05K3/4602 , H05K2201/10674 , H05K2201/10712 , Y10T29/435
摘要： A capacitor comprising: a plurality of laminated dielectric layers; a plurality of inner electrode layers each disposed between mutually adjacent ones of the dielectric layers; and dummy electrode layers respectively disposed between the dielectric layers, disposed on sides closer to outer peripheral sides of the dielectric layers than to the inner electrode layers and disposed apart from the inner electrode layers.
摘要翻译：一种电容器，包括：多个叠层电介质层; 多个内部电极层，各自设置在相互相邻的电介质层之间; 以及分别设置在电介质层之间的虚设电极层，其设置在比内部电极层更靠近电介质层的外周侧的一侧并且与内部电极层分离。

19. 发明授权

US07573697B2 Method of manufacturing capacitor for incorporation in wiring board, capacitor for incorporation in wiring board, and wiring board 有权
标题翻译：制造用于配线基板的电容器的制造方法，配线基板的电容器以及配线基板
公开(公告)号：US07573697B2
公开(公告)日：2009-08-11
申请号：US11512247
申请日：2006-08-30
申请人： Motohiko Sato , Kazuhiro Hayashi , Akifumi Tosa , Kenji Murakami , Tomohide Yamada , Motonobu Kurahashi
发明人： Motohiko Sato , Kazuhiro Hayashi , Akifumi Tosa , Kenji Murakami , Tomohide Yamada , Motonobu Kurahashi
IPC分类号： H01G4/228
CPC分类号： H01G4/232 , H01G4/012 , H01G4/30 , H01L2924/3511 , H05K1/0231 , H05K1/112 , H05K1/185 , H05K3/4602 , H05K2201/10674 , H05K2201/10712 , Y10T29/435
摘要： A capacitor comprising: a plurality of laminated dielectric layers; a plurality of inner electrode layers each disposed between mutually adjacent ones of the dielectric layers; and dummy electrode layers respectively disposed between the dielectric layers, disposed on sides closer to outer peripheral sides of the dielectric layers than to the inner electrode layers and disposed apart from the inner electrode layers.
摘要翻译：一种电容器，包括：多个叠层电介质层; 多个内部电极层，各自设置在相互相邻的电介质层之间; 以及分别设置在电介质层之间的虚设电极层，其设置在比内部电极层更靠近电介质层的外周侧的一侧并且与内部电极层分离。

20. 发明申请

US20070045814A1 Wiring board and ceramic chip to be embedded 有权
标题翻译：接线板和陶瓷芯片要嵌入
公开(公告)号：US20070045814A1
公开(公告)日：2007-03-01
申请号：US11508968
申请日：2006-08-24
申请人： Hiroshi Yamamoto , Toshitake Seki , Shinji Yuri , Masaki Muramatsu , Motohiko Sato , Akifumi Tosa
发明人： Hiroshi Yamamoto , Toshitake Seki , Shinji Yuri , Masaki Muramatsu , Motohiko Sato , Akifumi Tosa
IPC分类号： H01L23/04
CPC分类号： H01L21/6835 , H01G4/236 , H01G4/30 , H01L21/568 , H01L23/49822 , H01L2221/68345 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/16235 , H01L2224/16237 , H01L2924/00014 , H01L2924/01019 , H01L2924/01078 , H01L2924/09701 , H01L2924/15311 , H01L2924/19041 , H01L2924/30105 , H05K1/0231 , H05K1/112 , H05K1/185 , H05K3/4602 , H05K2201/096 , H05K2201/10674 , H05K2201/10712 , H01L2224/05599
摘要： A wiring board includes a substrate core and a ceramic chip to be embedded therein. The substrate core has a housing opening portion opening at a core main surface. The ceramic chip is accommodated in the housing opening portion so that the core main surface and a chip first main surface face the same way. The ceramic chip includes a plurality of second terminal electrodes comprised of a metallized layer and formed on the chip second main surface so as to protrude therefrom. A projecting portion, disposed on the second main surface side so as to surround a plurality of the second terminal electrodes, is formed on the chip second main surface so as to protrude therefrom.
摘要翻译：布线基板包括嵌入其中的基板芯和陶瓷芯片。基板芯具有在芯主表面处开口的壳体开口部。陶瓷芯片容纳在壳体开口部分中，使得芯主表面和芯片第一主表面相同。陶瓷芯片包括多个由金属化层构成的第二端子电极，并且形成在芯片第二主表面上以从其突出。在芯片第二主表面上形成有从第二主表面侧配置成包围多个第二端子电极的突出部，从而突出。

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