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11. 发明申请

WO2012030329A1 SYSTEMS, APPARATUSES AND METHODS FOR DYNAMIC VOLTAGE AND FREQUENCY CONTROL OF COMPONENTS USED IN A COMPUTER SYSTEM 审中-公开
标题翻译：用于计算机系统的组件的动态电压和频率控制的系统，装置和方法
公开(公告)号：WO2012030329A1
公开(公告)日：2012-03-08
申请号：PCT/US2010/047372
申请日：2010-08-31
申请人： INTEGRATED DEVICE TECHNOLOGY, INC. , HSIAO, Ivan , LEUNG, Eric , MATTHEWS, Frank , KUO, Ordin , BUI, Dinh , PHAM, Duy , LY, Wallace
发明人： HSIAO, Ivan , LEUNG, Eric , MATTHEWS, Frank , KUO, Ordin , BUI, Dinh , PHAM, Duy , LY, Wallace
IPC分类号： G06F1/26 , G06F1/04
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3253 , G06F1/3275 , G06F1/3296 , Y02D10/126 , Y02D10/14 , Y02D10/151 , Y02D10/172
摘要： Embodiments of the present disclosure include systems, apparatuses, and methods for dynamic frequency and voltage control of components used in a computer system. A system includes a processor voltage regulator and a system clock generator directly operably with each other. The processor voltage regulator provides a core voltage signal to a processor, and is configured to detect a present processor load state of the processor. The system clock generator is for providing a system clock signal to the processor. At least one of the processor voltage regulator or the system clock generator is further configured determine a desired frequency of the system clock signal responsive to the present processor load state, and determine a voltage level for the core voltage signal suitably paired with the desired frequency for proper operation of the processor at the desired frequency. Other systems, apparatuses, and methods are provided.
摘要翻译：本公开的实施例包括用于计算机系统中使用的组件的动态频率和电压控制的系统，装置和方法。系统包括处理器电压调节器和系统时钟发生器，它们彼此直接可操作。处理器电压调节器向处理器提供核心电压信号，并且被配置为检测处理器的当前处理器负载状态。系统时钟发生器用于向处理器提供系统时钟信号。处理器电压调节器或系统时钟发生器中的至少一个被进一步配置以响应于当前处理器负载状态确定系统时钟信号的期望频率，并且确定与期望频率适当配对的核心电压信号的电压电平以所需频率正确操作处理器。提供了其他系统，装置和方法。

12. 发明申请

WO2011159815A1 DYNAMIC EDID GENERATION 审中-公开
标题翻译：动态EDID生成
公开(公告)号：WO2011159815A1
公开(公告)日：2011-12-22
申请号：PCT/US2011/040551
申请日：2011-06-15
申请人： INTEGRATED DEVICE TECHNOLOGY, INC. , ZENG, Henry , QIAN, Jing , ZHANG, Xiaoqian , LIU, Xuexin
发明人： ZENG, Henry , QIAN, Jing , ZHANG, Xiaoqian , LIU, Xuexin
IPC分类号： G06F3/00
CPC分类号： G09G5/006 , G09G2370/042
摘要： A multi-monitor display driver that provides consolidated EDID data is provided. The display driver reads the EDID data from the one or more monitors coupled to the driver, determines a consolidated EDID data that is compatible with each of the monitors, and writes the EDID data to an EDID memory in the driver. A source interacting with the driver reads the consolidated EDID data to control interactions with the driver.
摘要翻译：提供了提供综合EDID数据的多显示器显示驱动程序。显示驱动器从耦合到驱动器的一个或多个监视器读取EDID数据，确定与每个监视器兼容的合并EDID数据，并将EDID数据写入驱动器中的EDID存储器。与驱动程序交互的源将读取合并的EDID数据，以控制与驱动程序的交互。

13. 发明申请

WO2011029037A1 METHOD AND APPARATUS FOR COMPRESSION OF CONFIGURATION BITSTREAM OF FIELD PROGRAMMABLE LOGIC 审中-公开
标题翻译：用于现场可编程逻辑的配置比特的压缩的方法和装置
公开(公告)号：WO2011029037A1
公开(公告)日：2011-03-10
申请号：PCT/US2010/047872
申请日：2010-09-03
申请人： INTEGRATED DEVICE TECHNOLOGY, INC. , GUNWANI, Manoj , VERMA, Hare K. , PRATER, Cordell
发明人： GUNWANI, Manoj , VERMA, Hare K. , PRATER, Cordell
IPC分类号： G06F7/38
CPC分类号： G11C29/40 , G11C2029/0401 , H03K19/17748 , H03K19/1776
摘要： A memory is disclosed that can be utilized with a field programmable gate array. In some embodiments, the memory can include a memory array comprising a plurality of memory banks, each memory bank including at least one memory block, each of the at least one memory block including an array of memory cells; an address decoder coupled to each of the at least one memory block, the address decoder including a comparator coupled to receive an input address and a block address and provide a compare bit that indicates when a portion of the input address matches the block address, and an OR gate coupled to receive the compare bit and a wildcard bit, the OR gate providing an enable to the memory block when either the compare bit or the wildcard bit is asserted; and a logic unit that receives a mode value and the input address.
摘要翻译：公开了可以与现场可编程门阵列一起使用的存储器。在一些实施例中，存储器可以包括包括多个存储体的存储器阵列，每个存储体包括至少一个存储器块，所述至少一个存储器块中的每一个包括存储器单元阵列; 耦合到所述至少一个存储器块中的每一个的地址解码器，所述地址解码器包括耦合以接收输入地址和块地址的比较器，并且提供指示输入地址的一部分何时与块地址匹配的比较位，以及或门，其耦合以接收所述比较位和通配符位，当所述比较位或所述通配符位被置位时，所述或门向所述存储器块提供使能; 以及接收模式值和输入地址的逻辑单元。

14. 发明申请

WO2011011449A1 BLOCK ARTIFACT REDUCER 审中-公开
标题翻译：块艺术减少
公开(公告)号：WO2011011449A1
公开(公告)日：2011-01-27
申请号：PCT/US2010/042650
申请日：2010-07-20
申请人： INTEGRATED DEVICE TECHNOLOGY, INC. , LEDINH, Phuc-Tue , LEDINH, Chon-Tam
发明人： LEDINH, Phuc-Tue , LEDINH, Chon-Tam
IPC分类号： H04N11/04
CPC分类号： H04N19/86 , H04N19/117 , H04N19/137 , H04N19/176 , H04N19/42 , H04N19/61 , H04N19/80
摘要： A block artifact reduction system is provided. An apparatus for reducing block artifact in an image sequence according to some embodiments of the present invention includes a motion detection unit that detects a motion signal from a first frame of an image signal and a second frame of the image signal; a block border offset and motion-based correction determination (BOMCS) unit that determines block border locations based on the second frame and a correction strength based on the second frame and the motion signal; and an intensity filter that filters the second frame based on the block border locations and the correction strength to output a corrected image signal.
摘要翻译：提供了一种块伪影减少系统。根据本发明的一些实施例的用于减少图像序列中的块伪影的装置包括：运动检测单元，其检测来自图像信号的第一帧和图像信号的第二帧的运动信号; 块边界偏移和基于运动的校正确定（BOMCS）单元，其基于第二帧确定块边界位置以及基于第二帧和运动信号的校正强度; 以及强度滤波器，其基于块边界位置和校正强度对第二帧进行滤波，以输出校正后的图像信号。

15. 发明申请

WO2010088464A2 THIN-FILM BULK ACOUSTIC RESONATORS HAVING PERFORATED BODIES THAT PROVIDE REDUCED SUSCEPTIBILITY TO PROCESS-INDUCED LATERAL DIMENSION VARIATIONS 审中-公开
标题翻译：具有减少对加工诱导的侧向尺寸变化的可靠性的执行体的薄膜膨胀聚合谐振器
公开(公告)号：WO2010088464A2
公开(公告)日：2010-08-05
申请号：PCT/US2010/022510
申请日：2010-01-29
申请人： INTEGRATED DEVICE TECHNOLOGY, INC. , WANG, Ye , BHUGRA, Harmeet
发明人： WANG, Ye , BHUGRA, Harmeet
IPC分类号： H03H9/17
CPC分类号： H03H9/172 , H03H9/2452 , H03H2009/0233 , H03H2009/241
摘要： Micro-electromechanical acoustic resonators include a resonator body suspended over a substrate. The resonator body may have a single perforation therein, which may extend substantially or completely therethrough. The resonator body may also be configured to have a center-of-mass within an interior of the perforation and/or a nodal line that overlaps the perforation. A perimeter and depth of the single perforation can be configured to reduce a susceptibility of the acoustic resonator to process-induced variations in resonant frequency relative to an otherwise equivalent resonator that omits the single perforation. In other embodiments, the resonator body may have multiple perforations therein that extend along a nodal line of the resonator.
摘要翻译：微机电声谐振器包括悬挂在衬底上的谐振器体。谐振器本体可以在其中具有单个穿孔，其可以基本上或完全地延伸穿过其中。谐振器主体还可以被配置为具有在穿孔内部和/或与穿孔重叠的节点线之间的质心。单个穿孔的周长和深度可以被配置为相对于省略单个穿孔的另外等效的谐振器来减小声谐振器对于处理引起的谐振频率变化的敏感性。在其他实施例中，谐振器本体可以具有沿着谐振器的节点线延伸的多个穿孔。

16. 发明申请

WO2010083168A1 MULTI-MONITOR DISPLAY 审中-公开
标题翻译：多显示器显示
公开(公告)号：WO2010083168A1
公开(公告)日：2010-07-22
申请号：PCT/US2010/020798
申请日：2010-01-12
申请人： INTEGRATED DEVICE TECHNOLOGY, INC. , ZENG, Henry , PARK, Ji
发明人： ZENG, Henry , PARK, Ji
IPC分类号： G09G5/00
CPC分类号： G06F3/1431 , G06F3/1446 , G09G5/006 , G09G2370/10
摘要： A multi-monitor display is disclosed. A multi-monitor display receives video data configured for a single N x M video display; splits the video data into a plurality of portions spanning the N x M display; and transmits the plurality of portions to a corresponding plurality of displays.
摘要翻译：公开了一种多显示器显示器。多显示器显示器接收为单个N×M视频显示配置的视频数据; 将视频数据分割成跨越N×M显示的多个部分; 并将多个部分发送到对应的多个显示器。

17. 发明申请

WO2009085232A1 ESTIMATION OF TRUE MOTION VECTORS USING AN ADAPTIVE SEARCH RANGE 审中-公开
标题翻译：使用自适应搜索范围估计真实运动矢量
公开(公告)号：WO2009085232A1
公开(公告)日：2009-07-09
申请号：PCT/US2008/013942
申请日：2008-12-18
申请人： INTEGRATED DEVICE TECHNOLOGY, INC. , ROSSIGNOL, Francois , LEDINH, Chon Tam , TRAN, Thi Thuy-Ha
发明人： ROSSIGNOL, Francois , LEDINH, Chon Tam , TRAN, Thi Thuy-Ha
IPC分类号： H04N7/26
CPC分类号： H04N19/194 , H04N19/513 , H04N19/521 , H04N19/57
摘要： A method and apparatus for estimating motion of a pixel block in a first frame, the method including searching a first area in a second frame to identify a first matching block that corresponds to the pixel block, the first matching block including a first error value that is a minimum of at least one error criteria between the pixel block and the first matching block, calculating a first motion vector associated with the first matching block. The method further including searching a second area in the second frame to identify a second matching block that corresponds to the pixel block, the second matching block including a second error value that is a minimum of the at least one error criteria between the pixel block and the second matching block, calculating a second motion vector associated with the second matching block and selecting a final motion vector between the first and second motion vectors based on the first and second error value.
摘要翻译：一种用于估计第一帧中的像素块的运动的方法和装置，所述方法包括搜索第二帧中的第一区域以识别对应于所述像素块的第一匹配块，所述第一匹配块包括第一误差值，是像素块和第一匹配块之间的至少一个误差标准的最小值，计算与第一匹配块相关联的第一运动向量。该方法还包括搜索第二帧中的第二区域以识别对应于像素块的第二匹配块，第二匹配块包括作为像素块与像素块之间的至少一个误差准则的最小值的第二误差值第二匹配块，计算与第二匹配块相关联的第二运动矢量，并且基于第一和第二误差值选择第一和第二运动矢量之间的最终运动矢量。

18. 发明申请

WO2007019338A3 METHOD AND APPARATUS FOR PREDICTIVE SWITCHING 审中-公开
公开(公告)号：WO2007019338A3
公开(公告)日：2007-02-15
申请号：PCT/US2006/030495
申请日：2006-08-04
申请人： INTEGRATED DEVICE TECHNOLOGY, INC.
发明人： FRANK, Ingolf
IPC分类号： H03D3/24
摘要： A method and apparatus for predictive switching an output have been disclosed.

19. 发明申请

WO2006135812A2 METHOD AND APPARATUS FOR SOURCE SYNCHRONOUS TESTING 审中-公开
标题翻译：用于源同步测试的方法和装置
公开(公告)号：WO2006135812A2
公开(公告)日：2006-12-21
申请号：PCT/US2006/022630
申请日：2006-06-09
申请人： INTEGRATED DEVICE TECHNOLOGY, INC.
发明人： SHRANK, Robert, W. , SOBAITI, Moussa , SHAMARAO, Prashant , BUTKA, Brian , HARRIS, Jim, K.
IPC分类号： G06F1/00
CPC分类号： G06F11/24 , G01R31/31725 , G01R31/31726 , G01R31/31727
摘要： A method and apparatus for source synchronous testing have been disclosed.
摘要翻译：已经公开了用于源同步测试的方法和装置。

20. 发明申请

WO2019139744A1 LASER DISTANCE SENSING USING PRIOR MEASUREMENT INFORMATION 审中-公开
公开(公告)号：WO2019139744A1
公开(公告)日：2019-07-18
申请号：PCT/US2018/066267
申请日：2018-12-18
申请人： INTEGRATED DEVICE TECHNOLOGY, INC.
发明人： HSIAO, Cheng Wen
IPC分类号： G01S17/89 , G01C3/02 , G01S17/06 , G01S17/08 , G01S17/88
摘要： A laser distance sensor (LDS) performs multiple measurement attempts with different values of operating parameters, e.g. of laser power gain (GL) or received light amplifier gain (GTIA). The parameter values, and the order of values for different measurement attempts, are determined from analysis of prior measurement data. Such data may include parameter values used in prior satisfactory measurements. The parameter values, the order indication, and other measurement information are stored by the LDS for use in subsequent measurements. Machine learning is performed to analyze stored data and determine the best parameter values and order for the current measurement.

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