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11. 发明专利

JPH1174223A METHOD FOR METAL LAYER FORMING ON SUBSTRATE 失效
公开(公告)号：JPH1174223A
公开(公告)日：1999-03-16
申请号：JP22840697
申请日：1997-08-25
申请人： CYPRESS SEMICONDUCTOR CORP
发明人： SAM GEHA
IPC分类号： C23C14/34 , H01L21/203 , H01L21/285
摘要： PROBLEM TO BE SOLVED: To form a metal layer that does not include voids or includes few voids on a substrate by speedily heating the substrate, when forming a metal layer on the substrate using a low-temperature deposition process and the succeeding high-temperature deposition process. SOLUTION: A method 200 for forming a metal layer on a substrate has a low-temperature deposition process 201 for depositing a metal, when a substrate is at a relatively low temperature and a high-temperature deposition process 202 for depositing a metal, when the substrate is at a relatively high temperature. By heating the substrate during the high-temperature deposition process 202, a metal (in some cases, also a metal that is deposited during the high-temperature deposition process 202 thereafter) that is deposited during the low-temperature deposition process 201 is further heated. In this case, the substrate is heated further rapidly during the high-temperature deposition process than the case of other metallization processes, including the high-temperature deposition process. Consequently, as a result, the mobility of metal atoms is increased further more rapidly than a conventional case. Especially, the mobility of an atom being farther away from the surface of the substrate increases further more rapidly than other methods.

12. 发明专利

JPH08274618A OVERVOLTAGE-RESISTANT INTEGRATED CIRCUIT OUTPUT BUFFER 失效
公开(公告)号：JPH08274618A
公开(公告)日：1996-10-18
申请号：JP3570096
申请日：1996-01-31
申请人： CYPRESS SEMICONDUCTOR CORP
发明人： JIYONASAN EFU CHIYAACHIRU
IPC分类号： H01L21/8238 , H01L27/092 , H03K19/003 , H03K19/0175 , H03K19/0948
摘要： PROBLEM TO BE SOLVED: To obtain the integrated circuit output buffer tolerant an overvoltage at input and output connection by applying nearly a voltage between a reference voltage and a voltage arisen at the input and output connection to a base region as a bias voltage. SOLUTION: An overvoltage detection circuit 40 produces an output on a node SENS so as to allow an input block circuit 46 receiving the output to block a signal on an input node A from a remaining buffer circuit 50. An I/O drive circuit 32 is used to provide a bias to an output node OUT or a supply destination which has a higher level and is biased at a voltage on the node OUT from a bias circuit 34. Furthermore, a driver changeover circuit 44 is separated from the supply destination because it receives signal levels on a node A3 resulting from an output from the input block circuit 46 and on a node A4. A voltage holding circuit 45 is configured so as not to switch on the I/O drive circuit 32 in mistake resulting from a capacitive coupling to a node A2 when the circuit 45 is a tri-state during restoration from an overvoltage.

13. 发明专利

JPS61190793A MEMORY ARRAY BIAS CIRCUIT FOR FAST CMOS DEVICE 失效
公开(公告)号：JPS61190793A
公开(公告)日：1986-08-25
申请号：JP28452485
申请日：1985-12-19
申请人： CYPRESS SEMICONDUCTOR CORP
发明人： KENESU II YANGU , BURUUSU ERU BEITOMAN
IPC分类号： H03K19/00 , G11C7/12 , H03K19/0948

14. 发明专利

JP4309210B2 Method and circuit for reading a potentiometer 有权
公开(公告)号：JP4309210B2
公开(公告)日：2009-08-05
申请号：JP2003309340
申请日：2003-09-01
申请人：サイプレスセミコンダクターコーポレーションCypress Semiconductor Corp.
发明人：ジー．ライトデーヴィッド , エス．ハットンバリー
IPC分类号： A63F13/02 , G01D5/16 , H03M1/50
CPC分类号： H03M1/50

15. 发明专利

JP2007115286A Bus interface system and method 有权
标题翻译：总线接口系统和方法
公开(公告)号：JP2007115286A
公开(公告)日：2007-05-10
申请号：JP2007012515
申请日：2007-01-23
申请人： Cypress Semiconductor Corp , サイプレス・セミコンダクタ・コーポレーション
发明人： SARTORE RONALD H , LARKY STEVEN P
IPC分类号： G06F13/14 , G06F13/10 , G06F13/42
CPC分类号： G06F13/10
摘要： PROBLEM TO BE SOLVED: To electronically simulate physical disconnection and reconnection of a peripheral device.
SOLUTION: The system for simulating disconnection and reconnection of the peripheral device connected to a host computer by a computer bus and port is provided with a first circuit for detecting the peripheral device connected to the port, and a second circuit for electronically simulating physical disconnection and reconnection of the peripheral device via the computer bus.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：电子模拟外围设备的物理断开和重新连接。解决方案：用于模拟通过计算机总线和端口连接到主计算机的外围设备的断开和重新连接的系统设置有用于检测连接到端口的外围设备的第一电路和用于电子模拟的第二电路通过计算机总线物理断开和重新连接外围设备。版权所有（C）2007，JPO＆INPIT

16. 发明专利

JPH09181181A TREATMENT METHOD TO MINIMIZE CORROSION OF LATERAL DIRECTION SPACER ON CONTACT REGION, AND SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH09181181A
公开(公告)日：1997-07-11
申请号：JP34372596
申请日：1996-12-24
申请人： CYPRESS SEMICONDUCTOR CORP
发明人： JIEEMUSU II NARUTEI , KURISUTOFUA JIEI PETEI
IPC分类号： H01L21/28 , H01L21/302 , H01L21/3065 , H01L21/311 , H01L21/336 , H01L21/60 , H01L21/768 , H01L21/8234 , H01L23/522 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To minimize corrosion of a lateral direction spacer on a contact region, and improve the alignment of a contact aperture to a gate electrode or another structure body. SOLUTION: A conducting layer is formed on a semiconductor main body, and an insulating layer adjacent to the conducting layer is deposited. An almost square insulative spacer is formed adjacently to a gate electrode. An etching stopper layer is deposited adjacently to the insulating layer, and etching is performed to eliminate the material of the etching stopper layer from the contact region. The etching is performed under the condition that the etching stopper layer can be eliminated and the form of the almost square lateral direction spacer of the insulating layer can be maintained.

17. 发明专利

JPH0922987A SINGLE END DUAL PORT MEMORY CELL 失效
公开(公告)号：JPH0922987A
公开(公告)日：1997-01-21
申请号：JP34946795
申请日：1995-12-22
申请人： CYPRESS SEMICONDUCTOR CORP
发明人： ANDORIYUU ERU HOOKINZU , SUTEFUAN PII SHIUIKU
IPC分类号： H01L27/10 , G11C8/16
摘要： PROBLEM TO BE SOLVED: To enable simultaneous access to a memory device by a plurality of system units by storing 1-bit data received from first and second ports, and being capable of simultaneously detecting the stored bits by the first and second ports. SOLUTION: NMOS transistors 350, 360 are functioned as a pass gate to the bit line 372 and band 382 of first port 270 and second port 380. A latch element for storing 1-bit data is formed of NMOS transistors 310 and 320 and PMOS transistors 330 and 340. The bit line 372 of the first port is used to write 1-bit data from the port 370 to a memory cell 300. The bit line 372 of the first port is used to read 1-bit information from the cell 300 via the port 370. The word line 374 of the first port is used to select the cell 300.

18. 发明专利

JPH08273364A FIVE-TRANSISTOR MEMORY CELL PROVIDED WITH SHARED POWER-SUPPLY LINE 失效
公开(公告)号：JPH08273364A
公开(公告)日：1996-10-18
申请号：JP2871196
申请日：1996-01-24
申请人： CYPRESS SEMICONDUCTOR CORP
发明人： PIITAA EICHI BUOSU , JIEFURII ERU RINDEN
IPC分类号： G11C11/412 , H01L21/8244 , H01L27/11
摘要： PROBLEM TO BE SOLVED: To reduce the number of transistors and bit lines per memory cell by forming constitution in which a static random access memory(SRAM) including five MOS transistors needs only two cells and three bit lines. SOLUTION: A first bit line 235 is connected on the opposite side to an SRAM cell 200 through a path transistor 225. A second bit line 265 is connected on the opposite side to an SRAM cell 210 through a path transistor 260. A third bit line 270 connects a power supply to the source terminals of p-channel transistors 205, 215, 240, 250. The gates of the path transistors 225, 260 are connected to a word line 230, and reading can be performed by the common basic line technique of a control circuit 275.

19. 发明专利

JPH08228147A CONTROL OF CLOCK GENERATOR,PHASE DETECTOR AND PLL 失效
公开(公告)号：JPH08228147A
公开(公告)日：1996-09-03
申请号：JP28237495
申请日：1995-10-05
申请人： CYPRESS SEMICONDUCTOR CORP
发明人： WILLIAMS BERTRAND J
IPC分类号： H03K5/26 , H03D13/00 , H03L7/085 , H04L7/033
摘要： PROBLEM TO BE SOLVED: To improve run length allowable difference by generating a third signal when a data signal remains in the same signal state over at least two transition edges in the same type of a clock signal. SOLUTION: A position detecting circuit 100 detects the transition edges of a data signal in a node 140, and outputs a pulse indicating the presence of the transition edge from an anode 181 to a phase detecting circuit 120. Moreover, a delay circuit 130 delays a data signal in the node 140, and outputs a delay data signal from a node 182. Then, the circuit 100 detects the transition edge of the data signal received in the node 140 more quickly than a position detecting circuit 110. In this case, when the transition edge of a clock signal is generated after the transition edge of the data signal, a first signal is generated, and when the transition edge of the clock signal is generated before the transition edge of the data signal, a second signal is generated. When the data signal remains in the same signal state over at least two transition edges in the same type of the clock signal, a third signal is generated.

20. 发明专利

JPH02101699A CIRCUIT CONTROLLING POWER TO PLURALITY OF SENSE AMPLIFIER 失效
公开(公告)号：JPH02101699A
公开(公告)日：1990-04-13
申请号：JP22473589
申请日：1989-09-01
申请人： CYPRESS SEMICONDUCTOR CORP
发明人： JIYAGUDEISHIYU PASAAKU , SUTEIIBUN EMU DAGURASU , HARU KAKOFUSUKII , DOBUUAMI BUAIDAA
IPC分类号： G11C17/00 , G05F3/24 , G11C7/06 , G11C16/06 , G11C16/26 , H03K5/04 , H03K19/00 , H03K19/177
摘要： PURPOSE: To reduce the consumption of electricity in a sense amplifier by feeding an electric power to the sense amplifier only during data transmission based on data passing time of a dummy cell array and dummy sense amplifier. CONSTITUTION: When clock pulses are applied to a circuit point A, the electric power is started feeding from the output OUT of a FF 148 to the sense amplifier via an inverter 140 and a NAND gate 141. At the same time, clock pulses at the point A are fed to the dummy cell array 143, having a delay amount more than the maximum data delay amount in a main array, and the dummy sense amplifier 145 via a dummy input resistor 142. Pulses passed the amplifier 145 are applied to the FF 148, the output OUT is put OFF, and the electric power is stopped feeding to the sense amplifier. By this way, the electric power is fed to the sense amplifier only during data transmission, thereby reducing the consumption of electricity.

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