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161. 发明申请

US20070239966A1 SELF-CONTAINED PROCESSOR SUBSYSTEM AS COMPONENT FOR SYSTEM-ON-CHIP DESIGN 有权
标题翻译：自包含处理器子系统作为系统片上设计的组件
公开(公告)号：US20070239966A1
公开(公告)日：2007-10-11
申请号：US11757166
申请日：2007-06-01
申请人： Christos Georgiou , Victor Gregurick , Valentina Salapura
发明人： Christos Georgiou , Victor Gregurick , Valentina Salapura
IPC分类号： G06F15/76
CPC分类号： G06F15/7832 , H04L49/109 , H04L49/602
摘要： A System-on-Chip (SoC) component comprising a single independent multiprocessor subsystem core including a plurality of multiple processors, each multiple processor having a local memory associated therewith forming a processor cluster; and a switch fabric means connecting each processor cluster within an SoC integrated circuit (IC). The single SoC independent multiprocessor subsystem core is capable of performing multi-threading operation processing for SoC devices when configured as a DSP, coprocessor, Hybrid ASIC, or network processing arrangements. The switch fabric means additionally interconnects a SoC local system bus device with SoC processor components with the independent multiprocessor subsystem core.
摘要翻译：一种片上系统（SoC）组件，其包括包括多个多个处理器的单个独立多处理器子系统核心，每个多处理器具有与其相关联的本地存储器形成处理器集群; 并且交换结构意味着连接SoC集成电路（IC）中的每个处理器集群。当配置为DSP，协处理器，混合ASIC或网络处理安排时，单个SoC独立多处理器子系统内核能够对SoC设备执行多线程操作处理。交换结构意味着另外将SoC本地系统总线设备与SoC处理器组件与独立的多处理器子系统核心互连。

162. 发明授权

US07003597B2 Dynamic reallocation of data stored in buffers based on packet size 失效
标题翻译：基于数据包大小动态重新分配存储在缓冲区中的数据
公开(公告)号：US07003597B2
公开(公告)日：2006-02-21
申请号：US10604295
申请日：2003-07-09
申请人： Christos John Georgiou , Valentina Salapura
发明人： Christos John Georgiou , Valentina Salapura
IPC分类号： G06F12/02
CPC分类号： H04L49/9078 , H04L49/90 , H04L49/901 , H04L49/9021 , H04L49/9052
摘要： A method and system is provided to efficiently manage memory in a network device that receives packets of variable size. The memory is allocated into portions whereby each portion, comprising multiple equally-sized buffers, receives packets of a particular size. One portion is used for smaller packet sizes and another portion is for larger packet sizes, although other portions may be created. As packets are received at the network device, they are stored into the appropriate memory portion based on their size. The number of available buffers in each portion is monitored so that, when it falls below a threshold, buffers are reallocated to the other thereby increasing the overall memory efficiency.
摘要翻译：提供了一种方法和系统来有效地管理接收可变大小的分组的网络设备中的存储器。存储器被分配到部分，由此包括多个相等大小的缓冲器的每个部分接收特定大小的分组。一部分用于较小的分组大小，另一部分用于较大的分组大小，但可以创建其他部分。当在网络设备处接收到分组时，它们基于它们的大小被存储到适当的存储器部分中。监视每个部分中的可用缓冲器的数量，使得当其低于阈值时，缓冲器被重新分配到另一个，从而增加整体存储器效率。

163. 发明授权

US06904040B2 Packet preprocessing interface for multiprocessor network handler 失效
标题翻译：用于多处理器网络处理程序的数据包预处理接口
公开(公告)号：US06904040B2
公开(公告)日：2005-06-07
申请号：US09682689
申请日：2001-10-05
申请人： Valentina Salapura , Christos J. Georgiou
发明人： Valentina Salapura , Christos J. Georgiou
IPC分类号： H04L12/56
CPC分类号： H04L47/2441 , H04L47/10 , H04L47/125 , H04L49/90
摘要： A network handler uses a DMA device to assign packets to network processors in accordance with a mapping function which classifies packets based on its content, e.g., bits in one or more header fields. Preferably, the mapping function is implemented as a hash function, which uses a predetermined number of bits from packet as inputs. The result of this function specifies the processor to which the packet is assigned. To make implementation manageable in a high-traffic environment, each processor may be equipped with a queue, which holds pointer information. Such a pointer provides an indication of the area in memory where incoming packet resides. The network handler is particularly useful in a Fiber Channel environment, where the hash function may be implemented to assign all packets from the same sequence to the same processor, thereby resulting in improved processing efficiency.
摘要翻译：网络处理器使用DMA设备来根据映射函数向网络处理器分配分组，所述映射函数根据其内容对分组进行分类，例如在一个或多个报头字段中的位。优选地，映射函数被实现为散列函数，其使用来自分组的预定数量的比特作为输入。此功能的结果指定分配给哪个分组的处理器。为了在高流量环境中实现可管理，每个处理器可以配备有保存指针信息的队列。这样的指针提供了输入分组所驻留的存储器中的区域的指示。网络处理器在光纤通道环境中特别有用，其中可以实现散列函数以将相同序列的所有分组分配给同一处理器，从而提高处理效率。

164. 发明授权

US09600281B2 Matrix multiplication operations using pair-wise load and splat operations 有权
公开(公告)号：US09600281B2
公开(公告)日：2017-03-21
申请号：US12834464
申请日：2010-07-12
申请人： Alexandre E. Eichenberger , Michael K. Gschwind , John A. Gunnels , Valentina Salapura
发明人： Alexandre E. Eichenberger , Michael K. Gschwind , John A. Gunnels , Valentina Salapura
IPC分类号： G06F9/30 , G06F9/312 , G06F9/38
CPC分类号： G06F9/30043 , G06F9/30014 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/30112 , G06F9/30145 , G06F9/3887
摘要： Mechanisms for performing a matrix multiplication operation are provided. A vector load operation is performed to load a first vector operand of the matrix multiplication operation to a first target vector register. A pair-wise load and splat operation is performed to load a pair of scalar values of a second vector operand and replicate the pair of scalar values within a second target vector register. An operation is performed on elements of the first target vector register and elements of the second target vector register to generate a partial product of the matrix multiplication operation. The partial product is accumulated with other partial products and a resulting accumulated partial product is stored. This operation may be repeated for a second pair of scalar values of the second vector operand.

165. 发明授权

US09292291B2 Instruction merging optimization 有权
标题翻译：指令合并优化
公开(公告)号：US09292291B2
公开(公告)日：2016-03-22
申请号：US13432458
申请日：2012-03-28
申请人： Michael K. Gschwind , Valentina Salapura
发明人： Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30181 , G06F9/3017 , G06F9/3836
摘要： A computer system for optimizing instructions is configured to identify two or more machine instructions as being eligible for optimization, to merge the two or more machine instructions into a single optimized internal instruction that is configured to perform functions of the two or more machine instructions, and to execute the single optimized internal instruction to perform the functions of the two or more machine instructions. Being eligible includes determining that the two or more machine instructions include a first instruction specifying a first target register and a second instruction specifying the first target register as a source register and a target register. The second instruction is a next sequential instruction of the first instruction in program order, wherein the first instruction specifies a first function to be performed, and the second instruction specifies a second function to be performed.
摘要翻译：用于优化指令的计算机系统被配置为将两个或更多个机器指令识别为有资格进行优化，以将两个或多个机器指令合并成被配置为执行两个或更多个机器指令的功能的单个优化内部指令，以及执行单个优化的内部指令来执行两个或更多个机器指令的功能。合格包括确定两个或多个机器指令包括指定第一目标寄存器的第一指令和指定第一目标寄存器作为源寄存器和目标寄存器的第二指令。第二指令是程序顺序中的第一指令的下一个顺序指令，其中第一指令指定要执行的第一功能，并且第二指令指定要执行的第二功能。

166. 发明授权

US09286067B2 Method and apparatus for a hierarchical synchronization barrier in a multi-node system 有权
标题翻译：多节点系统中分层同步屏障的方法和装置
公开(公告)号：US09286067B2
公开(公告)日：2016-03-15
申请号：US13614460
申请日：2012-09-13
申请人： Valentina Salapura , Robert W. Wisniewski
发明人： Valentina Salapura , Robert W. Wisniewski
IPC分类号： G06F9/52 , G06F9/30 , G06F9/38
CPC分类号： G06F9/522 , G06F9/30087 , G06F9/3851
摘要： A hierarchical barrier synchronization of cores and nodes on a multiprocessor system, in one aspect, may include providing by each of a plurality of threads on a chip, input bit signal to a respective bit in a register, in response to reaching a barrier; determining whether all of the plurality of threads reached the barrier by electrically tying bits of the register together and “AND”ing the input bit signals; determining whether only on-chip synchronization is needed or whether inter-node synchronization is needed; in response to determining that all of the plurality of threads on the chip reached the barrier, notifying the plurality of threads on the chip, if it is determined that only on-chip synchronization is needed; and after all of the plurality of threads on the chip reached the barrier, communicating the synchronization signal to outside of the chip, if it is determined that inter-node synchronization is needed.
摘要翻译：在一个方面，多处理器系统上的核心和节点的层级屏障同步可以包括：响应于达到屏障，将芯片上的多个线程中的每一个提供给寄存器中的相应位的输入比特信号; 确定所有多个线程是否通过将所述寄存器的位电一体化并将所述输入位信号“AND”到达所述障碍物; 确定是否仅需要片上同步或者是否需要节点间同步; 响应于确定芯片上的所有多个线程到达屏障，通知芯片上的多个线程，如果确定仅需要片上同步; 并且如果确定需要节点间同步，则在芯片上的所有多个线程到达屏障之后，将同步信号传送到芯片外部。

167. 发明授权

US09170888B2 Methods and apparatus for virtual machine recovery 有权
标题翻译：虚拟机恢复的方法和装置
公开(公告)号：US09170888B2
公开(公告)日：2015-10-27
申请号：US13493304
申请日：2012-06-11
申请人： Valentina Salapura , Richard E. Harper , Kyung D. Ryu
发明人： Valentina Salapura , Richard E. Harper , Kyung D. Ryu
IPC分类号： G06F11/00 , G06F11/14 , G06F11/20
CPC分类号： G06F11/1415 , G06F11/1417 , G06F11/1484 , G06F11/2041
摘要： Methods and apparatus for recovery of virtual machine failure. A succession of data images is captured, with each of the data images comprising an operating system of the virtual machine. The data images are images of data elements chosen based at least in part on their suitability for virtual machine restoration. Upon detection of a virtual machine failure, an attempt is made to restore the virtual machine using the highest ranked. If the attempt fails, further attempts are made using lower ranked data images, until an attempt is successful or all available data images have been used.
摘要翻译：恢复虚拟机故障的方法和设备。捕获连续的数据图像，其中每个数据图像包括虚拟机的操作系统。数据图像是至少部分地基于其对虚拟机恢复的适用性而选择的数据元素的图像。在检测到虚拟机故障时，尝试使用最高排名恢复虚拟机。如果尝试失败，则进一步尝试使用较低排名的数据图像，直到尝试成功或已使用所有可用的数据图像。

168. 发明授权

US09069891B2 Hardware enabled performance counters with support for operating system context switching 有权
标题翻译：支持硬件的性能计数器，支持操作系统上下文切换
公开(公告)号：US09069891B2
公开(公告)日：2015-06-30
申请号：US12684190
申请日：2010-01-08
申请人： Valentina Salapura , Robert W. Wisniewski
发明人： Valentina Salapura , Robert W. Wisniewski
IPC分类号： G06F15/00 , G06F7/38 , G06F9/00 , G06F9/44 , G06F11/34 , G06F9/46
CPC分类号： G06F11/348 , G06F9/461 , G06F2201/88
摘要： A device for supporting hardware enabled performance counters with support for context switching include a plurality of performance counters operable to collect information associated with one or more computer system related activities, a first register operable to store a memory address, a second register operable to store a mode indication, and a state machine operable to read the second register and cause the plurality of performance counters to copy the information to memory area indicated by the memory address based on the mode indication.
摘要翻译：用于支持具有对上下文切换的支持的支持硬件的性能计数器的设备包括多个性能计数器，可操作以收集与一个或多个计算机系统相关活动相关联的信息，可操作以存储存储器地址的第一寄存器，模式指示，以及可操作以读取第二寄存器并使多个性能计数器基于模式指示将信息复制到由存储器地址指示的存储区域的状态机。

169. 发明授权

US08972788B2 Ticket consolidation 有权
标题翻译：票务合并
公开(公告)号：US08972788B2
公开(公告)日：2015-03-03
申请号：US13348172
申请日：2012-01-11
申请人： Michael K. Gschwind , Ruchi Mahindru , Valentina Salapura
发明人： Michael K. Gschwind , Ruchi Mahindru , Valentina Salapura
IPC分类号： G06F11/00
CPC分类号： G06F11/3075 , G06F11/3006
摘要： A method of ticket consolidation in computing environment may in one aspect analyze problem reports, determine whether problems reported by machines are caused by the same or substantially the same run-time configuration error or are occurring on the same physical server, and are within the given sensitivity time window, consolidate the problem tickets and increase the priority of the consolidated ticket.
摘要翻译：在计算环境中的票据合并的方法可以在一个方面分析问题报告，确定机器报告的问题是由相同或基本相同的运行时配置错误引起的，或者是在相同的物理服务器上发生的，并且在给定的敏感时间窗口，整合问题单，增加综合票的优先级。

170. 发明授权

US08806501B2 Predictive dynamic system scheduling 有权
标题翻译：预测动态系统调度
公开(公告)号：US08806501B2
公开(公告)日：2014-08-12
申请号：US12751288
申请日：2010-03-31
申请人： Liana L. Fong , Valentina Salapura , Seetharami Seelam
发明人： Liana L. Fong , Valentina Salapura , Seetharami Seelam
IPC分类号： G06F9/46 , G06F15/173 , G06F9/50
CPC分类号： G06F9/5061
摘要： Resources of a partitionable computer system are partitioned into at least first and second partitions, in accordance with a first or second mode of operation of the partitionable computer system. The system is run in the first or second mode, partitioned in accordance with the partitioning step. Periodically, it is determined whether the computer system should be switched from one mode to the other mode. If so, the computer system is run in the other mode, partitioned in accordance with the other mode. The first and second modes of operation are defined in accordance with historical observations of the partitionable computer system. The periodic determination is carried out based on predictions in accordance with the historical observations.
摘要翻译：根据可分割计算机系统的第一或第二操作模式，可分区计算机系统的资源被划分成至少第一和第二分区。系统以第一或第二模式运行，根据分区步骤进行分区。定期地，确定计算机系统是否应该从一种模式切换到另一模式。如果是这样，则计算机系统以其他模式运行，根据其他模式进行分区。第一和第二操作模式根据可分区计算机系统的历史观察来定义。根据历史观察的预测进行周期性测定。

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