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131. 发明授权

US4980316A Method for producing a resist structure on a semiconductor 失效
标题翻译：在半导体上制造抗蚀剂结构的方法
公开(公告)号：US4980316A
公开(公告)日：1990-12-25
申请号：US385670
申请日：1989-07-26
申请人： Holger Huebner
发明人： Holger Huebner
IPC分类号： H01L21/302 , H01L21/027 , H01L21/285 , H01L21/3065 , H01L21/338 , H01L21/768 , H01L23/522 , H01L21/465
CPC分类号： H01L29/66863 , H01L21/0271 , H01L21/28587 , Y10S438/95 , Y10S438/951
摘要： A method for producing a resist structure on a semiconductor material which has an opening tapering towards the semiconductor material is provided. This method can be used, for example, for the manufacturing of T-gate metallizations in a field effect transistor. In this method, a thin, upper resist layer is structured, and the structure is transferred onto a silicon nitride layer. The structure is then transferred into a thickly applied resist while widening the upper part of the etching profile. The method is accomplished by a succession of anisotropic and isotropic dry etching steps.
摘要翻译：提供了一种在半导体材料上制造抗蚀剂结构的方法，其具有朝向半导体材料逐渐变细的开口。该方法可用于例如场效应晶体管中的T栅极金属化的制造。在该方法中，形成了薄的上抗蚀剂层，并将结构转移到氮化硅层上。然后将该结构转移到厚施加的抗蚀剂中，同时加宽蚀刻轮廓的上部。该方法通过一系列各向异性和各向同性的干蚀刻步骤来实现。

132. 发明授权

US4975382A Method of making a self-aligned field-effect transistor by the use of a dummy-gate 失效
标题翻译：通过使用虚拟栅极制作自对准场效应晶体管的方法
公开(公告)号：US4975382A
公开(公告)日：1990-12-04
申请号：US522514
申请日：1990-05-11
申请人： Satoru Takasugi
发明人： Satoru Takasugi
IPC分类号： H01L29/812 , H01L21/28 , H01L21/285 , H01L21/338
CPC分类号： H01L29/66871 , H01L21/28587 , Y10S148/053 , Y10S148/111 , Y10S438/951
摘要： A T-shaped gate of an FET is formed by utilizing the image reverse photolithography process, which includes coating of a semiconductor substrate with a positive resist, initial exposure of an resist outside region, reversal baking, flood exposure of the entire resist layer, and development of the resist layer. The image reverse photolithography process is performed after a dummy gate is formed on the semiconductor substrate. By properly adjusting a light quantity of the flood exposure, a resist pattern can be obtained which has a center hole whose boundary surface is inclined inwardly, and whose bottom surface defines a bottom resist layer thinner than the dummy gate. After removing the dummy gate, a gate material is deposited and then the resist pattern is removed to leave the T-shaped gate.
摘要翻译：通过利用图像反向光刻工艺形成FET的T形栅极，其包括用正性抗蚀剂涂覆半导体衬底，抗蚀剂外部区域的初始曝光，反转烘烤，整个抗蚀剂层的泛光曝光，以及抗蚀剂层的开发。在半导体衬底上形成虚拟栅极之后执行图像反向光刻工艺。通过适当地调整淹水的光量，可以获得具有边界面向内倾斜的中心孔，并且其底面限定比虚拟栅极薄的底部抗蚀剂层的抗蚀剂图案。在去除虚拟栅极之后，沉积栅极材料，然后去除抗蚀剂图案以离开T形栅极。

133. 发明授权

US4933303A Method of making self-aligned tungsten interconnection in an integrated circuit 失效
标题翻译：在集成电路中制造自对准钨互连的方法
公开(公告)号：US4933303A
公开(公告)日：1990-06-12
申请号：US384974
申请日：1989-07-25
申请人： Roy Mo
发明人： Roy Mo
IPC分类号： H01L21/3205 , H01L21/768
CPC分类号： H01L21/7688 , Y10S438/951
摘要： A process is disclosed for making a self-aligned metal (preferably tungsten) connection in an integrated circuit. A contact hole formed in a first dielectric layer on a substrate is filled with metal, after which the first dielectric layer and the metal-filled contact hole are covered with a second dielectric layer. A photoresist layer is formed over the second dielectric layer and is patterned. A trench is formed in the exposed second dielectric layer and a thin layer of silicon or a metal such as tungsten is then sputtered or evaporated to form a layer of the silicon or metal on the upper surface of the patterned photoresist and the bottom and side walls of the trench. The patterned photoresist is removed and the trench is filled with metal.
摘要翻译：公开了用于在集成电路中制造自对准金属（优选钨）连接的方法。形成在基板上的第一电介质层中的接触孔用金属填充，之后第一介电层和金属填充的接触孔被第二介电层覆盖。在第二电介质层上形成光致抗蚀剂层并进行图案化。在暴露的第二电介质层中形成沟槽，然后溅射或蒸发硅或诸如钨的金属的薄层，以在图案化光致抗蚀剂的上表面上形成硅或金属层，并且底部和侧壁的沟槽。去除图案化的光致抗蚀剂，并用金属填充沟槽。

134. 发明授权

US4931137A Process for producing mutually spaced conductor elements on a substrate 失效
标题翻译：在基板上制造相互间隔的导体元件的工艺
公开(公告)号：US4931137A
公开(公告)日：1990-06-05
申请号：US121678
申请日：1987-11-17
申请人： Henri Sibuet
发明人： Henri Sibuet
IPC分类号： H01L21/3205 , G11B5/31 , H01F41/34 , H01L21/033 , H01L21/28 , H05K3/14 , H01L21/00 , H01L21/283 , H01L21/308
CPC分类号： G11B5/3163 , H01F41/34 , H01L21/0337 , H01L21/28 , H05K3/143 , Y10S438/947 , Y10S438/951
摘要： The invention relates to a process for producing on a substrate conductor elements which are mutually spaced by a submicron dimension.This process comprises the stages of producing on substrate (1) spacers, whose dimensions and spacing are a function of the dimensions and spacing of the elements (11a) to be produced, anisotropic deposition on the substrate and perpendicular thereto of the material (11a) constituting the spacers and elimination of said spacers.The invention applies to the production of any random elements and particularly to the production of slightly mutually spaced electric conductors.
摘要翻译：本发明涉及一种用于在基板上制造相互间隔有亚微米尺寸的导体元件的方法。该方法包括在衬底（1）间隔件上生产的阶段，其尺寸和间距是要生产的元件（11a）的尺寸和间距的函数，基板上的各向异性沉积以及与材料（11a）垂直的各向异性沉积，构成间隔物并消除所述间隔物。本发明适用于生产任何随机元件，特别适用于生产稍微相互间隔的电导体。

135. 发明授权

US4902646A MESFET process employing dummy electrodes and resist reflow 失效
标题翻译： MESFET工艺采用虚拟电极和抗回流焊
公开(公告)号：US4902646A
公开(公告)日：1990-02-20
申请号：US276484
申请日：1988-11-28
申请人： Hirofumi Nakano
发明人： Hirofumi Nakano
IPC分类号： H01L29/812 , H01L21/28 , H01L21/338
CPC分类号： H01L29/66863 , H01L21/28 , Y10S148/111 , Y10S438/926 , Y10S438/951
摘要： A production method for a semiconductor device (e.g. MESFET) includes a metal pattern production process for producing a plurality of metal patterns e.g. gate, source, drain electrodes on a semiconductor substrate having an active layer. The metal pattern production process includes disposing dummy metal patterns (2a/2b) of silicon nitride at a plurality of metal pattern production regions on the semiconductor substrate using a resist mask (3), disposing a resist pattern (4) on the entire surface of the substrate with gaps between the metal pattern production regions, filling the gaps between said dummy metal patterns and the resist pattern with resist by reflowing the resist pattern (4), removing the dummy metal patterns (2a), depositing a metal layer over the entire surface of the partially completed device, and lifting off unwanted metal to produce a desired metal pattern of source/drain electrodes (5). The second and subsequent steps for replacing the dummy metal pattern with the metal pattern are repeated using another resist pattern (6) to form gate electrode (7).
摘要翻译：半导体器件（例如MESFET）的制造方法包括用于制造多个金属图案的金属图案制造工艺，例如，栅极，源极，漏电极，具有活性层。金属图案的制造方法包括使用抗蚀剂掩模（3）在半导体基板上的多个金属图案生产区域上设置氮化硅的虚设金属图案（2a / 2b），将抗蚀剂图案（4）设置在所述基板在所述金属图案生产区域之间具有间隙，通过回流所述抗蚀剂图案（4）填充所述虚设金属图案和所述抗蚀剂图案之间的间隙，去除所述伪金属图案（2a），在整个所述金属图案生成区域上沉积金属层部分完成的装置的表面，并且提起不需要的金属以产生所需的源极/漏极（5）的金属图案。使用另一抗蚀剂图案（6）重复用金属图案替换虚拟金属图案的第二和随后的步骤，以形成栅电极（7）。

136. 发明授权

US4861425A Lift-off process for terminal metals 失效
标题翻译：终端金属剥离工艺
公开(公告)号：US4861425A
公开(公告)日：1989-08-29
申请号：US234728
申请日：1988-08-22
申请人： Stuart E. Greer , Robert T. Howard, Jr.
发明人： Stuart E. Greer , Robert T. Howard, Jr.
IPC分类号： H01L21/3205 , H01L21/28 , H01L21/60 , H01L23/485
CPC分类号： H01L24/13 , H01L24/11 , H01L2224/1147 , H01L2224/13099 , H01L2224/131 , H01L2924/0001 , H01L2924/01006 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , Y10S438/951
摘要： A process is described for selective removal of unwanted metallization from the surface of a semiconductor device. The process comprises the usual deposition of a configurable image defining layer on the surface of the device upon which a suitable pad limiting metallurgy (PLM) has already been deposited. The layer is then opened over the pad limiting metallurgy using standard techniques and coated with a layer of the terminal metal. The coated device is then heated to just above the melting point of the terminal metal causing the melted metal, through surface tension to form a ball of metal on the PLM and to form small globules of metal on the surface of the layer and then permitted to cool. When cooled the layer is removed using the usual techniques. Because the coating of terminal metal is no longer a continuous layer on the surface of the mask, removal of the polymer mask can be accomplished in about one-tenth of the time required when compared to a deposited terminal metal layer that is not melted. Also because of the effects of surface tension the metal coating need only be one-half the thickness required under the prior art techniques.

137. 发明授权

US4684435A Method of manufacturing thin film transistor 失效
标题翻译：制造薄膜晶体管的方法
公开(公告)号：US4684435A
公开(公告)日：1987-08-04
申请号：US829001
申请日：1986-02-13
申请人： Kohhei Kishi , Mitsuhiro Koden , Fumiaki Funada
发明人： Kohhei Kishi , Mitsuhiro Koden , Fumiaki Funada
IPC分类号： G02F1/1368 , H01L21/308 , H01L21/336 , H01L21/77 , H01L21/84 , H01L29/786 , H01L21/306 , C23F1/02
CPC分类号： H01L27/1214 , G02F1/1368 , H01L21/308 , H01L29/66765 , H01L29/78669 , Y10S148/10 , Y10S438/951
摘要： An improved process for manufacturing a thin film transistor uses two masks for etching and therefore one mask alignment. The technical effect of said process is to provide the thin film transistor with low cost and enhanced yield.
摘要翻译：用于制造薄膜晶体管的改进方法使用两个用于蚀刻的掩模，因此一个掩模对准。所述工艺的技术效果是以低成本和高产率提供薄膜晶体管。

138. 发明授权

US4662989A High efficiency metal lift-off process 失效
标题翻译：高效金属剥离工艺
公开(公告)号：US4662989A
公开(公告)日：1987-05-05
申请号：US784925
申请日：1985-10-04
申请人： Daniel K. Casey , Eddie C. Lee
发明人： Daniel K. Casey , Eddie C. Lee
IPC分类号： H01L21/027 , H01L21/768 , H01L21/98 , B44C1/22 , B29C37/00 , C03C15/00 , C03C25/06
CPC分类号： H01L25/50 , H01L21/0272 , H01L21/7688 , H01L2924/0002 , Y10S438/951
摘要： An improved high efficiency metal lift-off process for removing a layer of metal at least partially covering a layer of photoresist. The method comprises forming microcracks located above the layer of photoresist in the layer of metal to be removed and providing solvent to the layer of photoresist through the microcracks.
摘要翻译：用于去除至少部分地覆盖光致抗蚀剂层的金属层的改进的高效金属剥离方法。该方法包括在待除去的金属层中形成位于光致抗蚀剂层之上的微裂纹，并通过微裂纹向光致抗蚀剂层提供溶剂。

139. 发明授权

US4601095A Process for fabricating a Schottky-barrier gate field effect transistor 失效
标题翻译：制造肖特基势垒栅场效应晶体管的工艺
公开(公告)号：US4601095A
公开(公告)日：1986-07-22
申请号：US361070
申请日：1982-03-23
申请人： Kenichi Kikuchi , Michitomo Iiyama , Toshiki Ebata , Hideki Hayashi
发明人： Kenichi Kikuchi , Michitomo Iiyama , Toshiki Ebata , Hideki Hayashi
IPC分类号： H01L21/28 , H01L21/285 , H01L21/338 , H01L29/10 , H01L29/47 , H01L29/812
CPC分类号： H01L29/66878 , H01L21/28 , H01L21/28587 , H01L29/1029 , H01L29/475 , H01L29/812 , Y10S438/909 , Y10S438/918 , Y10S438/951
摘要： A process for fabricating a Schottky-barrier gate field effect transistor, consists of forming an active layer of one electrically conductive type semiconductor crystal on one surface of a high resistivity or semi-insulating semiconductor crystal substrate, the active layer having a first active layer whose thickness and carrier concentration are so chosen as to give a predetermined value of pinch-off voltage and a second active layer having a carrier concentration which is substantially equal to that of the first active layer and having a larger thickness than that of the first active layer and provided on both sides of the first active layer; the first shallow active layer is provided with a Schottky-barrier gate electrode correctly positioned on the surface part and the second thick active layer is provided with a source electrode and drain electrode on the surface part.
摘要翻译：制造肖特基势垒栅场效应晶体管的工艺包括在高电阻率或半绝缘半导体晶体衬底的一个表面上形成一个导电型半导体晶体的有源层，该有源层具有第一有源层，选择厚度和载流子浓度以给出预定的夹断电压值，以及具有基本上等于第一有源层的载流子浓度并且具有比第一有源层的厚度大的厚度的第二有源层并设置在第一有源层的两侧; 第一浅有源层设置有正确位于表面部分上的肖特基势垒栅极，并且第二厚有源层在表面部分上设置有源电极和漏电极。

140. 发明授权

US4566940A Manufacturing process for semiconductor integrated circuits 失效
标题翻译：半导体集成电路制造工艺
公开(公告)号：US4566940A
公开(公告)日：1986-01-28
申请号：US661700
申请日：1984-10-17
申请人： Manabu Itsumi , Kohei Ehara , Susumu Muramoto , Seitaro Matsuo
发明人： Manabu Itsumi , Kohei Ehara , Susumu Muramoto , Seitaro Matsuo
IPC分类号： H01L21/3205 , H01L21/027 , H01L21/762 , H01L21/768 , H01L21/306 , B44C1/22 , C03C15/00 , C23F1/02
CPC分类号： H01L21/7688 , H01L21/0272 , H01L21/762 , Y10S438/951
摘要： A semiconductor integrated circuit in which layers such as an field isolation region, a gate electrode, interlayer insulating films and interconnection lines are formed by the combined use of a lift-off process and an ECR plasma deposition process. According to the present invention, even if vertical dimensions of patterns of the respective layers are large as compared with their lateral dimensions, the upper surfaces of the respective layers can be planarized, permitting the fabrication of an LSI of high packing density, high operating speed and high reliability which is free from shorting and breakage of the interconnection lines.

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