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131. 发明授权

US09214400B2 Semiconductor device with back gate isolation regions and method for manufacturing the same 有权
标题翻译：具有背栅隔离区的半导体器件及其制造方法
公开(公告)号：US09214400B2
公开(公告)日：2015-12-15
申请号：US13504643
申请日：2011-11-18
申请人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L21/84 , H01L27/1203
摘要： The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises: an SOI wafer comprising a semiconductor substrate, an insulating buried layer, and a semiconductor layer, wherein the insulating buried layer is disposed on the semiconductor substrate, and the semiconductor layer is disposed on the insulating buried layer; adjacent MOSFETs formed in the SOI wafer, wherein each of the adjacent MOSFETs comprises a back gate formed in the semiconductor substrate and a back gate isolation region formed completely under the back gate; and a shallow trench isolation, wherein the shallow trench isolation is formed between the adjacent MOSFETs to isolate the adjacent MOSFETs from each other, wherein a PN junction is formed between the back gate and the back gate isolation region of each of the adjacent MOSFETs. According to embodiments of the present disclosure, a PN junction is formed between the back gate isolation regions of the adjacent MOSFETs. In addition to back gate isolation implemented by the shallow trench isolation between the adjacent MOSFETs, the adjacent MOSFETs are also isolated by means of PNPN junctions or NPNP junctions formed in the back gates and the back gate isolation regions. As a result, the semiconductor device has a better isolation effect, and thus the possibility of accidental breakdown of the semiconductor device is substantially reduced.
摘要翻译：本发明提供一种半导体器件及其制造方法。半导体器件包括：SOI晶片，其包括半导体衬底，绝缘掩埋层和半导体层，其中绝缘掩埋层设置在半导体衬底上，并且半导体层设置在绝缘掩埋层上; 形成在SOI晶片中的相邻MOSFET，其中每个相邻的MOSFET包括形成在半导体衬底中的背栅和完全在后栅下形成的背栅隔离区; 和浅沟槽隔离，其中在相邻的MOSFET之间形成浅沟槽隔离以将相邻的MOSFET彼此隔离，其中在每个相邻MOSFET的背栅极和背栅极隔离区域之间形成PN结。根据本公开的实施例，在相邻MOSFET的背栅隔离区之间形成PN结。除了通过相邻MOSFET之间的浅沟槽隔离实现的背栅隔离之外，相邻的MOSFET也通过形成在后栅极和后栅极隔离区域中的PNPN结或NPNP结隔离。结果，半导体器件具有更好的隔离效果，从而显着降低了半导体器件意外击穿的可能性。

132. 发明授权

US09082849B2 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US09082849B2
公开(公告)日：2015-07-14
申请号：US13580966
申请日：2012-05-14
申请人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L29/78 , H01L21/84 , H01L21/762 , H01L21/8234 , H01L29/66
CPC分类号： H01L29/785 , H01L21/7624 , H01L21/823431 , H01L21/845 , H01L29/66795
摘要： The present invention provides a method for manufacturing a semiconductor structure, comprising the steps of: providing a semiconductor substrate, forming an insulating layer on the semiconductor substrate, and forming a semiconductor base layer on the insulating layer; forming a sacrificial layer and a spacer surrounding the sacrificial layer on the semiconductor base layer, and etching the semiconductor base layer by taking the spacer as a mask to form a semiconductor body; forming a dielectric film on sidewalls of the semiconductor body; removing the sacrificial layer and the semiconductor body located under the sacrificial layer to form a first semiconductor fin and a second semiconductor fin; and forming a retrograde doped well structure on the inner walls of the first semiconductor fin and the second semiconductor fin, wherein the inner walls thereof are opposite to each other. Correspondingly, the present invention further provides a semiconductor structure. In the present invention, a retrograde doped well structure is formed on the sidewalls of the two semiconductor fins that are opposite to each other, so that the width of the source/drain depletion layer may be effectively reduced, and thereby the short channel effect is reduced.
摘要翻译：本发明提供一种制造半导体结构的方法，包括以下步骤：提供半导体衬底，在半导体衬底上形成绝缘层，并在绝缘层上形成半导体基底层; 在所述半导体基底层上形成包围所述牺牲层的牺牲层和间隔物，并且通过以所述间隔物作为掩模来蚀刻所述半导体基底层以形成半导体本体; 在所述半导体主体的侧壁上形成电介质膜; 去除位于牺牲层下面的牺牲层和半导体本体以形成第一半导体鳍片和第二半导体鳍片; 以及在所述第一半导体翅片和所述第二半导体翅片的内壁上形成逆向掺杂的阱结构，其中所述内壁彼此相对。相应地，本发明还提供一种半导体结构。在本发明中，在两个相互相对的两个半导体鳍片的侧壁上形成逆向掺杂阱结构，从而可以有效地减小源/漏耗尽层的宽度，从而短沟道效应为减少

133. 发明申请

US20150145046A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20150145046A1
公开(公告)日：2015-05-28
申请号：US14397586
申请日：2012-05-22
申请人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L27/12 , H01L29/66 , H01L21/266 , H01L21/02 , H01L21/306 , H01L21/308 , H01L21/768 , H01L29/78 , H01L21/84
CPC分类号： H01L27/1203 , H01L21/02529 , H01L21/02532 , H01L21/2652 , H01L21/266 , H01L21/30604 , H01L21/3081 , H01L21/743 , H01L21/76897 , H01L21/84 , H01L29/165 , H01L29/66636 , H01L29/66659 , H01L29/66772 , H01L29/78 , H01L29/78612 , H01L29/78648
摘要： The present invention provides a method for manufacturing a semiconductor structure, which comprises following steps: providing a substrate, which comprises upwards in order a base layer, a buried isolation layer, a buried ground layer, an ultra-thin insulating buried layer and a surface active layer; implementing ion implantation doping to the buried ground layer; forming a gate stack, sidewall spacers and source/drain regions on the substrate; forming a mask layer on the substrate that covers the gate stack and the source/drain regions, and etching the mask layer to expose the source region; etching the source region and the ultra-thin insulating buried layer under the source region to form an opening that exposes the buried ground layer; filling the opening through epitaxial process to form a contact plug for the buried ground layer. Accordingly, the present invention further provides a semiconductor structure. The present invention proposes formation of a buried ground layer contact plug, which thence connects buried ground layer electrically to source region, thereby enhancing control capabilities of a semiconductor device over threshold voltages, suppressing short-channel effects and improving device performance; whereas no independent contact is required to build for the buried ground layer, which thence saves device area and simplifies manufacturing process accordingly.
摘要翻译：本发明提供了一种制造半导体结构的方法，其包括以下步骤：提供基底，其基本层向上依次包括掩埋隔离层，埋地层，超薄绝缘掩埋层和表面活性层对埋地层进行离子注入掺杂; 在衬底上形成栅极堆叠，侧壁间隔物和源极/漏极区域; 在覆盖栅极堆叠和源极/漏极区域的衬底上形成掩模层，并蚀刻掩模层以暴露源极区域; 蚀刻源极区域下的源极区域和超薄绝缘掩埋层，形成暴露埋入地层的开口; 通过外延工艺填充开口以形成埋地层的接触塞。因此，本发明还提供一种半导体结构。本发明提出一种掩埋地层接触塞的形成，其将掩埋地层电连接到源极区域，从而提高半导体器件在阈值电压下的控制能力，抑制短沟道效应和提高器件性能; 而不需要独立的接触来构建埋地层，从而节省设备面积并相应地简化制造过程。

134. 发明授权

US09012272B2 MOSFET and method for manufacturing the same 有权
标题翻译： MOSFET及其制造方法
公开(公告)号：US09012272B2
公开(公告)日：2015-04-21
申请号：US13379444
申请日：2011-08-01
申请人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L21/00 , H01L21/84 , H01L21/336 , H01L21/76 , H01L27/12 , H01L21/265 , H01L29/423 , H01L29/786
CPC分类号： H01L21/2652 , H01L21/2658 , H01L29/42384 , H01L29/78648
摘要： The present application discloses an MOSFET and a method for manufacturing the same. The MOSFET comprises: a semiconductor substrate; a first insulation buried layer disposed on the semiconductor substrate; a back gate formed in a first semiconductor layer which is disposed on the first insulation buried layer; a second insulation buried layer disposed on the first semiconductor layer; source/drain regions formed in a second semiconductor layer which is disposed on the second insulation buried layer; a gate disposed on the second semiconductor layer; and electric connections to the source/drain regions, the gate and the back gate, wherein the back gate comprises first back gate regions of a first conductivity type which are disposed under the source/drain regions and a second back gate region of a second conductivity type which is disposed under a channel region, the first back gate regions adjoins the second back gate region, the first conductivity type is opposite to the second conductivity type, and the electric connection to the back gate comprise a conductive via contacted with one of the first back gate regions. The MOSFET, of any conductivity type, can have adjustable threshold voltage and reduced leakage current via the back gate between the source/drain regions by using the back gate in the form of a PNP junction or an NPN junction.
摘要翻译：本申请公开了一种MOSFET及其制造方法。 MOSFET包括：半导体衬底; 设置在所述半导体基板上的第一绝缘埋层; 形成在第一绝缘掩埋层上的第一半导体层中形成的背栅; 设置在所述第一半导体层上的第二绝缘埋层; 源极/漏极区域，形成在第二绝缘掩埋层上的第二半导体层中; 设置在所述第二半导体层上的栅极; 以及与源极/漏极区域，栅极和背栅极的电连接，其中所述背栅极包括设置在所述源极/漏极区域下方的第一导电类型的第一后栅极区域和具有第二导电性的第二背栅极区域所述第一导电类型与所述第二导电类型相反，并且与所述第二导电类型的电连接包括与所述第二导电类型之一接触的导电通孔，第一个后门区域。任何导电类型的MOSFET可以通过使用PNP结或NPN结形式的背栅，通过源极/漏极区之间的背栅极具有可调节的阈值电压和减小的漏电流。

135. 发明申请

US20150084130A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：半导体结构及其制造方法
公开(公告)号：US20150084130A1
公开(公告)日：2015-03-26
申请号：US14397558
申请日：2012-05-16
申请人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L29/78 , H01L21/02 , H01L21/762 , H01L27/12 , H01L29/66
CPC分类号： H01L29/7841 , H01L21/02532 , H01L21/76264 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203 , H01L29/6656 , H01L29/66772 , H01L29/78612 , H01L29/78648
摘要： The present invention provides a method for manufacturing a semiconductor structure, which comprises following steps: providing an SOI substrate, onto which a heavily doped buried layer and a surface active layer are formed; forming a gate stack and sidewall spacers on the substrate; forming an opening at one side of the gate stack, wherein the opening penetrates through the surface active layer, the heavily doped buried layer and reaches into a silicon film located on an insulating buried layer of the SOI substrate; filling the opening to form a plug; forming source/drain regions, wherein the source region overlaps with the heavily doped buried layer, and a part of the drain region is located in the plug. Accordingly, the present invention further provides a semiconductor structure. In the present invention, the heavily doped buried layer is favorable for reducing width of depletion layers at source/drain regions and suppressing short-channel effects. The heavily doped buried layer overlaps with the source region, which thence forms a heavily doped pn junction favorable for suppressing floating body effects of SOI MOS devices, thereby improving performance of semiconductor devices. Besides, no body contact is needed in the present invention, thus device area and manufacturing cost are saved.
摘要翻译：本发明提供一种制造半导体结构的方法，其包括以下步骤：提供SOI衬底，在其上形成重掺杂掩埋层和表面活性层; 在衬底上形成栅极叠层和侧壁间隔物; 在所述栅极叠层的一侧形成开口，其中所述开口穿过所述表面有源层，所述重掺杂掩埋层并进入位于所述SOI衬底的绝缘掩埋层上的硅膜; 填充开口形成插头; 形成源极/漏极区域，其中源极区域与重掺杂的掩埋层重叠，并且漏极区域的一部分位于插塞中。因此，本发明还提供一种半导体结构。在本发明中，重掺杂掩埋层有利于减小源极/漏极区的耗尽层的宽度并抑制短沟道效应。重掺杂掩埋层与源区重叠，从而形成重掺杂pn结，有利于抑制SOI MOS器件的浮体效应，从而提高半导体器件的性能。此外，在本发明中不需要接触体，从而节省了设备面积和制造成本。

136. 发明申请

US20150076603A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20150076603A1
公开(公告)日：2015-03-19
申请号：US14395076
申请日：2012-05-10
申请人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L29/78 , H01L21/266 , H01L29/06 , H01L29/66 , H01L29/16 , H01L29/161
CPC分类号： H01L29/785 , H01L21/26586 , H01L21/266 , H01L21/84 , H01L27/1203 , H01L29/0649 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/6656 , H01L29/66795 , H01L29/7842 , H01L29/7843 , H01L29/7848 , H01L29/7849
摘要： The present invention provides a semiconductor structure comprising: a semiconductor base located on an insulating layer, wherein the insulating layer is located on a semiconductor substrate; source/drain regions, which are in contact with first sidewalls of the semiconductor base opposite to each other; gates located on second sidewalls of the semiconductor base opposite to each other; an insulating via located on the insulating layer and embedded into the semiconductor base; and an epitaxial layer sandwiched between the insulating via and the semiconductor base. The present invention further provides a method for manufacturing a semiconductor structure comprising: forming an insulating layer on a semiconductor substrate; forming a semiconductor base on the insulating layer; forming a void within the semiconductor base, wherein the void exposes the semiconductor substrate; forming an epitaxial layer in the void through selective epitaxy; and forming an insulating via within the void. Short-channel effects are significantly suppressed through forming super-steep retrograde well (SSRW).
摘要翻译：本发明提供一种半导体结构，包括：位于绝缘层上的半导体基底，其中所述绝缘层位于半导体衬底上; 源极/漏极区域，其与半导体基板的彼此相对的第一侧壁接触; 位于半导体基板的彼此相对的第二侧壁上的门; 位于绝缘层上并嵌入到半导体基底中的绝缘通孔; 以及夹在绝缘通孔和半导体基底之间的外延层。本发明还提供一种用于制造半导体结构的方法，包括：在半导体衬底上形成绝缘层; 在绝缘层上形成半导体基底; 在所述半导体基底内形成空隙，其中所述空隙暴露所述半导体衬底; 通过选择性外延在空隙中形成外延层; 并在空隙内形成绝缘通孔。通过形成超陡逆行井（SSRW），短通道效应被显着抑制。

137. 发明申请

US20150076602A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20150076602A1
公开(公告)日：2015-03-19
申请号：US14394802
申请日：2012-05-30
申请人： Huilong Zhu , Haizhou Yin , Zhijiong Luo , Qingqing Liang
发明人： Huilong Zhu , Haizhou Yin , Zhijiong Luo , Qingqing Liang
IPC分类号： H01L29/78 , H01L21/265 , H01L21/324 , H01L29/06 , H01L29/66
CPC分类号： H01L29/7849 , H01L21/265 , H01L21/26506 , H01L21/2652 , H01L21/324 , H01L29/0649 , H01L29/66545 , H01L29/66583 , H01L29/66772 , H01L29/78654
摘要： A method for manufacturing a semiconductor structure, comprises the following steps: providing an SOI substrate and forming a gate structure on the SOI substrate; implanting ions to induce stress in the semiconductor structure by using the gate structure as mask to form a stress-inducing region, which is located under the BOX layer on the SOI substrate on both sides of the gate structure. A semiconductor structure manufactured according to the above method is also disclosed. The semiconductor structure and the method for manufacturing the same disclosed in the present application form on the ground layer a stress-inducing region, which provides favorable stress to the semiconductor device channel and contributes to the improvement of the semiconductor device performance.
摘要翻译：一种制造半导体结构的方法，包括以下步骤：在SOI衬底上提供SOI衬底并形成栅极结构; 通过使用栅极结构作为掩模来注入离子以在半导体结构中引起应力，以形成位于栅极结构两侧的SOI衬底上的BOX层下方的应力诱导区域。还公开了根据上述方法制造的半导体结构。在本申请中公开的半导体结构及其制造方法在地层上形成应力诱导区域，其对半导体器件沟道提供有利的应力，有助于提高半导体器件的性能。

138. 发明授权

US08822334B2 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US08822334B2
公开(公告)日：2014-09-02
申请号：US13380612
申请日：2011-04-18
申请人： Haizhou Yin , Jun Luo , Zhijiong Luo , Huilong Zhu
发明人： Haizhou Yin , Jun Luo , Zhijiong Luo , Huilong Zhu
IPC分类号： H01L21/44 , H01L29/45 , H01L21/285 , H01L29/66
CPC分类号： H01L29/6653 , H01L21/28518 , H01L29/456 , H01L29/66545
摘要： A method for manufacturing a semiconductor structure comprises: providing a substrate (100) on which a dummy gate stack is formed, forming a spacer (240) at sidewalls of the dummy gate stack, and forming a source/drain region (110) and a source/drain extension region (111) at both sides of the dummy gate stack; removing at least part of the spacer (240), to expose at least part of the source/drain extension region (111); forming a contact layer (112) on the source/drain region (110) and the exposed source/drain extension region (111), the contact layer (112) being [made of] one of CoSi2, NiSi and Ni(Pt)Si2-y or combinations thereof, and a thickness of the contact layer (112) being less than 10 nm. Correspondingly, the present invention further provides a semiconductor structure which is beneficial to reducing contact resistance and can maintain excellent performance in a subsequent high temperature process.
摘要翻译：一种用于制造半导体结构的方法，包括：提供其上形成有虚拟栅极堆叠的衬底（100），在所述虚拟栅极堆叠的侧壁处形成间隔物（240），以及形成源/漏区（110）和源极/漏极延伸区域（111）; 去除所述间隔物（240）的至少一部分，以暴露所述源极/漏极延伸区域（111）的至少一部分; 在源/漏区（110）和暴露的源极/漏极延伸区（111）上形成接触层（112），接触层（112）由CoSi2，NiSi和Ni（Pt）Si2 -y或其组合，并且接触层（112）的厚度小于10nm。相应地，本发明还提供一种半导体结构，该半导体结构有利于降低接触电阻并且可以在随后的高温工艺中保持优异的性能。

139. 发明授权

US08772127B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08772127B2
公开(公告)日：2014-07-08
申请号：US13142591
申请日：2011-01-27
申请人： Haizhou Yin , Huicai Zhong , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huicai Zhong , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L29/772
CPC分类号： H01L29/7846 , H01L21/76224 , H01L29/045 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： The present invention provides a semiconductor device and a method for manufacturing the same. The method for manufacturing the semiconductor device comprises: providing a silicon substrate having a gate stack structure formed thereon and having {100} crystal indices; forming an interlayer dielectric layer coving a top surface of the silicon substrate; forming a first trench in the interlayer dielectric layer and/or in the gate stack structure, the first trench having an extension direction being along crystal direction and perpendicular to that of the gate stack structure; and filling the first trench with a first dielectric layer, wherein the first dielectric layer is a tensile stress dielectric layer. The present invention introduces a tensile stress in the transverse direction of a channel region by using a simple process, which improves the response speed and performance of semiconductor devices.
摘要翻译：本发明提供一种半导体器件及其制造方法。制造半导体器件的方法包括：提供其上形成有栅极叠层结构并具有{100}晶体指数的硅衬底; 形成层叠所述硅衬底的顶表面的层间电介质层; 在所述层间介质层和/或所述栅堆叠结构中形成第一沟槽，所述第一沟槽具有沿着晶体方向并且垂直于所述栅堆叠结构的延伸方向; 以及用第一介电层填充所述第一沟槽，其中所述第一介电层是拉伸应力介电层。本发明通过使用简单的工艺在沟道区域的横向上引入拉伸应力，这提高了半导体器件的响应速度和性能。

140. 发明授权

US08765540B2 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US08765540B2
公开(公告)日：2014-07-01
申请号：US13697072
申请日：2012-05-16
申请人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L27/092 , H01L29/66
CPC分类号： H01L27/092 , H01L21/76272 , H01L21/76283 , H01L21/76289 , H01L29/0649 , H01L29/0653 , H01L29/0657 , H01L29/1083 , H01L29/66477 , H01L29/78
摘要： The present invention provides a semiconductor structure, which comprises: a substrate, a semiconductor base, a semiconductor auxiliary base layer, a cavity, a gate stack, a sidewall spacer, and a source/drain region, wherein the gate stack is located on the semiconductor base; the sidewall spacer is located on the sidewalls of the gate stack; the source/drain region is embedded in the semiconductor base and is located on both sides of the gate stack; the cavity is embedded in the substrate; the semiconductor base is suspended above the cavity, the thickness of the middle portion of the semiconductor base is greater than the thickness of the two end portions of the semiconductor base in the direction of the length of the gate, and the two end portions of the semiconductor base are connected to the substrate in the direction of the width of the gate; and the semiconductor auxiliary base layer is located on the sidewall of the semiconductor base and has an opposite doping type to that of the source/drain region, and the doping concentration of the semiconductor auxiliary base layer is higher than that of the semiconductor base. Correspondingly, the present invention also provides a method for manufacturing a semiconductor structure. According to the present invention, the short channel effect can be suppressed, and the device performance can be improved, thereby reducing the cost and simplifying the process.
摘要翻译：本发明提供了一种半导体结构，其包括：基板，半导体基底，半导体辅助基底层，空腔，栅极堆叠，侧壁间隔物和源极/漏极区域，其中栅极堆叠位于半导体基地侧壁间隔件位于栅极叠层的侧壁上; 源极/漏极区域嵌入在半导体基底中并且位于栅极叠层的两侧; 空腔嵌入基板中; 半导体基底悬挂在空腔上方，半导体基底的中间部分的厚度大于半导体基底的两个端部在栅极长度方向上的厚度，而两个端部的厚度半导体基底沿栅极的宽度方向连接到基板; 并且半导体辅助基极层位于半导体基底的侧壁上并且具有与源极/漏极区相反的掺杂型，并且半导体辅助基极层的掺杂浓度高于半导体基底的掺杂浓度。相应地，本发明还提供一种制造半导体结构的方法。根据本发明，可以抑制短通道效应，并且可以提高装置性能，从而降低成本并简化处理。

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