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    • 131. 发明授权
    • Snowboard binding with highback
    • 滑雪板绑定与高背
    • US06467795B1
    • 2002-10-22
    • US09750016
    • 2000-12-29
    • Syuichi HirayamaToshiyuki Tanaka
    • Syuichi HirayamaToshiyuki Tanaka
    • A63C908
    • A63C10/10A63C10/106A63C10/18A63C10/22A63C10/24
    • A snowboard binding is provided that is relatively easy to step-in and step-out of. The snowboard binding preferably has a highback that provides a tight fit between a soft boot and the highback. The snowboard binding has a base plate, a first binding member and a second binding member. The first binding member is coupled to one of the front and rear portions of the base plate. The second binding member is coupled to the other of the front and rear portions of the base plate. The second binding member is coupled to the base plate at a location that is longitudinally spaced from the first binding member. The second binding member includes a catch member movably relative to the base plate and a latch member movable movably relative to the base plate. The latch member is arranged to selectively hold the catch member in a plurality of engagement positions having different heights above the base plate.
    • 提供了滑雪板装订,其相对容易进入和逐出。 滑雪板装订优选地具有在软启动和高背部之间紧密配合的高背。 滑雪板装订具有基板,第一装订构件和第二装订构件。 第一装订构件联接到基板的前部和后部中的一个。 第二装订构件联接到基板的前部和后部中的另一个。 第二装订构件在与第一装订构件纵向间隔开的位置处联接到基板。 第二装订构件包括相对于基板可移动的锁定构件和可相对于基板可移动地移动的闩锁构件。 闩锁构件被布置成选择性地将卡扣构件保持在具有不同高度的基板上方的多个接合位置。
    • 132. 发明授权
    • Nitride-based semiconductor light emitting device and manufacturing method therefor
    • 氮化物系半导体发光元件及其制造方法
    • US06442184B1
    • 2002-08-27
    • US09459471
    • 1999-12-13
    • Hiroyuki OtaAtsushi WatanabeToshiyuki Tanaka
    • Hiroyuki OtaAtsushi WatanabeToshiyuki Tanaka
    • H01S500
    • H01L33/007H01L33/22H01S5/0213H01S5/3202H01S5/32341
    • A semiconductor light emitting device having multi-layer structure of group-3 nitride-based semiconductors is disclosed. The light emitting device has lower density of threading dislocation extending from a boundary of a crystal substrate through the multi-layer structure, thereby obtaining good luminescence characteristics. The nitride semiconductor light emitting device has the multi-layer structure. The multi-layer structure comprises a first crystal layer containing substantially pyramidal crystal grains, each of grains has a crystal face non-parallel to a surface of the substrate, and the pyramidal crystal grains are distributed at random like islands. The structure further comprises a second crystal layer formed on the first crystal layer with a compound having a different lattice constant from that of the first crystal layer. The second crystal layer smoothes a surface of the first crystal layer parallel to the surface of the substrate.
    • 公开了一种具有III族氮化物基半导体的多层结构的半导体发光器件。 发光器件具有从晶体衬底的边界通过多层结构延伸的穿透位错的较低密度,从而获得良好的发光特性。 氮化物半导体发光器件具有多层结构。 多层结构包括含有大致锥形晶粒的第一晶体层,每个晶粒具有不平行于衬底表面的晶面,并且金字塔形晶粒以岛状随机分布。 该结构还包括在第一晶体层上形成具有与第一晶体层不同的晶格常数的化合物的第二晶体层。 第二晶体层使平行于衬底表面的第一晶体层的表面平滑。
    • 133. 发明授权
    • Charge pump circuit and PLL circuit using the same
    • 电荷泵电路和PLL电路使用相同
    • US06407619B1
    • 2002-06-18
    • US09661303
    • 2000-09-13
    • Toshiyuki Tanaka
    • Toshiyuki Tanaka
    • H02J1982
    • H03L7/0895
    • A charge pump circuit which can improve the C/N ratio of a PLL circuit and can prevent dead bands is provided. The charge pump circuit comprises a first current mirror circuit including a first reference current path and a first output current path, and a second current mirror circuit including a second reference current path and a second output current path. When this phase comparison signal showing a lagging phase is low, the first current mirror circuit puts a first output transistor provided within the first output current path in a cutoff state that is nearly turned on. On the other hand, when this phase comparison signal is high, the first current mirror circuit makes the first output transistor turn on immediately, thus the rise time of the charge pump current is shortened. When this phase comparison signal showing a leading phase is low, the second current mirror circuit puts a second output transistor provided within the second output current path in a cutoff state that is nearly turned on. On the other hand, when this phase comparison signal is high, the second current mirror circuit makes the second output transistor turn on immediately, thus the rise time of the charge pump current is shortened.
    • 提供了能够提高PLL电路的C / N比并能够防止死区的电荷泵电路。 电荷泵电路包括包括第一参考电流路径和第一输出电流路径的第一电流镜电路和包括第二参考电流路径和第二输出电流路径的第二电流镜电路。 当显示滞后相位的该相位比较信号为低时,第一电流镜电路将设置在第一输出电流路径内的第一输出晶体管置于几乎导通的截止状态。 另一方面,当该相位比较信号为高时,第一电流镜电路使第一输出晶体管立即导通,从而缩短了电荷泵电流的上升时间。 当显示超前相位的相位比较信号为低时,第二电流镜电路将设置在第二输出电流路径内的第二输出晶体管置于接近导通的截止状态。 另一方面,当该相位比较信号为高时,第二电流镜电路使第二输出晶体管立即导通,从而缩短了电荷泵电流的上升时间。
    • 134. 发明授权
    • Editing apparatus
    • 编辑装置
    • US06314231B1
    • 2001-11-06
    • US09206520
    • 1998-12-07
    • Toshiyuki TanakaSojiro KizuTakashi TabuchiAkira KikuchiYutaka Saito
    • Toshiyuki TanakaSojiro KizuTakashi TabuchiAkira KikuchiYutaka Saito
    • H04N593
    • H04N5/262G11B27/024G11B27/028G11B27/031G11B27/032G11B27/34G11B2220/90H04H60/04
    • An editing apparatus forms an output video signal by effecting an editing processing on a plurality of video signals such as first and second input video signals. There are generated first and second video clips representing a starting position and an ending position set to the first input video signal, third and fourth video clips representing a starting position and an ending position set to a second input video signal, and fifth and sixth video clips representing a starting position and an ending position set to an output video signal. The first, second, third and fourth video clips are displayed on the basis of time information attached to each video clip so as to express a positional relationship of the first, second, third and fourth video clips on a time axis. Also, the fifth and sixth video clips are displayed.
    • 编辑装置通过对诸如第一和第二输入视频信号的多个视频信号进行编辑处理来形成输出视频信号。 产生代表第一输入视频信号的开始位置和结束位置的第一和第二视频剪辑,表示设置到第二输入视频信号的开始位置和结束位置的第三和第四视频剪辑,以及第五和第六视频 剪辑表示设置为输出视频信号的开始位置和结束位置。 基于附加到每个视频剪辑的时间信息来显示第一,第二,第三和第四视频剪辑,以便在时间轴上表达第一,第二,第三和第四视频剪辑的位置关系。 此外,显示第五和第六视频剪辑。
    • 135. 发明授权
    • Picture processor and picture editing system
    • 图片处理器和图片编辑系统
    • US06215949B1
    • 2001-04-10
    • US08592380
    • 1996-10-15
    • Toshiyuki Tanaka
    • Toshiyuki Tanaka
    • H04N593
    • G06T1/20G11B27/028G11B27/031G11B27/032G11B27/034G11B27/10G11B27/34G11B2220/61G11B2220/90
    • A time-divided multi-task image processing apparatus conducts each task in a time slice. This image processing apparatus correlates a first identification code to the picture information sequentially input and stores it in memory means for a specified period. Then, when the second identification code having any value is given from an external device which generates the second identification code synchronized with the first identification code, the image processing apparatus searches the first identification code which has the nearest value to that of the second identification code and which satisfies a specified relation between the value of the second identification code by second control means, and then reads out the picture information which is combined with the first identification code from the memory means.
    • 时分多任务图像处理装置在时间片中进行每个任务。 该图像处理装置将第一识别码与依次输入的图像信息相关联,并将其存储在存储装置中一段指定的周期。 然后,当从产生与第一识别码同步的第二识别码的外部装置给出具有任何值的第二识别码时,图像处理装置搜索具有与第二识别码的最接近的值最接近的第一识别码 并且通过第二控制装置满足第二识别码的值之间的指定关系,然后从存储装置读出与第一识别码组合的图像信息。
    • 136. 发明授权
    • Editing apparatus
    • 编辑装置
    • US6052151A
    • 2000-04-18
    • US907369
    • 1997-08-07
    • Toshiyuki Tanaka
    • Toshiyuki Tanaka
    • G11B27/031H04N5/262G06F13/00
    • G11B27/031H04N5/262
    • A main CPU 11 of a Main CPU Module 10 simultaneously sends out control information to respective Sub CPUs 22, 32, . . . , n2, . . . of plural Sub CPU Modules 20, 30, . . . , n0, . . . by broadcast buses 201, 202 of a system bus 200. In the case where control information from the Main CPU sent out through the broadcast buses 201, 202 is control information with respect to corresponding one of Sub CPU Devices 23, 33, . . . , n3, . . . , each Sub CPU carries out operation control of the Sub CPU device on the basis of the corresponding control information. Thus, the Main CPU is not required to finely control processing inherent in the Sub CPU Devices or timings thereof, etc. Also in the case where new Sub CPU Device is supplemented, or Sub CPU Device of different timing is assembled or incorporated into the apparatus, modification of the control program of the Main CPU can be held down to the minimum level. In addition, control program is supplemented to Sub CPU corresponding to Sub CPU Device to be supplemented, thereby making it possible to cope with implementation of such supplement. This editing apparatus can smoothly carry out extension of the apparatus and/or enlargement of scale without lowering performance of the apparatus.
    • 主CPU模块10的主CPU11同时向各个子CPU 22,32发出控制信息。 。 。 ,n2,。 。 。 的多个子CPU模块20,30。 。 。 ,n0,。 。 。 通过广播总线201,202发出的来自主CPU的控制信息是关于子CPU设备23,33中的相应一个的控制信息的情况。 。 。 ,n3,。 。 。 每个子CPU基于相应的控制信息执行子CPU设备的操作控制。 因此,不需要主CPU来精细地控制子CPU设备中固有的处理或其定时等。另外在补充新的Sub CPU设备的情况下,或者将不同时序的Sub CPU设备组装或并入设备中 ,可以将主CPU的控制程序的修改降至最低。 另外,辅助子控制器对应的子CPU的控制程序被补充,从而可以应付这种补充的实现。 该编辑装置可以平滑地进行装置的扩展和/或扩大刻度而不降低装置的性能。
    • 138. 发明授权
    • Objective lens driving apparatus and method including visco-elastic
support for a magnetic circuit which allows translation of the magnetic
circuit without pivoting or rotating there of
    • 物镜驱动装置和方法包括用于磁路的粘弹性支撑,其允许磁路的平移而不枢转或旋转
    • US5719834A
    • 1998-02-17
    • US671510
    • 1996-06-27
    • Masayasu FutagawaKeiji SakaiToshiyuki Tanaka
    • Masayasu FutagawaKeiji SakaiToshiyuki Tanaka
    • G11B7/09G11B7/085
    • G11B7/0932G11B7/0935
    • An objective lens driving apparatus includes a base, an objective lens for converging an optical beam on an optical disc while the optical disc is rotating, and a holding member for holding the objective lens. A first supporting mechanism elastically supports the holding member on the base in such a manner as to allow the holding member to be translated in a focusing direction which is substantially perpendicular to a surface of the optical disc and in a tracking direction which is substantially perpendicular to the focusing direction and parallel to a radial direction of the optical disc. A moving mechanism including a coil and a magnetic circuit for translates the holding member in the focusing direction and the tracking direction by a driving force generated by the coil and the magnetic circuit. A second supporting mechanism for visco-elastically supports the magnetic circuit on the base in such a manner as to translate the magnetic circuit in the focusing direction. The magnetic circuit is translated in an opposite direction to the translation direction of the holding member by a driving force acting oppositely to the driving force for translating the holding member in the focusing direction.
    • 物镜驱动装置包括基座,用于在光盘旋转时将光束会聚在光盘上的物镜,以及用于保持物镜的保持构件。 第一支撑机构以这样一种方式弹性地支撑保持构件,使得保持构件能够在基本上垂直于光盘的表面的聚焦方向上平移,并且在跟踪方向上基本上垂直于 聚焦方向并平行于光盘的径向方向。 一种移动机构,包括线圈和磁路,用于通过线圈和磁路产生的驱动力使保持构件在聚焦方向和跟踪方向上平移。 第二支撑机构用于以使得磁路在聚焦方向平移的方式在基座上弹性地支撑磁路。 通过与用于在聚焦方向上平移保持构件的驱动力相反的驱动力,磁路沿与保持构件的平移方向相反的方向平移。
    • 139. 发明授权
    • Efficient interrupt control apparatus with a common interrupt control
program and control method thereof
    • 具有共同中断控制程序的高效中断控制装置及其控制方法
    • US5568643A
    • 1996-10-22
    • US454240
    • 1995-06-12
    • Toshiyuki Tanaka
    • Toshiyuki Tanaka
    • G06F9/48G06F13/24G06F9/46
    • G06F9/4812G06F13/24
    • An interrupt control apparatus using an RISC etc. for performing the same interrupt processing at a plurality of interrupt terminals, which interrupt control apparatus is able to perform interrupt processing corresponding to a plurality of interrupts efficiently. In this interrupt control apparatus 1, interrupt processing control data corresponding to the interrupt signal holding circuits 26a.sub.1 to 26a.sub.n are stored in the form of a table in the memory circuit 34. A program for performing common interrupt control processing when any of the interrupt signals is detected and interrupt processing programs corresponding to the plurality of interrupt signals are stored in the memory circuit 34 in a system callable manner. When the interrupt control apparatus 12 of the RISC processor 10 detects an interrupt signal, the common interrupt control program specifies the interrupt signal input to the interrupt signal holding circuit 26a.sub.1 to 26a.sub.n and activates the corresponding interrupt processing program.
    • PCT No.PCT / JP94 / 01690 Sec。 371日期:1995年6月12日 102(e)1995年6月12日PCT PCT 1994年10月11日PCT公布。 WO95 / 10806 PCT出版物 日期1995年4月20日使用RISC等的中断控制装置在多个中断端子执行相同的中断处理,该中断控制装置能够有效地执行与多个中断相对应的中断处理。 在该中断控制装置1中,与中断信号保持电路26a1〜26an对应的中断处理控制数据以表的形式存储在存储器电路34中。当任何中断信号为 对应于多个中断信号的检测和中断处理程序以系统可调用方式存储在存储器电路34中。 当RISC处理器10的中断控制装置12检测到中断信号时,公共中断控制程序指定输入到中断信号保持电路26a1至26an的中断信号并激活相应的中断处理程序。