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131. 发明申请

US20140019693A1 PARALLEL PROCESSING OF A SINGLE DATA BUFFER 审中-公开
标题翻译：单个数据缓冲器的并行处理
公开(公告)号：US20140019693A1
公开(公告)日：2014-01-16
申请号：US13631761
申请日：2012-09-28
申请人： Sean M. Gulley , Wajdi K. Feghali , Vinodh Gopal , James D. Guilford , Gilbert M. Wolrich , Kirk S. Yap
发明人： Sean M. Gulley , Wajdi K. Feghali , Vinodh Gopal , James D. Guilford , Gilbert M. Wolrich , Kirk S. Yap
IPC分类号： G06F12/00
CPC分类号： G06F5/06 , G06F21/64 , H04L9/0643 , H04L9/3236 , H04L2209/12 , H04L2209/20
摘要： Technologies for executing a serial data processing algorithm on a single variable length data buffer includes streaming segments of the buffer into a data register, executing the algorithm on each of the segments in parallel, and combining the results of executing the algorithm on each of the segments to form the output of the serial data processing algorithm.
摘要翻译：用于在单个可变长度数据缓冲器上执行串行数据处理算法的技术包括缓冲器的流片段到数据寄存器中，并行地对每个片段执行算法，并且在每个片段上合并执行算法的结果形成串行数据处理算法的输出。

132. 发明申请

US20140016774A1 INSTRUCTIONS TO PERFORM GROESTL HASHING 有权
标题翻译：执行GROESTL HASHING的说明
公开(公告)号：US20140016774A1
公开(公告)日：2014-01-16
申请号：US13992461
申请日：2011-12-22
申请人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal , James D. Guilford , Erdinc Ozturk , Sean M. Gulley , Wajdi K. Feghali , Martin G. Dixon
发明人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal , James D. Guilford , Erdinc Ozturk , Sean M. Gulley , Wajdi K. Feghali , Martin G. Dixon
IPC分类号： H04L9/28
CPC分类号： H04L9/28 , G06F9/30018 , G06F9/30036 , G06F9/30109 , G06F13/14 , H04L9/0631 , H04L9/0643
摘要： A method is described. The method includes executing an instruction to perform one or more Galois Field (GF) multiply by 2 operations on a state matrix and executing an instruction to combine results of the one or more GF multiply by 2 operations with exclusive or (XOR) functions to generate a result matrix.
摘要翻译：描述了一种方法。该方法包括执行在状态矩阵上乘以2次操作的一个或多个伽罗瓦域（GF）的指令，并且执行将所述一个或多个GF乘以2个运算的结果与异或（XOR）函数相结合的指令，以产生一个结果矩阵。

133. 发明授权

US08340281B2 Efficient method and apparatus for modular inverses 有权
标题翻译：模块化逆变器的高效方法和装置
公开(公告)号：US08340281B2
公开(公告)日：2012-12-25
申请号：US12291318
申请日：2008-11-07
申请人： Pierre Laurent , Vinodh Gopal
发明人： Pierre Laurent , Vinodh Gopal
IPC分类号： H04K1/00
CPC分类号： G06F7/727 , G06F7/721 , H04L9/3093 , H04N7/1675 , H04N21/2383
摘要： Methods and apparatus are described for computing modular inverses of odd input values modulo 2N (or modulo xN, for example in some Galois field) to perform a modular multiplication in cryptographic processing systems. In one embodiment an approximation is computed having 2k bits of the modular inverse of the odd input value without multiplications, for example using a binary extended Euclidean algorithm. A sequence of log2N−k Newton-Raphson or similarly quadratically convergent iterations are applied to the approximation using an extended precision multiplier to generate the modular inverse of the odd input value modulo 2N (or modulo xN), the modular inverse having up to N bits of precision. The modular inverse of the odd input value is then used in a modular multiplication to perform cryptographic operations and/or cyclic redundancy checks on communication data.
摘要翻译：描述的方法和装置用于计算模2N的奇数输入值（或者例如在一些伽罗瓦域中的模xN）以在密码处理系统中执行模乘。在一个实施例中，计算具有奇数输入值的模数逆的2k位的近似，而不进行乘法，例如使用二进制扩展的欧几里德算法。使用扩展精度乘数将log2N-k Newton-Raphson或类似的二次收敛迭代的序列应用于近似，以产生模2N（或模xN）的奇数输入值的模逆，该模逆向具有多达N位的精度。然后，以模数乘法将奇数输入值的模数反向用于对通信数据执行加密操作和/或循环冗余校验。

134. 发明授权

US08325069B2 System, method, and apparatus for a scalable processor architecture for a variety of string processing applications 有权
标题翻译：用于各种字符串处理应用的可扩展处理器架构的系统，方法和装置
公开(公告)号：US08325069B2
公开(公告)日：2012-12-04
申请号：US12645392
申请日：2009-12-22
申请人： Vinodh Gopal , Gilbert M. Wolrich , Christopher F. Clark , Wadji K. Feghali
发明人： Vinodh Gopal , Gilbert M. Wolrich , Christopher F. Clark , Wadji K. Feghali
IPC分类号： H03M7/34 , H03M7/38
CPC分类号： H03M7/40 , H03M7/3084 , H03M13/09
摘要： Systems, methods, and apparatus for a scalable processor architecture for variety of string processing application are described. In one such apparatus, n input first in, first out (FIFO) buffer stores an input stream. A plurality of memory banks store data from the input stream. A re-configurable controller processes the input stream. And an output FIFO buffer stores the processed input stream.
摘要翻译：描述了用于各种字符串处理应用的可扩展处理器架构的系统，方法和装置。在一个这样的装置中，n输入先进先出（FIFO）缓冲器存储输入流。多个存储器组从输入流存储数据。可重新配置的控制器处理输入流。并且输出FIFO缓冲器存储经处理的输入流。

135. 发明申请

US20110153997A1 Bit Range Isolation Instructions, Methods, and Apparatus 有权
标题翻译：位范围隔离说明，方法和设备
公开(公告)号：US20110153997A1
公开(公告)日：2011-06-23
申请号：US12645307
申请日：2009-12-22
申请人： Maxim Loktyukhin , Eric W. Mahurin , Bret L. Toll , Martin G. Dixon , Sean P. Mirkes , David L. Kreitzer , El Moustapha Ould-Ahmed-Vall , Vinodh Gopal
发明人： Maxim Loktyukhin , Eric W. Mahurin , Bret L. Toll , Martin G. Dixon , Sean P. Mirkes , David L. Kreitzer , El Moustapha Ould-Ahmed-Vall , Vinodh Gopal
IPC分类号： G06F9/305 , G06F9/30 , G06F12/02
CPC分类号： G06F9/30145 , G06F9/30018 , G06F9/30029 , G06F9/30094 , G06F9/3802
摘要： Receiving an instruction indicating a source operand and a destination operand. Storing a result in the destination operand in response to the instruction. The result operand may have: (1) first range of bits having a first end explicitly specified by the instruction in which each bit is identical in value to a bit of the source operand in a corresponding position; and (2) second range of bits that all have a same value regardless of values of bits of the source operand in corresponding positions. Execution of instruction may complete without moving the first range of the result relative to the bits of identical value in the corresponding positions of the source operand, regardless of the location of the first range of bits in the result. Execution units to execute such instructions, computer systems having processors to execute such instructions, and machine-readable medium storing such an instruction are also disclosed.
摘要翻译：接收指示源操作数和目标操作数的指令。将结果存储在目标操作数中以响应指令。结果操作数可以具有：（1）具有第一端的第一范围，其中每个位在相应位置中的每个位与源操作数的位相同的指令明确地指定; 和（2）与相应位置中的源操作数的位的值无关的所有位都具有相同值的第二范围。不管移动第一范围的结果相对于源操作数的相应位置中相同值的位，执行指令都可以完成，而不考虑结果中第一个位的位置。还公开了执行这些指令的执行单元，具有执行这种指令的处理器的计算机系统以及存储这种指令的机器可读介质。

136. 发明申请

US20090019342A1 Determining a Message Residue 有权
标题翻译：确定消息残差
公开(公告)号：US20090019342A1
公开(公告)日：2009-01-15
申请号：US11777538
申请日：2007-07-13
申请人： Shay Gueron , Vinodh Gopal , Wajdi K. Feghali , Gilbert M. Wolrich
发明人： Shay Gueron , Vinodh Gopal , Wajdi K. Feghali , Gilbert M. Wolrich
IPC分类号： H03M13/15
CPC分类号： H03M13/091
摘要： A technique of determining a message residue includes accessing a message and simultaneously determining a set of modular remainders with respect to a polynomial for different respective segments of the message. The technique also includes determining a modular remainder with respect to the polynomial for the message based on the set of modular remainders and a set of constants determined prior to accessing the message. The modular remainder with respect to the polynomial for the message is stored in a memory.
摘要翻译：确定消息残差的技术包括访问消息并且同时确定关于消息的不同相应段的多项式的一组模块余数。该技术还包括基于模块余数的集合和在访问消息之前确定的一组常数来确定关于消息的多项式的模块余数。相对于消息的多项式的模数余数存储在存储器中。

137. 发明申请

US20080159526A1 Architecture and instruction set for implementing advanced encryption standard (AES) 有权
标题翻译：实现高级加密标准（AES）的体系结构和指令集
公开(公告)号：US20080159526A1
公开(公告)日：2008-07-03
申请号：US11648434
申请日：2006-12-28
申请人： Shay Gueron , Wajdi K. Feghali , Vinodh Gopal
发明人： Shay Gueron , Wajdi K. Feghali , Vinodh Gopal
IPC分类号： H04L9/28
CPC分类号： H04L9/0631 , G06F9/30007 , G06F21/602 , H04L9/14 , H04L2209/24
摘要： A flexible aes instruction for a general purpose processor is provided that performs aes encryption or decryption using n rounds, where n includes the standard aes set of rounds {10, 12, 14}. A parameter is provided to allow the type of aes round to be selected, that is, whether it is a “last round”. In addition to standard aes, the flexible aes instruction allows an AES-like cipher with 20 rounds to be specified or a “one round” pass.
摘要翻译：提供了一种用于通用处理器的灵活的aes指令，其使用n次循环执行aes加密或解密，其中n包括标准的一组轮{10,12,14}。提供了一个参数，以允许选择一轮的类型，即是否是“最后一轮”。除了标准aes之外，灵活的aes指令允许指定具有20发的AES类密码或“一轮”通过。

138. 发明申请

US20080019512A1 Accelerating diffie-hellman key-exchange protocol with zero-biased exponent windowing 有权
标题翻译：用零偏置指数窗口加速diffie-hellman密钥交换协议
公开(公告)号：US20080019512A1
公开(公告)日：2008-01-24
申请号：US11480153
申请日：2006-06-29
申请人： Shay Gueron , Vinodh Gopal
发明人： Shay Gueron , Vinodh Gopal
IPC分类号： H04L9/00
CPC分类号： H04L9/088 , H04L9/0841
摘要： A method for improving performance in exponentiation algorithms for encryption programs such as the Diffie-Hellman key-exchange protocol. The program determines if a standard exponentiation algorithm or an algorithm optimized for reduced memory are optimal for a given circumstance. The optimized algorithms may use zero-biased exponents to minimize the number of precomputed vectors needed and the number of multiplication operations required.
摘要翻译：一种用于提高加密程序（如Diffie-Hellman密钥交换协议）的求幂算法中的性能的方法。该程序确定对于给定的情况，标准求幂算法还是针对减少的存储器优化的算法是最优的。优化的算法可以使用零偏置指数来最小化所需的预计算向量的数量和所需的乘法运算的数量。

139. 发明申请

US20080002825A1 Method and a system for a quick verification rabin signature scheme 失效
标题翻译：用于快速验证rabin签名方案的方法和系统
公开(公告)号：US20080002825A1
公开(公告)日：2008-01-03
申请号：US11479100
申请日：2006-06-30
申请人： Shay Gueron , Vinodh Gopal
发明人： Shay Gueron , Vinodh Gopal
IPC分类号： H04L9/30
CPC分类号： H04L9/302 , H04L9/3249
摘要： A method and a system to perform a Quick Verification of a Rabin Signature (QVRS) is provided. In one embodiment, the signing party generates a Rabin signature S of an original message M using a public key N in the Rabin signature generating formula M=S2 mod N. In one embodiment, the signing party also generates a value q according to the formula q=floor(S2/N). In one embodiment, the signing party sends the original message M, the signature S, the public key N and the value q to the verifying party. In one embodiment, the verifying party verifies the integrity of the message M using the signature S, the public key N and the value q and the test equation M=S2−qN.
摘要翻译：提供了一种执行拉宾签名快速验证（QVRS）的方法和系统。在一个实施例中，签名方使用Rabin签名生成公式M = S＆lt; 2＆gt; mod N中的公共密钥N来生成原始消息M的拉宾签名S.在一个实施例中，签约方也根据公式q = floor（S ^{2 / N）生成值q。在一个实施例中，签名方向验证方发送原始消息M，签名S，公钥N和值q。在一个实施例中，验证方使用签名S，公开密钥N和值q以及测试方程M = S 2 -Q N验证消息M的完整性。}

140. 发明申请

US20200266995A1 MANAGING STATE IN ACCELERATORS 审中-公开
公开(公告)号：US20200266995A1
公开(公告)日：2020-08-20
申请号：US16865492
申请日：2020-05-04
申请人： Vinodh Gopal
发明人： Vinodh Gopal
IPC分类号： H04L9/32
摘要： Methods and apparatus for managing state in accelerators. An accelerator performs processing operations on a data chunk relating to a job submitted to the accelerator. During or following processing the data chunk, the accelerator generates state information corresponding to its current state and stores the state information or, optionally, the accelerator state information is obtained and stored by privileged software. In connection with continued processing of the current data chunk or a next job and next data chunk, the accelerator accesses previously stored state information identified by the job and validates the state information was generated by itself, another accelerator, or privileged software. Valid state information is then reloaded to restore the state of the accelerator/process state, and processing continues. The chunk processing, accelerator state store, validation, and restore operations are repeated to process subsequent jobs. An accelerator and/or privileged software may use a MAC (Message Authentication Code) algorithm to generate a MAC over a message comprising the accelerator state information. The MAC is then used to validate previously stored state information.

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