专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

131. 发明授权

US07816664B2 Defect reduction by oxidation of silicon 有权
标题翻译：通过氧化硅来减少缺陷
公开(公告)号：US07816664B2
公开(公告)日：2010-10-19
申请号：US12139080
申请日：2008-06-13
申请人： Stephen W. Bedell , Huajie Chen , Anthony G. Domenicucci , Keith E. Fogel , Devendra K. Sadana
发明人： Stephen W. Bedell , Huajie Chen , Anthony G. Domenicucci , Keith E. Fogel , Devendra K. Sadana
IPC分类号： H01L29/06
CPC分类号： H01L21/7624 , Y10S438/933 , Y10T428/12674
摘要： A high-quality, substantially relaxed SiGe-on-insulator substrate material which may be used as a template for strained Si is described. The substantially relaxed SiGe-on-insulator substrate includes a Si-containing substrate, an insulating region that is resistant to Ge diffusion present atop the Si-containing substrate, and a substantially relaxed SiGe layer present atop the insulating region. The insulating region includes an upper region that is comprised of a thermal oxide and the substantially relaxed SiGe layer has a thickness of about 2000 nm or less.
摘要翻译：描述了可用作应变Si的模板的高质量，基本上松弛的绝缘体上硅衬底材料。基本上松弛的绝缘体上硅衬底包括含硅衬底，在含Si衬底顶部存在耐Ge扩散的绝缘区域和存在于绝缘区域顶部的基本弛豫的SiGe层。绝缘区域包括由热氧化物组成的上部区域，并且基本上松弛的SiGe层具有约2000nm或更小的厚度。

132. 发明申请

US20100261319A1 N-type carrier enhancement in semiconductors 有权
标题翻译：半导体中的N型载流子增强
公开(公告)号：US20100261319A1
公开(公告)日：2010-10-14
申请号：US12420258
申请日：2009-04-08
申请人： Jee Hwan Kim , Stephen W. Bedell , Siegfried Maurer , Devendra K. Sadana
发明人： Jee Hwan Kim , Stephen W. Bedell , Siegfried Maurer , Devendra K. Sadana
IPC分类号： H01L21/265 , H01L21/20 , H01L21/335
CPC分类号： H01L21/26513 , H01L29/165 , H01L29/167 , H01L29/66636 , Y10S438/919
摘要： A method for generating n-type carriers in a semiconductor is disclosed. The method includes supplying a semiconductor having an atomic radius. Implanting an n-type dopant species into the semiconductor, which n-type dopant species has a dopant atomic radius. Implanting a compensating species into the semiconductor, which compensating species has a compensating atomic radius. Selecting the n-type dopant species and the compensating species in such manner that the size of the semiconductor atomic radius is inbetween the dopant atomic radius and the compensating atomic radius. A further method is disclosed for generating n-type carriers in germanium (Ge). The method includes setting a target concentration for the carriers, implanting a dose of an n-type dopant species into the Ge, and selecting the dose to correspond to a fraction of the target carrier concentration. Thermal annealing the Ge in such manner as to activate the n-type dopant species and to repair a least a portion of the implantation damage. Repeating the implantation and the thermal annealing until the target n-type carrier concentration has been reached.
摘要翻译：公开了一种在半导体中产生n型载流子的方法。该方法包括提供具有原子半径的半导体。将n型掺杂物种植入半导体，其中n型掺杂剂物质具有掺杂剂原子半径。将补偿物种植入到半导体中，补偿物质具有补偿原子半径。以使得半导体原子半径的尺寸在掺杂剂原子半径和补偿原子半径之间的方式选择n型掺杂物种类和补偿种类。公开了用于在锗（Ge）中生成n型载流子的另一种方法。该方法包括设定载体的目标浓度，将一定剂量的n型掺杂剂物质注入到Ge中，并选择与目标载体浓度分数相对应的剂量。对Ge进行热退火，以激活n型掺杂物种类并修复至少一部分注入损伤。重复注入和热退火直到目标n型载流子浓度达到。

133. 发明授权

US07785982B2 Structures containing electrodeposited germanium and methods for their fabrication 失效
标题翻译：含有电沉积锗的结构及其制造方法
公开(公告)号：US07785982B2
公开(公告)日：2010-08-31
申请号：US11620224
申请日：2007-01-05
申请人： Stephen W. Bedell , Hariklia Deligianni , Qiang Huang , Lubomyr T. Romankiw , Devendra K. Sadana , Katherine L. Saenger
发明人： Stephen W. Bedell , Hariklia Deligianni , Qiang Huang , Lubomyr T. Romankiw , Devendra K. Sadana , Katherine L. Saenger
IPC分类号： H01L21/76
CPC分类号： H01L21/823807 , H01L21/0237 , H01L21/02532 , H01L21/02628 , H01L21/02636 , H01L21/02639 , H01L21/28255 , H01L29/1054 , H01L29/78
摘要： Methods for electrodepositing germanium on various semiconductor substrates such as Si, Ge, SiGe, and GaAs are provided. The electrodeposited germanium can be formed as a blanket or patterned film, and may be crystallized by solid phase epitaxy to the orientation of the underlying semiconductor substrate by subsequent annealing. These plated germanium layers may be used as the channel regions of high-mobility channel field effect transistors (FETs) in complementary metal oxide semiconductor (CMOS) circuits.
摘要翻译：提供了在诸如Si，Ge，SiGe和GaAs的各种半导体衬底上电沉积锗的方法。电沉积锗可以形成为覆盖或图案化的膜，并且可以通过后续退火使固相外延结晶到下面的半导体衬底的取向。这些电镀锗层可以用作互补金属氧化物半导体（CMOS）电路中的高迁移率沟道场效应晶体管（FET）的沟道区。

134. 发明申请

US20080246019A1 DEFECT REDUCTION BY OXIDATION OF SILICON 有权
标题翻译：通过氧化硅减少缺陷
公开(公告)号：US20080246019A1
公开(公告)日：2008-10-09
申请号：US12139080
申请日：2008-06-13
申请人： Stephen W. Bedell , Huajie Chen , Anthony G. Domenicucci , Keith E. Fogel , Devendra K. Sadana
发明人： Stephen W. Bedell , Huajie Chen , Anthony G. Domenicucci , Keith E. Fogel , Devendra K. Sadana
IPC分类号： H01L29/15 , H01L29/165
CPC分类号： H01L21/7624 , Y10S438/933 , Y10T428/12674
摘要： A method of fabricating high-quality, substantially relaxed SiGe-on-insulator substrate materials which may be used as a template for strained Si is described. A silicon-on-insulator substrate with a very thin top Si layer is used as a template for compressively strained SiGe growth. Upon relaxation of the SiGe layer at a sufficient temperature, the nature of the dislocation motion is such that the strain-relieving defects move downward into the thin Si layer when the buried oxide behaves semi-viscously. The thin Si layer is consumed by oxidation of the buried oxide/thin Si interface. This can be accomplished by using internal oxidation at high temperatures. In this way the role of the original thin Si layer is to act as a sacrificial defect sink during relaxation of the SiGe alloy that can later be consumed using internal oxidation.
摘要翻译：描述了可以用作应变Si的模板的制造高质量，基本上松弛的绝缘体上硅衬底材料的方法。使用具有非常薄的顶部Si层的绝缘体上硅衬底作为压缩应变SiGe生长的模板。当SiGe层在足够的温度下弛豫时，位错运动的性质使得当埋入的氧化物半粘着时，应变消除缺陷向下移动到薄的Si层中。薄Si层被掩埋氧化物/薄Si界面的氧化所消耗。这可以通过在高温下使用内部氧化来实现。以这种方式，原始薄Si层的作用是在SiGe合金的弛豫期间用作牺牲缺陷陷阱，SiGe合金随后可以使用内部氧化来消耗。

135. 发明授权

US07247546B2 Method of forming strained silicon materials with improved thermal conductivity 有权
标题翻译：形成具有改善导热性的应变硅材料的方法
公开(公告)号：US07247546B2
公开(公告)日：2007-07-24
申请号：US10710826
申请日：2004-08-05
申请人： Stephen W. Bedell , Huajie Chen , Keith Fogel , Ryan M. Mitchell , Devendra K. Sadana
发明人： Stephen W. Bedell , Huajie Chen , Keith Fogel , Ryan M. Mitchell , Devendra K. Sadana
IPC分类号： H01L21/20 , H01L21/36 , H01L31/117
CPC分类号： H01L29/1054 , H01L21/02381 , H01L21/0245 , H01L21/02507 , H01L21/02532
摘要： A method is disclosed for forming a strained Si layer on SiGe, where the SiGe layer has improved thermal conductivity. A first layer of Si or Ge is deposited on a substrate in a first depositing step; a second layer of the other element is deposited on the first layer in a second depositing step; and the first and second depositing steps are repeated so as to form a combined SiGe layer having a plurality of Si layers and a plurality of Ge layers. The respective thicknesses of the Si layers and Ge layers are in accordance with a desired composition ratio of the combined SiGe layer (so that a 1:1 ratio typically is realized with Si and Ge layers each about 10 Å thick). The combined SiGe layer is characterized as a digital alloy of Si and Ge having a thermal conductivity greater than that of a random alloy of Si and Ge. This method may further include the step of depositing a Si layer on the combined SiGe layer; the combined SiGe layer is characterized as a relaxed SiGe layer, and the Si layer is a strained Si layer. For still greater thermal conductivity in the SiGe layer, the first layer and second layer may be deposited so that each layer consists essentially of a single isotope.
摘要翻译：公开了一种在SiGe上形成应变Si层的方法，其中SiGe层具有改善的导热性。在第一沉积步骤中将第一层Si或Ge沉积在衬底上; 另一个元件的第二层在第二沉积步骤中沉积在第一层上; 并且重复第一和第二沉积步骤以形成具有多个Si层和多个Ge层的组合SiGe层。 Si层和Ge层的各自的厚度根据组合的SiGe层的期望组成比（使得Si和Ge层的厚度通常为1：1，每个厚度大约为10埃）。组合的SiGe层的特征在于具有大于Si和Ge的随机合金的热导率的Si和Ge的数字合金。该方法还可以包括在组合的SiGe层上沉积Si层的步骤; 组合的SiGe层被表征为弛豫的SiGe层，并且Si层是应变的Si层。对于SiGe层中更高的热导率，可以沉积第一层和第二层，使得每层基本上由单一同位素组成。

136. 发明授权

US07169226B2 Defect reduction by oxidation of silicon 失效
标题翻译：通过氧化硅来减少缺陷
公开(公告)号：US07169226B2
公开(公告)日：2007-01-30
申请号：US10610612
申请日：2003-07-01
申请人： Stephen W. Bedell , Huajie Chen , Anthony G. Domenicucci , Keith E. Fogel , Devendra K. Sadana
发明人： Stephen W. Bedell , Huajie Chen , Anthony G. Domenicucci , Keith E. Fogel , Devendra K. Sadana
IPC分类号： C30B13/00 , H01L21/20
CPC分类号： H01L21/7624 , Y10S438/933 , Y10T428/12674
摘要： A method of fabricating high-quality, substantially relaxed SiGe-on-insulator substrate materials which may be used as a template for strained Si is described. A silicon-on-insulator substrate with a very thin top Si layer is used as a template for compressively strained SiGe growth. Upon relaxation of the SiGe layer at a sufficient temperature, the nature of the dislocation motion is such that the strain-relieving defects move downward into the thin Si layer when the buried oxide behaves semi-viscously. The thin Si layer is consumed by oxidation of the buried oxide/thin Si interface. This can be accomplished by using internal oxidation at high temperatures. In this way the role of the original thin Si layer is to act as a sacrificial defect sink during relaxation of the SiGe alloy that can later be consumed using internal oxidation.
摘要翻译：描述了可以用作应变Si的模板的制造高质量，基本上松弛的绝缘体上硅衬底材料的方法。使用具有非常薄的顶部Si层的绝缘体上硅衬底作为压缩应变SiGe生长的模板。当SiGe层在足够的温度下弛豫时，位错运动的性质使得当埋入的氧化物半粘着时，应变消除缺陷向下移动到薄的Si层中。薄Si层被掩埋氧化物/薄Si界面的氧化所消耗。这可以通过在高温下使用内部氧化来实现。以这种方式，原始薄Si层的作用是在SiGe合金的弛豫期间用作牺牲缺陷陷阱，SiGe合金随后可以使用内部氧化来消耗。

137. 发明授权

US09099596B2 Heterojunction photovoltaic device and fabrication method 有权
标题翻译：异质结光伏器件及其制造方法
公开(公告)号：US09099596B2
公开(公告)日：2015-08-04
申请号：US13194301
申请日：2011-07-29
申请人： Stephen W. Bedell , Keith E. Fogel , Bahman Hekmatshoar-Tabari , Devendra K. Sadana , Ghavam G. Shahidi , Davood Shahrjerdi
发明人： Stephen W. Bedell , Keith E. Fogel , Bahman Hekmatshoar-Tabari , Devendra K. Sadana , Ghavam G. Shahidi , Davood Shahrjerdi
IPC分类号： H01L31/0745 , H01L31/18 , H01L31/0312 , H01L31/0747 , H01L31/0725 , H01L31/078 , H01L31/20
CPC分类号： H01L31/0725 , C23C14/3407 , H01L31/02167 , H01L31/022441 , H01L31/074 , H01L31/0747 , H01L31/078 , H01L31/1808 , H01L31/1812 , H01L31/204 , Y02E10/50 , Y02P70/521
摘要： A photovoltaic device and method include a doped germanium-containing substrate, an emitter contact coupled to the substrate on a first side and a back contact coupled to the substrate on a side opposite the first side. The emitter includes at least one doped layer of an opposite conductivity type as that of the substrate and the back contact includes at least one doped layer of the same conductivity type as that of the substrate. The at least one doped layer of the emitter contact or the at least one doped layer of the back contact is in direct contact with the substrate, and the at least one doped layer of the emitter contact or the back contact includes an n-type material having an electron affinity smaller than that of the substrate, or a p-type material having a hole affinity larger than that of the substrate.
摘要翻译：光伏器件和方法包括掺杂的含锗衬底，在第一侧耦合到衬底的发射极触点和在与第一侧相对的一侧耦合到衬底的后触点。发射极包括与衬底相反的导电类型的至少一个掺杂层，而后接触包括至少一个与衬底相同导电类型的掺杂层。发射极接触的至少一个掺杂层或背接触的至少一个掺杂层与衬底直接接触，并且发射极接触或后接触的至少一个掺杂层包括n型材料具有小于衬底的电子亲和力，或具有大于衬底的孔亲合力的p型材料。

138. 发明授权

US09064722B2 Breakdown voltage multiplying integration scheme 有权
标题翻译：击穿电压倍增积分方案
公开(公告)号：US09064722B2
公开(公告)日：2015-06-23
申请号：US13418476
申请日：2012-03-13
申请人： Stephen W. Bedell , Bahman Hekmatshoartabari , Devendra K. Sadana , Ghavam G. Shahidi , Davood Shahrjerdi
发明人： Stephen W. Bedell , Bahman Hekmatshoartabari , Devendra K. Sadana , Ghavam G. Shahidi , Davood Shahrjerdi
IPC分类号： H01L27/088 , H01L21/8252 , H01L27/06 , G06F17/50
CPC分类号： H01L29/7786 , G06F17/5045 , G06F17/5063 , H01L21/6835 , H01L21/8252 , H01L27/0605 , H01L27/088 , H01L27/095 , H01L29/0634 , H01L29/2003 , H01L29/205 , H01L29/402 , H01L29/66462 , H01L29/872 , H01L2221/68363
摘要： A circuit includes a first field effect transistor having a gate, a first drain-source terminal, and a second drain-source terminal; and a second field effect transistor having a gate, a first drain-source terminal, and a second drain-source terminal. The second field effect transistor and the first field effect transistor are of the same type, i.e., both n-channel transistors or both p-channel transistors. The second drain-source terminal of the first field effect transistor is coupled to the first drain-source terminal of the second field effect transistor; and the gate of the second field effect transistor is coupled to the first drain-source terminal of the second field effect transistor. The resulting three-terminal device can be substituted for a single field effect transistor that would otherwise suffer breakdown under proposed operating conditions.
摘要翻译：电路包括具有栅极的第一场效应晶体管，第一漏极 - 源极端子和第二漏极 - 源极端子; 以及具有栅极的第二场效应晶体管，第一漏极 - 源极端子和第二漏极 - 源极端子。第二场效应晶体管和第一场效应晶体管是相同类型的，即n沟道晶体管或两个p沟道晶体管。第一场效应晶体管的第二漏极 - 源极端子耦合到第二场效应晶体管的第一漏极 - 源极端子; 并且第二场效应晶体管的栅极耦合到第二场效应晶体管的第一漏极 - 源极端子。所得到的三端子器件可以替代否则在所提出的工作条件下会损坏的单个场效应晶体管。

139. 发明授权

US08933456B2 Germanium-containing release layer for transfer of a silicon layer to a substrate 有权
标题翻译：含锗释放层，用于将硅层转移到基底
公开(公告)号：US08933456B2
公开(公告)日：2015-01-13
申请号：US13616322
申请日：2012-09-14
申请人： Stephen W. Bedell , Keith E. Fogel , Daniel A. Inns , Jeehwan Kim , Devendra K. Sadana , Katherine L. Saenger
发明人： Stephen W. Bedell , Keith E. Fogel , Daniel A. Inns , Jeehwan Kim , Devendra K. Sadana , Katherine L. Saenger
IPC分类号： H01L29/38 , H01L21/02 , H01L21/762
CPC分类号： H01L21/0262 , H01L21/0245 , H01L21/02532 , H01L21/02576 , H01L21/02579 , H01L21/02664 , H01L21/76254
摘要： A germanium-containing layer is deposited on a single crystalline bulk silicon substrate in an ambient including a level of oxygen partial pressure sufficient to incorporate 1%-50% of oxygen in atomic concentration. The thickness of the germanium-containing layer is preferably limited to maintain some degree of epitaxial alignment with the underlying silicon substrate. Optionally, a graded germanium-containing layer can be grown on, or replace, the germanium-containing layer. An at least partially crystalline silicon layer is subsequently deposited on the germanium-containing layer. A handle substrate is bonded to the at least partially crystalline silicon layer. The assembly of the bulk silicon substrate, the germanium-containing layer, the at least partially crystalline silicon layer, and the handle substrate is cleaved within the germanium-containing layer to provide a composite substrate including the handle substrate and the at least partially crystalline silicon layer. Any remaining germanium-containing layer on the composite substrate is removed.
摘要翻译：含锗层沉积在单一晶体体硅衬底上，包括足以以原子浓度掺入1％-50％的氧的氧分压水平。含锗层的厚度优选被限制以保持与底层硅衬底的一定程度的外延对准。任选地，可以在含锗层上生长或替代含锗层。随后将至少部分结晶的硅层沉积在含锗层上。手柄基板结合到至少部分结晶的硅层。本体硅衬底，含锗层，至少部分结晶的硅层和处理衬底的组件在含锗层内被切割以提供复合衬底，该复合衬底包括处理衬底和至少部分结晶的硅层。去除复合衬底上任何剩余的含锗层。

140. 发明授权

US08916450B2 Method for improving quality of spalled material layers 有权
标题翻译：提高剥离材料层质量的方法
公开(公告)号：US08916450B2
公开(公告)日：2014-12-23
申请号：US13565378
申请日：2012-08-02
申请人： Stephen W. Bedell , Keith E. Fogel , Paul A. Lauro , Ning Li , Devendra K. Sadana , Katherine L. Saenger , Ibrahim Alhomoudi
发明人： Stephen W. Bedell , Keith E. Fogel , Paul A. Lauro , Ning Li , Devendra K. Sadana , Katherine L. Saenger , Ibrahim Alhomoudi
IPC分类号： H01L21/30 , H01L21/46 , H01L21/00
CPC分类号： H01L21/304 , B26F3/00 , C30B33/00 , C30B33/06 , H01L21/2855 , H01L21/32051 , H01L21/321 , H01L31/1892 , Y02E10/50 , Y10T225/10
摘要： Methods for removing a material layer from a base substrate utilizing spalling in which mode III stress, i.e., the stress that is perpendicular to the fracture front created in the base substrate, during spalling is reduced. The substantial reduction of the mode III stress during spalling results in a spalling process in which the spalled material has less surface roughness at one of its' edges as compared to prior art spalling processes in which the mode III stress is present and competes with spalling.
摘要翻译：利用剥落的材料层从基底基板上去除材料层的方法，其中在剥离期间模式III应力即垂直于在基底基板中产生的断裂面的应力减小。在剥落过程中模式III应力的显着降低导致剥落过程，其中剥离材料在其一个边缘处具有较小的表面粗糙度，与现有技术的剥离过程相比，其中存在模式III应力并与剥落相竞争。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式